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* Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos2019-03-081-0/+1
|\ | | | | drivers: mmc: Fix some issues with MMC stack
| * drivers: mmc: Fix some issues with MMC stackTien Hock, Loh2019-03-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | Ensure proper ID register is checked for feature detectionDimitris Papastamos2019-03-041-0/+1
| | | | | | | | | | | | | | | | | | | | SSBS support is determined by checking ID_AA64PFR1_EL1 and not ID_AA64PFR0_EL1. Fixes ARM-Software/tf-issues#679 Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Merge pull request #1851 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz2019-03-041-3/+5
|\ \ | | | | | | Correctly check for support of Address Authentication
| * | Correctly check for support of Address AuthenticationAntonio Nino Diaz2019-03-011-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | Check for both IMPLEMENTATION_DEFINED and Architected algorithms of Address Authentication. Change-Id: I209dcc6087172cfef7baf8d09e0454628f02cbd0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-012-5/+65
|\ \ \ | | | | | | | | Tegra scatter file support
| * | | Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-272-5/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Merge pull request #1849 from loumay-arm/lm/a73_errataAntonio Niño Díaz2019-03-011-0/+2
|\ \ \ \ | |_|/ / |/| | | Cortex-A73: Implement workaround for errata 852427
| * | | Cortex-A73: Implement workaround for errata 852427Louis Mayencourt2019-02-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz2019-03-017-0/+56
|\ \ \ \ | | | | | | | | | | Apply workarounds for errata of Cortex-A53, A55 and A57
| * | | | Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent2019-02-284-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent2019-02-282-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 798797Ambroise Vincent2019-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 778703Ambroise Vincent2019-02-281-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 768277Ambroise Vincent2019-02-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | | | | Merge pull request #1846 from loumay-arm/lm/mpamAntonio Niño Díaz2019-03-011-0/+4
|\ \ \ \ \ | | | | | | | | | | | | MPAM: enable MPAM EL2 traps
| * | | | | MPAM: enable MPAM EL2 trapsLouis Mayencourt2019-02-281-0/+4
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2 traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest. Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | | Merge pull request #1848 from antonio-nino-diaz-arm/an/docsAntonio Niño Díaz2019-03-012-4/+4
|\ \ \ \ \ | |_|/ / / |/| | | | Minor changes to documentation and comments
| * | | | Minor changes to documentation and commentsAntonio Nino Diaz2019-02-282-4/+4
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1839 from loumay-arm/lm/a7x_errataAntonio Niño Díaz2019-02-283-0/+9
|\ \ \ \ | |/ / / |/| | | Cortex-A73/75/76 errata workaround
| * | | Add workaround for errata 1073348 for Cortex-A76Louis Mayencourt2019-02-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * | | Add workaround for errata 1220197 for Cortex-A76Louis Mayencourt2019-02-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * | | Add workaround for errata 764081 of Cortex-A75Louis Mayencourt2019-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * | | Add workaround for errata 855423 of Cortex-A73Louis Mayencourt2019-02-261-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge pull request #1829 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz2019-02-2711-46/+124
|\ \ \ | | | | | | | | Add Pointer Authentication (ARMv8.3-PAuth) support to the TF
| * | | TSP: Enable pointer authentication supportAntonio Nino Diaz2019-02-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.4% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +352 | +0 | +16 | +0 | | | 3.1% | | 15.8% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I6cc1fe0b2345c547dcef66f98758c4eb55fe5ee4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | BL31: Enable pointer authentication supportAntonio Nino Diaz2019-02-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +192 | +1536 | +0 | +0 | | | 0.3% | 3.1% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +1848 | +1536 | +16 | +0 | | | 3.3% | 3.1% | 3.1% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | BL2_AT_EL3: Enable pointer authentication supportAntonio Nino Diaz2019-02-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ The results are valid for the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ BL2_AT_EL3=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | BL2: Enable pointer authentication supportAntonio Nino Diaz2019-02-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 The changes for BL2_AT_EL3 aren't done in this commit. Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | BL1: Enable pointer authentication supportAntonio Nino Diaz2019-02-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 | | | 0.5% | 0.8% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 | | | 3.7% | 0.8% | 7.0% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | Add support for pointer authenticationAntonio Nino Diaz2019-02-274-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz2019-02-273-15/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | | Cleanup context handling libraryAntonio Nino Diaz2019-02-271-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Minor style cleanup. Change-Id: Ief19dece41a989e2e8157859a265701549f6c585 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1Antonio Niño Díaz2019-02-271-1/+0
|\ \ \ \ | |/ / / |/| | | RaspberryPi3 sdhost driver improvement.
| * | | rpi3: sdhost: SDHost driver improvementYing-Chun Liu (PaulLiu)2019-02-271-1/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
* | | Merge pull request #1831 from antonio-nino-diaz-arm/an/sccdAntonio Niño Díaz2019-02-274-15/+29
|\ \ \ | |/ / |/| | Disable processor Cycle Counting in Secure state
| * | Disable processor Cycle Counting in Secure stateAntonio Nino Diaz2019-02-184-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a system with ARMv8.5-PMU implemented: - If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting in Secure state in PMCCNTR. - If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in Secure state in PMCCNTR_EL0. So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64) or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure as any EL can change that value. Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz2019-02-222-0/+5
|\ \ \ | | | | | | | | Update documentation for STM32MP1 and add Cortex-M4 support
| * | | stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier2019-02-202-0/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | Merge pull request #1835 from jts-arm/renameAntonio Niño Díaz2019-02-223-43/+43
|\ \ \ | | | | | | | | Apply official names to new Arm Neoverse cores
| * | | Rename Cortex-Helios to Neoverse E1John Tsichritzis2019-02-191-8/+8
| | | | | | | | | | | | | | | | | | | | Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | Rename Cortex-Helios filenames to Neoverse E1John Tsichritzis2019-02-191-0/+0
| | | | | | | | | | | | | | | | | | | | Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | Rename Cortex-Ares to Neoverse N1John Tsichritzis2019-02-191-13/+13
| | | | | | | | | | | | | | | | | | | | Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
| * | | Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis2019-02-191-0/+0
| | |/ | |/| | | | | | | | | | Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | Merge pull request #1828 from uarif1/masterAntonio Niño Díaz2019-02-214-6/+39
|\ \ \ | |_|/ |/| | Introduce Versatile Express FVP platform to arm-trusted-firmware.
| * | plat/arm: Support for Cortex A5 in FVP Versatile Express platformUsama Arif2019-02-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A5 doesnt support VFP, Large Page addressing and generic timer which are addressed in this patch. The device tree for Cortex a5 is also included. Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678 Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | Division functionality for cores that dont have divide hardware.Usama Arif2019-02-191-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly as well as include appropriate files for software divison. The software division algorithm is a modified version obtained from: http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652 Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | ARMv7: support non-LPAE mapping (not xlat_v2)Etienne Carriere2019-02-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support 32bit descriptor MMU table. This is required by ARMv7 architectures that do not support the Large Page Address Extensions. nonlpae_tables.c source file is dumped from the OP-TEE project: core_mmu_armv7.c and related header files. Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Usama Arif <usama.arif@arm.com>
| * | Rename PLAT_ARM_BL31_RUN_UART* variableUsama Arif2019-02-181-4/+4
| |/ | | | | | | | | | | | | | | The variable is renamed to PLAT_ARM_RUN_UART as the UART is used outside BL31 as well. Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a Signed-off-by: Usama Arif <usama.arif@arm.com>
* | Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2Antonio Niño Díaz2019-02-191-5/+17
|\ \ | |/ |/| Update macro to check need for CVE-2017-5715 mitigation
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