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| author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-02-19 14:01:55 +0000 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-02-19 14:02:34 +0000 |
| commit | 11088e392468a2aade66e1593a4cce8d5b1ff82f (patch) | |
| tree | d785c148eb681411d62edc9174380d7a897f8560 /include | |
| parent | fd4bb0ad4b2403156c62dea2ae7c1e02c19e79bf (diff) | |
| download | platform_external_arm-trusted-firmware-11088e392468a2aade66e1593a4cce8d5b1ff82f.tar.gz platform_external_arm-trusted-firmware-11088e392468a2aade66e1593a4cce8d5b1ff82f.tar.bz2 platform_external_arm-trusted-firmware-11088e392468a2aade66e1593a4cce8d5b1ff82f.zip | |
Rename Cortex-Helios to Neoverse E1
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_e1.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h index 0c11a9a4c..708460480 100644 --- a/include/lib/cpus/aarch64/neoverse_e1.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -4,28 +4,28 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H #include <lib/utils_def.h> -#define CORTEX_HELIOS_MIDR U(0x410FD060) +#define NEOVERSE_E1_MIDR U(0x410FD060) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) -#endif /* CORTEX_HELIOS_H */ +#endif /* NEOVERSE_E1_H */ |