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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-25 11:37:38 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:21:06 +0000 |
| commit | 5cc8c7ba1b24ace2ef7345e96d933141f3609817 (patch) | |
| tree | f9ab8df5738d6245ca1b4e4fd7c5af143c223f2f /include | |
| parent | 508d71108a06c7fce2eeef78659b9b7739cee6eb (diff) | |
| download | platform_external_arm-trusted-firmware-5cc8c7ba1b24ace2ef7345e96d933141f3609817.tar.gz platform_external_arm-trusted-firmware-5cc8c7ba1b24ace2ef7345e96d933141f3609817.tar.bz2 platform_external_arm-trusted-firmware-5cc8c7ba1b24ace2ef7345e96d933141f3609817.zip | |
Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.
Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 5779d7bab..52ab92ef6 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -18,6 +18,8 @@ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ |