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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-19 10:04:00 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-19 10:04:00 +0000 |
| commit | 41bd188266d78807bf4b78d7ef31c83fa51a58cd (patch) | |
| tree | 0e4256852c1a1b3b325a19b7783c82ec85d5b886 /include | |
| parent | fa233ac9d435905d2717a9880cfb3a1671e37134 (diff) | |
| parent | ff6f62e105c6553a7b64a8c3c2165b53f7250300 (diff) | |
| download | platform_external_arm-trusted-firmware-41bd188266d78807bf4b78d7ef31c83fa51a58cd.tar.gz platform_external_arm-trusted-firmware-41bd188266d78807bf4b78d7ef31c83fa51a58cd.tar.bz2 platform_external_arm-trusted-firmware-41bd188266d78807bf4b78d7ef31c83fa51a58cd.zip | |
Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2
Update macro to check need for CVE-2017-5715 mitigation
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cpu_macros.S | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index b907668b3..044aacaf4 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #define CPU_MACROS_S #include <arch.h> +#include <assert_macros.S> #include <lib/cpus/errata_report.h> #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ @@ -263,11 +264,22 @@ mrs \_reg, id_aa64pfr0_el1 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH /* - * If the field equals to 1 then branch targets trained in one - * context cannot affect speculative execution in a different context. + * If the field equals 1, branch targets trained in one context cannot + * affect speculative execution in a different context. + * + * If the field equals 2, it means that the system is also aware of + * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we + * expect users of the registers to do the right thing. + * + * Only apply mitigations if the value of this field is 0. */ - cmp \_reg, #1 - beq \_label +#if ENABLE_ASSERTIONS + cmp \_reg, #3 /* Only values 0 to 2 are expected */ + ASM_ASSERT(lo) +#endif + + cmp \_reg, #0 + bne \_label .endm /* |