diff options
| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-22 13:05:37 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-22 13:05:37 +0000 |
| commit | 3f995f3078a9a22c5079e3d05995e26173ff6499 (patch) | |
| tree | 3efcf4b5aeb8d51b4f7d1117454d38d77c654556 /include | |
| parent | 5ba32a7660051464ed1d56129adf2606db54b5e3 (diff) | |
| parent | 11088e392468a2aade66e1593a4cce8d5b1ff82f (diff) | |
| download | platform_external_arm-trusted-firmware-3f995f3078a9a22c5079e3d05995e26173ff6499.tar.gz platform_external_arm-trusted-firmware-3f995f3078a9a22c5079e3d05995e26173ff6499.tar.bz2 platform_external_arm-trusted-firmware-3f995f3078a9a22c5079e3d05995e26173ff6499.zip | |
Merge pull request #1835 from jts-arm/rename
Apply official names to new Arm Neoverse cores
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_ares.h | 35 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_e1.h (renamed from include/lib/cpus/aarch64/cortex_helios.h) | 16 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 35 |
3 files changed, 43 insertions, 43 deletions
diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h deleted file mode 100644 index cfc36e473..000000000 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H - -#include <lib/utils_def.h> - -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) - -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) - -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) - -/* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 - -#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/neoverse_e1.h index 0c11a9a4c..708460480 100644 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -4,28 +4,28 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H #include <lib/utils_def.h> -#define CORTEX_HELIOS_MIDR U(0x410FD060) +#define NEOVERSE_E1_MIDR U(0x410FD060) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) -#endif /* CORTEX_HELIOS_H */ +#endif /* NEOVERSE_E1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 000000000..908993e45 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H + +#include <lib/utils_def.h> + +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) + +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) + +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* NEOVERSE_N1_H */ |