diff options
| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-28 10:19:24 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 10:19:24 +0000 |
| commit | 64503b2f81bbd12051d8e0fd065a5a0b0c38bd2a (patch) | |
| tree | 89a0e3acb4e84aabc69b66f8f5f9e16dd9358a81 /include | |
| parent | 1baa28bb2dc79f23c550d67604324afd222221c3 (diff) | |
| parent | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 (diff) | |
| download | platform_external_arm-trusted-firmware-64503b2f81bbd12051d8e0fd065a5a0b0c38bd2a.tar.gz platform_external_arm-trusted-firmware-64503b2f81bbd12051d8e0fd065a5a0b0c38bd2a.tar.bz2 platform_external_arm-trusted-firmware-64503b2f81bbd12051d8e0fd065a5a0b0c38bd2a.zip | |
Merge pull request #1839 from loumay-arm/lm/a7x_errata
Cortex-A73/75/76 errata workaround
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch64/arch.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a73.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 6 |
3 files changed, 9 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index b9d1f9fae..1032d9ae9 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -251,6 +251,7 @@ #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) #define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 3b401805a..61b2b737b 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -31,4 +31,6 @@ #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) +#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 + #endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 5779d7bab..c2af8cad9 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -18,9 +18,15 @@ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) |