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| author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-02-19 13:49:06 +0000 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-02-19 13:50:07 +0000 |
| commit | da6d75a0e7fc262ee3085cf0b6c164063408042f (patch) | |
| tree | b61edd6f7cee25408eee1a960b5a3c5539ec5c5d /include | |
| parent | b04ea14b790b7899e73c34f6c678d90efdb9f9fc (diff) | |
| download | platform_external_arm-trusted-firmware-da6d75a0e7fc262ee3085cf0b6c164063408042f.tar.gz platform_external_arm-trusted-firmware-da6d75a0e7fc262ee3085cf0b6c164063408042f.tar.bz2 platform_external_arm-trusted-firmware-da6d75a0e7fc262ee3085cf0b6c164063408042f.zip | |
Rename Cortex-Ares to Neoverse N1
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index cfc36e473..908993e45 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -1,30 +1,30 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H #include <lib/utils_def.h> -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 @@ -32,4 +32,4 @@ #define CPUPOR_EL3 S3_6_C15_C8_2 #define CPUPMR_EL3 S3_6_C15_C8_3 -#endif /* CORTEX_ARES_H */ +#endif /* NEOVERSE_N1_H */ |