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| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-02-21 16:25:37 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-02-28 09:56:58 +0000 |
| commit | a6cc661016a32494f1bbe7b7377bc9a549f297b4 (patch) | |
| tree | 00193c7ee7a034defebc8a9f26aba8107270d4bc /include | |
| parent | 1afeee92751840e4352201c9b3e99056a6fe5c9d (diff) | |
| download | platform_external_arm-trusted-firmware-a6cc661016a32494f1bbe7b7377bc9a549f297b4.tar.gz platform_external_arm-trusted-firmware-a6cc661016a32494f1bbe7b7377bc9a549f297b4.tar.bz2 platform_external_arm-trusted-firmware-a6cc661016a32494f1bbe7b7377bc9a549f297b4.zip | |
Cortex-A55: Implement workaround for erratum 778703
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 5db0f008f..13f209994 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -18,13 +18,23 @@ #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) +/******************************************************************************* + * CPU Identification register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 + +#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) + /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) |