aboutsummaryrefslogtreecommitdiffstats
path: root/lib/cpus/aarch64
Commit message (Collapse)AuthorAgeFilesLines
* rainier: remove cpu workaround for errata 1542419Manoj Kumar2021-02-051-89/+1
| | | | | | | | This patch removes the Neoverse N1 CPU errata workaround for bug 1542419 as the bug is not present in Rainier R0P0 core. Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* Workaround for Cortex N1 erratum 1946160johpow012021-01-131-1/+64
| | | | | | | | | | | | | | | Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
* Workaround for Cortex A78 erratum 1951500johpow012021-01-131-0/+60
| | | | | | | | | | | | | Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
* Workaround for Cortex A78 erratum 1941498johpow012021-01-121-2/+36
| | | | | | | | | | | | Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
* Workaround for Cortex A76 erratum 1946160johpow012020-12-181-0/+61
| | | | | | | | | | | | | | Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
* Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino2020-11-303-16/+138
| | | | | | | Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
* Revert workaround for A77 erratum 1800714johpow012020-11-121-35/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
* Revert workaround for A76 erratum 1800710johpow012020-11-121-35/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
* Workaround for Cortex A77 erratum 1925769johpow012020-10-071-0/+35
| | | | | | | | | | | | | Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
* Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into ↵Madhukar Pappireddy2020-10-062-45/+45
|\ | | | | | | | | | | | | | | integration * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE
| * Rename Neoverse Zeus to Neoverse V1Jimmy Brisson2020-10-051-24/+24
| | | | | | | | | | Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
| * Rename Cortex Hercules AE to Cortex 78 AEJimmy Brisson2020-10-051-21/+21
| | | | | | | | | | Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Workaround for Cortex A76 erratum 1868343johpow012020-10-031-40/+52
|/ | | | | | | | | | | | | | | | | Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
* Merge "Workaround for Cortex A77 erratum 1508412" into integrationMadhukar Pappireddy2020-09-291-0/+70
|\
| * Workaround for Cortex A77 erratum 1508412laurenw-arm2020-09-251-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
* | Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integrationManish Pandey2020-09-291-0/+218
|\ \ | | | | | | | | | | | | | | | | | | * changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs
| * | lib/cpus: add support for Morello Rainier CPUsManoj Kumar2020-09-281-0/+218
| |/ | | | | | | | | | | | | | | | | This patch adds CPU support for the Rainier CPU which is derived from Neoverse N1 r4p0 CPU and implements the Morello capability architecture. Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* / arm_fpga: Add support for unknown MPIDsJavier Almansa Sobrino2020-09-252-10/+129
|/ | | | | | | | | | | | | | This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
* Workaround for Neoverse N1 erratum 1868343johpow012020-09-101-0/+38
| | | | | | | | | | | | | | Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
* Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" ↵Manish Pandey2020-09-032-10/+41
|\ | | | | | | into integration
| * lib: cpu: Check SCU presence in DSU before accessing DSU registersPramod Kumar2020-09-022-10/+41
| | | | | | | | | | | | | | | | | | | | | | | | The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
* | cpus: denver: skip DCO enable/disable for recent SKUsVarun Wadekar2020-08-311-4/+14
| | | | | | | | | | | | | | | | DCO is not supported by the SKUs released after MIDR_PN4. This patch skips enabling or disabling the DCO on these SKUs. Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | lib: cpus: denver: add MIDR PN9 variantHemant Nigam2020-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3
* | cpus: denver: introduce macro to declare cpu_opsVarun Wadekar2020-08-311-62/+19
| | | | | | | | | | | | | | | | This patch introduces a macro to declare cpu_op for all Denver SKUs. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977
* | lib: cpus: sanity check pointers before useVarun Wadekar2020-08-241-0/+24
|/ | | | | | | | | | | | | The cpu_ops structure contains a lot of function pointers. It is a good idea to verify that the function pointer is not NULL before executing it. This patch sanity checks each pointer before use to prevent any unforeseen crashes. These checks have been enabled for debug builds only. Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* lib/cpus: Report AT speculative erratum workaroundManish V Badarkhe2020-08-185-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | Reported the status (applies, missing) of AT speculative workaround which is applicable for below CPUs. +---------+--------------+ | Errata | CPU | +=========+==============+ | 1165522 | Cortex-A76 | +---------+--------------+ | 1319367 | Cortex-A72 | +---------+--------------+ | 1319537 | Cortex-A57 | +---------+--------------+ | 1530923 | Cortex-A55 | +---------+--------------+ | 1530924 | Cortex-A53 | +---------+--------------+ Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT' if AT speculative errata workaround is enabled for any of the above CPUs using 'ERRATA_*' CPU specific build macro. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b
* lib: cpus: denver: add some MIDR valuesAlex Van Brunt2020-08-081-0/+28
| | | | | | | | | This patch adds support for additional Denver MIDRs to cover all the current SKUs. Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* lib: cpus: denver: mark exception vectors as privateVarun Wadekar2020-08-081-2/+0
| | | | | | | | | This patch removes the 'workaround_bpflush_runtime_exceptions' exception vector table base address from the globals list as it gets used only by the Denver CPU implementation. Change-Id: I6ef94989f6dc4535d464493cc8621d32795ee1f6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Revert workaround for Neoverse N1 erratum 1800710johpow012020-07-231-35/+0
| | | | | | | | | | | | | | | This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
* Workaround for Neoverse N1 erratum 1800710johpow012020-06-251-0/+35
| | | | | | | | | | | | | Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
* Workaround for Cortex A77 erratum 1800714johpow012020-06-251-2/+61
| | | | | | | | | | | | | | | | | Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad
* Workaround for Cortex A76 erratum 1800710johpow012020-06-221-0/+35
| | | | | | | | | | | | | Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
* Workaround for Cortex A76 erratum 1791580johpow012020-06-221-0/+33
| | | | | | | | | | | | | Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925
* cpus: denver: disable cycle counter when event counting is prohibitedVarun Wadekar2020-06-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the PMCR_EL0 to be saved in non-secure context. This patch disables cycle counter when event counting is prohibited immediately on entering the secure world to avoid leaking useful information about the PMU counters. The context saving code later saves the value of PMCR_EL0 to the non-secure world context. Verified with 'PMU Leakage' test suite. ******************************* Summary ******************************* > Test suite 'PMU Leakage' Passed ================================= Tests Skipped : 2 Tests Passed : 2 Tests Failed : 0 Tests Crashed : 0 Total tests : 4 ================================= Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875
* Rename Cortex-Hercules to Cortex-A78Jimmy Brisson2020-06-012-45/+45
| | | | | Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* Rename Cortex Hercules Files to Cortex A78Jimmy Brisson2020-06-011-2/+2
| | | | | | | This should allow git to easily track file moves Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327
* cpus: denver: fixup register used to store return addressKalyani Chidambaram2020-03-091-4/+4
| | | | | | | | | | | | The denver_enable_dco and denver_disable_dco use register X3 to store the return address. But X3 gets over-written by other functions, downstream. This patch stores the return address to X18 instead, to fix this anomaly. Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* Merge "Add Matterhorn CPU lib" into integrationjoanna.farley2020-02-211-0/+77
|\
| * Add Matterhorn CPU libJimmy Brisson2020-02-181-0/+77
| | | | | | | | | | | | | | Also update copyright statements Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Merge "Add CPULib for Klein Core" into integrationjoanna.farley2020-02-211-0/+77
|\|
| * Add CPULib for Klein CoreJimmy Brisson2020-02-181-0/+77
| | | | | | | | | | Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | cpus: higher performance non-cacheable load forwardingVarun Wadekar2020-02-201-0/+12
|/ | | | | | | | | | | | | | | The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Neovers N1: added support to update presence of External LLCManish Pandey2020-01-271-0/+7
| | | | | | | | | | | | CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
* Prevent speculative execution past ERETAnthony Steinhauser2020-01-223-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
* Workaround for Hercules erratum 1688305Madhukar Pappireddy2019-12-231-11/+54
| | | | | | | | | | Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Fix white space errors + remove #if definedlaurenw-arm2019-10-241-7/+5
| | | | | | | | Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
* Merge "Neoverse N1 Errata Workaround 1542419" into integrationSoby Mathew2019-10-072-1/+105
|\
| * Neoverse N1 Errata Workaround 1542419laurenw-arm2019-10-042-1/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
* | Introducing support for Cortex-A65AEImre Kis2019-10-031-0/+81
| | | | | | | | | | Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com>
* | Introducing support for Cortex-A65Imre Kis2019-10-021-0/+81
|/ | | | | Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 15:25:15 +0000