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* Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4Alistair Delva2021-02-161560-20986/+109550
|\ | | | | | | | | | | | | | | Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611 MUST ONLY BE SUBMITTED BY AUTOMERGER Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
| * Merge branch 'aosp/upstream-master' into HEADandroid-s-preview-1Alistair Delva2021-02-151560-20986/+109550
|/| | | | | | | | | | | | | | | | | | | This keeps the bl31 interface change reverted which still has not been fixed in upstream U-Boot for rockchip devices. Test: CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rk3399 \ DEBUG=0 ERROR_DEPRECATED=1 bl31 Signed-off-by: Alistair Delva <adelva@google.com> Change-Id: I7c3972a7b767715efb05593096d5d92dba14c609
| * Merge "spmd: ensure SIMD context is saved/restored on SPMC entry/exit" into ↵Olivier Deprez2021-02-121-0/+7
| |\ | | | | | | | | | integration
| | * spmd: ensure SIMD context is saved/restored on SPMC entry/exitOlivier Deprez2021-02-121-0/+7
| | | | | | | | | | | | | | | Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I8ed58ec5f97e05d91451020a2739464bb8e428b3
| * | Merge "nxp: added the makefile helper macros" into integrationManish Pandey2021-02-121-0/+11
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| | * nxp: added the makefile helper macrosPankaj Gupta2021-02-121-0/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP specifc macro SET_NXP_MAKE_FLAG is added. NXP has pool of multiple IPs. This macro helps: - In soc.mk, this macro help the selected IP source files to be included for that SoC. -- The set of IPs required for one NXP SoC is different to the set of IPs required by another NXP SoC. - For the same SoC, -- For one feature, the IP may be required in both BL2 and BL31. -- Without the above feature, that IP may be required in one. This macro help in selecting the inclusion of source and header files to: --- BL2 only --- BL31 only --- COMM (used by BL2 and BL31) Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765
| * Merge "plat/arm: juno: Refactor juno_getentropy()" into integrationbipin.ravi2021-02-113-51/+51
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| | * plat/arm: juno: Refactor juno_getentropy()Andre Przywara2021-02-113-51/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we use the Juno's TRNG hardware entropy source to initialise the stack canary. The current function allows to fill a buffer of any size, but we will actually only ever request 16 bytes, as this is what the hardware implements. Out of this, we only need at most 64 bits for the canary. In preparation for the introduction of the SMCCC TRNG interface, we can simplify this Juno specific interface by making it compatible with the generic one: We just deliver 64 bits of entropy on each call. This reduces the complexity of the code. As the raw entropy register readouts seem to be biased, it makes sense to do some conditioning inside the juno_getentropy() function already. Also initialise the TRNG hardware, if not already done. Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | Merge "bl32: Enable TRNG service build" into integrationMark Dykes2021-02-111-0/+5
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| | * bl32: Enable TRNG service buildAndre Przywara2021-02-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Trusted Random Number Generator service is using the standard SMC service dispatcher, running in BL31. For that reason we list the files implementing the service in bl31.mk. However when building for a 32-bit TF-A runtime, sp_min.mk is the Makefile snippet used, so we have to add the files into there as well. This fixes 32-bit builds of platforms that provide the TRNG service. Change-Id: I8be61522300d36477a9ee0a9ce159a140390b254 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | Merge "plat/arm/rdn2: update TZC base address" into integrationMadhukar Pappireddy2021-02-111-1/+1
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| | * | plat/arm/rdn2: update TZC base addressVijayenthiran Subramaniam2021-02-111-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | Update TZC base address to align with the recent changes in the platform memory map. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a
| * | Merge changes from topic "mp/strto_libc" into integrationMadhukar Pappireddy2021-02-117-5/+515
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: libc: Import strtoull from FreeBSD project libc: Import strtoll from FreeBSD project libc: Import strtoul from FreeBSD project libc: Import strtol from FreeBSD project
| | * | libc: Import strtoull from FreeBSD projectMadhukar Pappireddy2021-02-034-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| | * | libc: Import strtoll from FreeBSD projectMadhukar Pappireddy2021-02-034-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| | * | libc: Import strtoul from FreeBSD projectMadhukar Pappireddy2021-02-034-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| | * | libc: Import strtol from FreeBSD projectMadhukar Pappireddy2021-02-034-5/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | Merge "morello: Modify morello_plat_info structure" into integrationMadhukar Pappireddy2021-02-112-13/+19
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| | * | morello: Modify morello_plat_info structureManoj Kumar2021-02-082-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structure has been modified to specify the memory size in bytes instead of Gigabytes. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7
| * | | Merge "services: TRNG: Fix -O0 compilation" into integrationbipin.ravi2021-02-101-0/+2
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| | * | | services: TRNG: Fix -O0 compilationAndre Przywara2021-02-101-0/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to check for the presence of the TRNG service relies on toolchain garbage collection, which is not enabled with -O0. Add #ifdef guards around the call to the TRNG service handler to cover builds without optimisation as well. Change-Id: I08ece2005ea1c8fa96afa13904a851dec6b24216 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | Merge changes from topic "GIC-work" into integrationMadhukar Pappireddy2021-02-105-4/+84
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm: fvp: Protect GICR frames for fused/unused cores doc: Build option to protect GICR frame plat/arm: fvp: Do not map GIC region in BL1 and BL2
| | * | | plat/arm: fvp: Protect GICR frames for fused/unused coresManish V Badarkhe2021-02-094-3/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BLs are mapping the GIC memory region as read-write for all cores on boot-up. This opens up the security hole where the active core can write the GICR frame of fused/inactive core. To avoid this issue, disable the GICR frame of all inactive cores as below: 1. After primary CPU boots up, map GICR region of all cores as read-only. 2. After primary CPU boots up, map its GICR region as read-write and initialize its redistributor interface. 3. After secondary CPU boots up, map its GICR region as read-write and initialize its redistributor interface. 4. All unused/fused core's redistributor regions remain read-only and write attempt to such protected regions results in an exception. As mentioned above, this patch offers only the GICR memory-mapped region protection considering there is no facility at the GIC IP level to avoid writing the redistributor area. These changes are currently done in BL31 of Arm FVP and guarded under the flag 'FVP_GICR_REGION_PROTECTION'. As of now, this patch is tested manually as below: 1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core. 2. Verify data abort triggered by manually updating the ‘GICR_CTLR’ register of core 1’s(fused) redistributor from core 0(active). Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| | * | | doc: Build option to protect GICR frameManish V Badarkhe2021-02-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added a build option 'FVP_GICR_REGION_PROTECTION' to make redistributor frame of fused/unused cores as read only. Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| | * | | plat/arm: fvp: Do not map GIC region in BL1 and BL2Manish V Badarkhe2021-02-091-1/+5
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GIC memory region is not getting used in BL1 and BL2. Hence avoid its mapping in BL1 and BL2 that freed some page table entries to map other memory regions in the future. Retains mapping of CCN interconnect region in BL1 and BL2 overlapped with the GIC memory region. Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * | | Merge "fdts: use scmi_dvfs clock index 1 for cores 4-7" into integrationSandrine Bailleux2021-02-091-4/+4
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| | * | fdts: use scmi_dvfs clock index 1 for cores 4-7Usama Arif2021-02-091-4/+4
| |/ / | | | | | | | | | | | | | | | | | | This allows Matterhorn cores to operate at their optimal OPPs. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116
| * | Merge "ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask" into integrationMadhukar Pappireddy2021-02-051-2/+2
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| | * | ddr: stm32mp1_ddr: correct SELFREF_TO_X32 maskYann Gautier2021-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is wrong. This field is from bit 16 to 23. Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | Merge "rainier: remove cpu workaround for errata 1542419" into integrationLauren Wehrmeister2021-02-052-91/+1
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| | * | | rainier: remove cpu workaround for errata 1542419Manoj Kumar2021-02-052-91/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the Neoverse N1 CPU errata workaround for bug 1542419 as the bug is not present in Rainier R0P0 core. Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
| * | | Merge "Add TRNG Firmware Interface service" into integrationAndré Przywara2021-02-0513-6/+462
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| | * | Add TRNG Firmware Interface serviceJimmy Brisson2021-02-0513-6/+462
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the TRNG Firmware Interface Service to the standard service dispatcher. This includes a method for dispatching entropy requests to platforms and includes an entropy pool implementation to avoid dropping any entropy requested from the platform. Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | Merge changes from topic "RD_INFRA_POWER_MODING" into integrationLauren Wehrmeister2021-02-033-6/+7
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm/board: enable AMU for RD-N2 plat/arm/board: enable AMU for RD-V1 plat/arm/sgi: allow all PSCI callbacks on RD-V1
| | * | plat/arm/board: enable AMU for RD-N2Pranav Madhu2021-01-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMU counters are used for monitoring the CPU performance. RD-N2 platform has architected AMU available for each core. Enable the use of AMU by non-secure OS for supporting the use of counters for processor performance control (ACPI CPPC). Change-Id: I5cc749cf63c18fc5c7563dd754c2f42990a97e23 Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
| | * | plat/arm/board: enable AMU for RD-V1Pranav Madhu2021-01-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMU counters are used for monitoring the CPU performance. RD-V1 platform has architected AMU available for each core. Enable the use of AMU by non-secure OS for supporting the use of counters for processor performance control (ACPI CPPC). Change-Id: I4003d21407953f65b3ce99eaa8f496d6052546e0 Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
| | * | plat/arm/sgi: allow all PSCI callbacks on RD-V1Pranav Madhu2021-01-291-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the PSCI platform callbacks were restricted on RD-V1 platform because the idle was not functional. Now that it is functional, remove all the restrictions on the use PSCI platform callbacks. Change-Id: I4cb97cb54de7ee166c30f28df8fea653b6b425c7 Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
| * | | Merge "plat/arm:juno: fix parallel build issue for romlib config" into ↵Manish Pandey2021-02-031-2/+2
| |\ \ \ | | | | | | | | | | | | | | | integration
| | * | | plat/arm:juno: fix parallel build issue for romlib configZelalem2021-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building TF-A with USE_ROMLIB=1 and -j make options, the build fails with the following error: make[1]: *** No rule to make target '/build/juno/debug/romlib/romlib.bin', needed by 'bl1_romlib.bin'. This patch fixes that issue. Signed-off-by: Zelalem <zelalem.aweke@arm.com> Change-Id: I0cca416f3f50f400759164e0735c2d6b520ebf84
| * | | | Merge "product/tc0: Enable Theodul DSU in TC platform" into integrationManish Pandey2021-02-036-42/+145
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| | * | | product/tc0: Enable Theodul DSU in TC platformAvinash Mehta2021-02-036-42/+145
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase the core count and add respective entries in DTS. Add Klein assembly file to cpu sources for core initialization. Add SCMI entries for cores. Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
| * | | Merge "Fix exception handlers in BL31: Use DSB to synchronize pending EA" ↵Madhukar Pappireddy2021-02-024-7/+103
| |\ \ \ | | | | | | | | | | | | | | | into integration
| | * | | Fix exception handlers in BL31: Use DSB to synchronize pending EAMadhukar Pappireddy2021-01-294-7/+103
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs which do not implement RAS, use DSB as a barrier to synchronize pending external aborts at the entry and exit of exception handlers. This is needed to isolate the SErrors to appropriate context. However, this introduces an unintended side effect as discussed in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440 A summary of the side effect and a quick workaround is provided as part of this patch and summarized here: The explicit DSB at the entry of various exception vectors in BL31 for handling exceptions from lower ELs can inadvertently trigger an SError exception in EL3 due to pending asyncrhonouus aborts in lower ELs. This will end up being handled by serror_sp_elx in EL3 which will ultimately panic and die. The way to workaround is to update a flag to indicate if the exception truly came from EL3. This flag is allocated in the cpu_context structure. This is not a bullet proof solution to the problem at hand because we assume the instructions following "isb" that help to update the flag (lines 100-102 & 139-141) execute without causing further exceptions. Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | Merge changes from topic "marvell-armada-docs" into integrationManish Pandey2021-02-021-26/+46
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image docs: marvell: Fix description of flash-image.bin image docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board docs: marvell: Move Supported Marvell platforms to PLAT build option
| | * | | docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example ↵Pali Rohár2021-02-021-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | how to build production release of Marvell firmware image ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous mentioned example. It produced debug binary with custom log level, which was not described. So rather replace this duplicate build example by a full example with all steps how to build production release of Marvell firmware image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52
| | * | | docs: marvell: Fix description of flash-image.bin imagePali Rohár2021-02-021-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6
| | * | | docs: marvell: Add information into CLOCKSPRESET option how to identify CPU ↵Pali Rohár2021-02-021-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | frequency Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1
| | * | | docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra boardPali Rohár2021-02-021-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a
| | * | | docs: marvell: Move Supported Marvell platforms to PLAT build optionPali Rohár2021-02-021-9/+12
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | Reformat list of boards, remove unsupported OcteonTX2 and mention supported Turris MOX board. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563
| * | | Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integrationManish Pandey2021-02-022-3/+9
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile docs: marvell: Update info about BOOTDEV=SATA
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