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| author | Varun Wadekar <vwadekar@nvidia.com> | 2020-05-24 16:26:22 -0700 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2020-06-09 19:54:29 +0000 |
| commit | c5c1af0db66fe09558f3158c5af3d5a7ca866140 (patch) | |
| tree | 20f0d1e6066bc1a136e41aea7fa7d44feb622cea /lib/cpus/aarch64 | |
| parent | 02383c28da9aedc215d336e512e29168056f3b79 (diff) | |
| download | platform_external_arm-trusted-firmware-c5c1af0db66fe09558f3158c5af3d5a7ca866140.tar.gz platform_external_arm-trusted-firmware-c5c1af0db66fe09558f3158c5af3d5a7ca866140.tar.bz2 platform_external_arm-trusted-firmware-c5c1af0db66fe09558f3158c5af3d5a7ca866140.zip | |
cpus: denver: disable cycle counter when event counting is prohibited
The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the
PMCR_EL0 to be saved in non-secure context.
This patch disables cycle counter when event counting is prohibited
immediately on entering the secure world to avoid leaking useful
information about the PMU counters. The context saving code later
saves the value of PMCR_EL0 to the non-secure world context.
Verified with 'PMU Leakage' test suite.
******************************* Summary *******************************
> Test suite 'PMU Leakage'
Passed
=================================
Tests Skipped : 2
Tests Passed : 2
Tests Failed : 0
Tests Crashed : 0
Total tests : 4
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/denver.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index e260f8d28..c050b02a7 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,6 +34,12 @@ vector_base workaround_bpflush_runtime_exceptions .macro apply_workaround stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + /* Disable cycle counter when event counting is prohibited */ + mrs x1, pmcr_el0 + orr x0, x1, #PMCR_EL0_DP_BIT + msr pmcr_el0, x0 + isb + /* ------------------------------------------------- * A new write-only system register where a write of * 1 to bit 0 will cause the indirect branch predictor |