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| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2019-12-18 15:56:27 -0600 |
|---|---|---|
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2019-12-23 11:21:16 -0600 |
| commit | 83e955241aafb4bfac8f2b6db402d7bfc34a5167 (patch) | |
| tree | 35a44b43b9f5f73e43ec8040107ba63d419dfdf7 /lib/cpus/aarch64 | |
| parent | 86ed8953b5233570c49a58060d424b7863d3a396 (diff) | |
| download | platform_external_arm-trusted-firmware-83e955241aafb4bfac8f2b6db402d7bfc34a5167.tar.gz platform_external_arm-trusted-firmware-83e955241aafb4bfac8f2b6db402d7bfc34a5167.tar.bz2 platform_external_arm-trusted-firmware-83e955241aafb4bfac8f2b6db402d7bfc34a5167.zip | |
Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.
Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/cortex_hercules.S | 65 |
1 files changed, 54 insertions, 11 deletions
diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S index 4e048145f..a23919626 100644 --- a/lib/cpus/aarch64/cortex_hercules.S +++ b/lib/cpus/aarch64/cortex_hercules.S @@ -16,12 +16,49 @@ #error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + +/* -------------------------------------------------- + * Errata Workaround for Hercules Erratum 1688305. + * This applies to revision r0p0 and r1p0 of Hercules. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_hercules_1688305_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1688305 + cbz x0, 1f + mrs x1, CORTEX_HERCULES_ACTLR2_EL1 + orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1 + msr CORTEX_HERCULES_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_hercules_1688305_wa + +func check_errata_1688305 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1688305 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-Hercules * ------------------------------------------------- */ -#if ENABLE_AMU func cortex_hercules_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_HERCULES_1688305 + mov x0, x18 + bl errata_hercules_1688305_wa +#endif + +#if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT @@ -39,11 +76,11 @@ func cortex_hercules_reset_func /* Enable group1 counters */ mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 - isb +#endif - ret + isb + ret x19 endfunc cortex_hercules_reset_func -#endif /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -66,6 +103,18 @@ endfunc cortex_hercules_core_pwr_dwn */ #if REPORT_ERRATA func cortex_hercules_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305 + + ldp x8, x30, [sp], #16 ret endfunc cortex_hercules_errata_report #endif @@ -89,12 +138,6 @@ func cortex_hercules_cpu_reg_dump ret endfunc cortex_hercules_cpu_reg_dump -#if ENABLE_AMU -#define HERCULES_RESET_FUNC cortex_hercules_reset_func -#else -#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC -#endif - declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \ - HERCULES_RESET_FUNC, \ + cortex_hercules_reset_func, \ cortex_hercules_core_pwr_dwn |