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* pmf: Make the runtime instrumentation work on AArch32Bence Szépkúti2019-12-171-0/+3
| | | | | | | | | | | Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
* SiP: Don't validate entrypoint if state switch is impossibleBence Szépkúti2019-12-173-13/+16
| | | | | | | | Switching execution states is only possible if EL3 is AArch64. As such there is no need to validate the entrypoint on AArch32 builds. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608
* Merge "allwinner: Fix incorrect ARISC code patch offset check" into integrationSoby Mathew2019-12-133-9/+6
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| * allwinner: Fix incorrect ARISC code patch offset checkSamuel Holland2019-12-043-9/+6
| | | | | | | | | | | | | | | | | | | | The current range check for the offset is wrong: it is counting bytes, while indexing an array of uint32_t. Since the offset is always zero, the parameter is unnecessary. Instead of adding more code to fix the check, remove the parameter to avoid the problem entirely. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
* | Merge "allwinner: power: Add DLDO4 power rail" into integrationSandrine Bailleux2019-12-131-0/+1
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| * | allwinner: power: Add DLDO4 power railStefan Mavrodiev2019-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | A64-OLinuXino family boards (maybe others too) uses PG for USB vbus enable/disable. However PG is supplied by DLDO4, which is not present in the list of known regulators. This patch adds DLD04 to it. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466
* | | Merge "intel: s10: Remove unused source code" into integrationSandrine Bailleux2019-12-132-586/+0
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| * | | intel: s10: Remove unused source codeHadi Asyrafi2019-12-122-586/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818
* | | | Tegra194: smmu: add support for backup multiple smmu regsPritesh Raithatha2019-12-102-138/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | | | Tegra194: introduce tegra_mc_def.hPritesh Raithatha2019-12-101-0/+650
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | | | Tegra194: 40-bit wide memory address spaceSteven Kao2019-12-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao <skao@nvidia.com>
* | | | Tegra194: psci: rename 'percpu_data' variableVarun Wadekar2019-12-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
* | | | Merge "Use the proper size for tb_fw_cfg_dtb" into integrationAlexei Fedorov2019-12-101-5/+3
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| * | | | Use the proper size for tb_fw_cfg_dtbLouis Mayencourt2019-12-091-5/+3
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page (but depend on the platform). Instead, read the actual size of the dtb with the libfdt "fdt_totalsize" function. This avoid flushing extra memory after updating the dtb with mbedtls heap information when shared heap is used. Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integrationSandrine Bailleux2019-12-101-1/+4
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| * | | arm: Fix current RECLAIM_INIT_CODE behaviorAmbroise Vincent2019-12-091-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com>
* | | Merge changes from topic "allwinner_bl31_size" into integrationSoby Mathew2019-12-064-5/+9
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: Reduce space lost to object alignment imx: Fix multiple definition of ipc_handle imx: Fix missing inclusion of cdefs.h
| * | | imx: Fix multiple definition of ipc_handleSamuel Holland2019-12-042-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
| * | | imx: Fix missing inclusion of cdefs.hSamuel Holland2019-12-042-2/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
* | | Merge "intel: Refactor common platform code [5/5]" into integrationMark Dykes2019-12-049-80/+51
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| * | | intel: Refactor common platform code [5/5]Hadi Asyrafi2019-11-289-80/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
* | | | Merge changes from topic "platform-refactor" into integrationMark Dykes2019-12-0434-1117/+210
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: intel: Refactor common platform code [4/5] intel: Refactor common platform code [3/5] intel: Refactor common platform code [2/5] intel: Refactor common platform code [1/5]
| * | | intel: Refactor common platform code [4/5]Hadi Asyrafi2019-11-284-20/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd
| * | | intel: Refactor common platform code [3/5]Hadi Asyrafi2019-11-2813-415/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
| * | | intel: Refactor common platform code [2/5]Hadi Asyrafi2019-11-2811-277/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
| * | | intel: Refactor common platform code [1/5]Hadi Asyrafi2019-11-2820-405/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
* | | | Merge "rockchip: px30: Add support for UART3 as serial output" into integrationManish Pandey2019-12-041-0/+3
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| * | | rockchip: px30: Add support for UART3 as serial outputPaul Kocialkowski2019-11-271-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | Add the UART3 base definition for serial output, which is used on some PX30 SoM boards. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015
* | | Merge "Enable -Wlogical-op always" into integrationManish Pandey2019-12-031-1/+1
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| * | | Enable -Wlogical-op alwaysJustin Chadwell2019-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Wlogical-op prevents common errors with using numerical constants where a boolean one is expected as well as when the operands of a logical operator are the same. While these are perfectly valid behavior, they can be a sign that something is slightly off. This patch adds this warning to gcc and it's closest equivalent to clang, while also fixing any warnings that enabling them causes. Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | | | Merge "Enable -Wshadow always" into integrationManish Pandey2019-12-034-26/+26
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| * | | Enable -Wshadow alwaysJustin Chadwell2019-11-194-26/+26
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* | | Merge "plat/rockchip: initialize reset and poweroff GPIOs with known invalid ↵Manish Pandey2019-12-031-2/+9
|\ \ \ | | | | | | | | | | | | value" into integration
| * | | plat/rockchip: initialize reset and poweroff GPIOs with known invalid valueVasily Khoruzhick2019-11-171-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And return NULL if we didn't get them in bl aux params otherwise reset and poweroff will be broken on platforms that do not have reset and poweroff GPIOs. Fixes: c1185ffde17c ("plat/rockchip: Switch to use new common BL aux parameter library") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Change-Id: Ic6cf6383d8f05d745e2c5d5e1b1df38514ea8429
* | | | Merge changes from topic "tegra-downstream-092319" into integrationSandrine Bailleux2019-12-0325-1654/+2296
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: Tegra194: add support to reset GPU Tegra194: memctrl: fix logic to check TZDRAM config register access Tegra: introduce plat_enable_console() Tegra: include: drivers: introduce spe.h Tegra194: update nvg header to v6.4 Tegra194: mce: enable strict checking Tegra194: CC6 state from last offline CPU in the cluster Tegra194: console driver compilation from platform makefiles Tegra194: memctrl: platform handler for TZDRAM setup Tegra194: memctrl: override SE client as coherent Tegra194: save system suspend entry marker to TZDRAM Tegra194: helper functions for CPU rst handler and SMMU ctx offset Tegra194: cleanup references to Tegra186 Tegra194: mce: display NVG header version during boot Tegra194: mce: fix cg_cstate encoding format Tegra194: drivers: SE and RNG1/PKA1 context save support Tegra194: rename secure scratch register macros Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation Tegra194: mce: remove unsupported functionality Tegra194: sanity check target cluster during core power on Tegra194: fix defects flagged by MISRA scan Tegra194: mce: fix defects flagged by MISRA scan Tegra194: remove the GPU reset register macro Tegra194: MC registers to allow CPU accesses to TZRAM Tegra194: increase MAX_MMAP_REGIONS macro value Tegra194: update nvg header to v6.1 Tegra194: update cache operations supported by the ROC Tegra194: memctrl: platform handlers to reprogram MSS Tegra194: core and cluster count values Tegra194: correct the TEGRA_CAR_RESET_BASE macro value Tegra194: add MC_SECURITY mask defines Tegra194: Update wake mask, wake time for cpu offlining Tegra194: program stream ids for XUSB Tegra194: Update checks for c-state stats Tegra194: smmu: fix mask for board revision id Tegra194: smmu: ISO support Tegra194: Initialize smmu on system suspend exit Tegra194: Update cpu core-id calculation Tegra194: read-modify-write ACTLR_ELx registers Tegra194: Enable fake system suspend Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits Tegra194: platform support for memctrl/smmu drivers Tegra194: Support for cpu suspend
| * | | | Tegra194: add support to reset GPUJeetesh Burman2019-11-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros, to define registers required to support GPU reset, for Tegra194 SoCs. Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526 Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
| * | | | Tegra194: memctrl: fix logic to check TZDRAM config register accessSteven Kao2019-11-282-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the logic to check if the previous bootloader has disabled access to the TZDRAM configuration registers. The polarity for the bit was incorrect in the previous check. Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03 Signed-off-by: Steven Kao <skao@nvidia.com>
| * | | | Tegra: introduce plat_enable_console()Varun Wadekar2019-11-288-56/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra: include: drivers: introduce spe.hVarun Wadekar2019-11-281-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a header file for the spe-console driver. This file currently provides a device struct and a registration function call for clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799
| * | | | Tegra194: update nvg header to v6.4Steven Kao2019-11-281-222/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the header, t194_nvg.h, to v6.4. This gets it in synch with MTS pre-release 2 - cl39748439. Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7 Signed-off-by: Steven Kao <skao@nvidia.com>
| * | | | Tegra194: mce: enable strict checkingDilan Lee2019-11-285-1/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee <dilee@nvidia.com>
| * | | | Tegra194: CC6 state from last offline CPU in the clusterVarun Wadekar2019-11-281-35/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the CC6 cluster state for the cluster, if the current CPU being offlined is the last CPU in the cluster. Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: console driver compilation from platform makefilesVarun Wadekar2019-11-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the console driver from individual platform makefile, to allow future platforms to include consoles of their choice. Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: memctrl: platform handler for TZDRAM setupSteven Kao2019-11-282-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the platform with flexibility to perform custom steps during TZDRAM setup. Tegra194 platforms checks if the config registers are locked and TZDRAM setup has already been done by the previous bootloaders, before setting up the fence. Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3 Signed-off-by: Steven Kao <skao@nvidia.com>
| * | | | Tegra194: memctrl: override SE client as coherentPuneet Saxena2019-11-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables IO coherency for SE clients, SEWR and SERD, by overriding their platform settings to "normal_coherent". This setting also converts read/write requests from these SE clients to Normal type. Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
| * | | | Tegra194: save system suspend entry marker to TZDRAMVarun Wadekar2019-11-283-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra194 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: helper functions for CPU rst handler and SMMU ctx offsetVarun Wadekar2019-11-284-19/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: cleanup references to Tegra186Varun Wadekar2019-11-288-128/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up all references to the Tegra186 family of SoCs. Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: mce: display NVG header version during bootVarun Wadekar2019-11-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MCE driver checks the NVG interface version during boot and disaplys the hardware and software versions on the console. The software version is being displayed as zero. This patch updates the prints to use the real NVG header version instead. Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | | Tegra194: mce: fix cg_cstate encoding formatVignesh Radhakrishnan2019-11-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: - cstate_info variable is used to pass on requested cstate to mce - Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info - cg_cstate values can range from 0 to 7, with 7 representing cg7 - Thus, cg_cstate is to be encoded using 3 bits (val: 0-7) - Fix this, as per ISS and ensure bits 8, 9, 10 are used Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 21:15:54 +0000