Tegra194: smmu: add support for backup multiple smmu regs

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

2 files changed, 3 insertions, 138 deletions

diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 1696d5910..640ef4deb 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -270,143 +270,8 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	mc_make_sid_override_cfg(MIU2W),
 	mc_make_sid_override_cfg(MIU3R),
 	mc_make_sid_override_cfg(MIU3W),
-	smmu_make_gnsr0_nsec_cfg(CR0),
-	smmu_make_gnsr0_sec_cfg(IDR0),
-	smmu_make_gnsr0_sec_cfg(IDR1),
-	smmu_make_gnsr0_sec_cfg(IDR2),
-	smmu_make_gnsr0_nsec_cfg(GFSR),
-	smmu_make_gnsr0_nsec_cfg(GFSYNR0),
-	smmu_make_gnsr0_nsec_cfg(GFSYNR1),
-	smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
-	smmu_make_gnsr0_nsec_cfg(PIDR2),
-	smmu_make_smrg_group(0),
-	smmu_make_smrg_group(1),
-	smmu_make_smrg_group(2),
-	smmu_make_smrg_group(3),
-	smmu_make_smrg_group(4),
-	smmu_make_smrg_group(5),
-	smmu_make_smrg_group(6),
-	smmu_make_smrg_group(7),
-	smmu_make_smrg_group(8),
-	smmu_make_smrg_group(9),
-	smmu_make_smrg_group(10),
-	smmu_make_smrg_group(11),
-	smmu_make_smrg_group(12),
-	smmu_make_smrg_group(13),
-	smmu_make_smrg_group(14),
-	smmu_make_smrg_group(15),
-	smmu_make_smrg_group(16),
-	smmu_make_smrg_group(17),
-	smmu_make_smrg_group(18),
-	smmu_make_smrg_group(19),
-	smmu_make_smrg_group(20),
-	smmu_make_smrg_group(21),
-	smmu_make_smrg_group(22),
-	smmu_make_smrg_group(23),
-	smmu_make_smrg_group(24),
-	smmu_make_smrg_group(25),
-	smmu_make_smrg_group(26),
-	smmu_make_smrg_group(27),
-	smmu_make_smrg_group(28),
-	smmu_make_smrg_group(29),
-	smmu_make_smrg_group(30),
-	smmu_make_smrg_group(31),
-	smmu_make_smrg_group(32),
-	smmu_make_smrg_group(33),
-	smmu_make_smrg_group(34),
-	smmu_make_smrg_group(35),
-	smmu_make_smrg_group(36),
-	smmu_make_smrg_group(37),
-	smmu_make_smrg_group(38),
-	smmu_make_smrg_group(39),
-	smmu_make_smrg_group(40),
-	smmu_make_smrg_group(41),
-	smmu_make_smrg_group(42),
-	smmu_make_smrg_group(43),
-	smmu_make_smrg_group(44),
-	smmu_make_smrg_group(45),
-	smmu_make_smrg_group(46),
-	smmu_make_smrg_group(47),
-	smmu_make_smrg_group(48),
-	smmu_make_smrg_group(49),
-	smmu_make_smrg_group(50),
-	smmu_make_smrg_group(51),
-	smmu_make_smrg_group(52),
-	smmu_make_smrg_group(53),
-	smmu_make_smrg_group(54),
-	smmu_make_smrg_group(55),
-	smmu_make_smrg_group(56),
-	smmu_make_smrg_group(57),
-	smmu_make_smrg_group(58),
-	smmu_make_smrg_group(59),
-	smmu_make_smrg_group(60),
-	smmu_make_smrg_group(61),
-	smmu_make_smrg_group(62),
-	smmu_make_smrg_group(63),
-	smmu_make_cb_group(0),
-	smmu_make_cb_group(1),
-	smmu_make_cb_group(2),
-	smmu_make_cb_group(3),
-	smmu_make_cb_group(4),
-	smmu_make_cb_group(5),
-	smmu_make_cb_group(6),
-	smmu_make_cb_group(7),
-	smmu_make_cb_group(8),
-	smmu_make_cb_group(9),
-	smmu_make_cb_group(10),
-	smmu_make_cb_group(11),
-	smmu_make_cb_group(12),
-	smmu_make_cb_group(13),
-	smmu_make_cb_group(14),
-	smmu_make_cb_group(15),
-	smmu_make_cb_group(16),
-	smmu_make_cb_group(17),
-	smmu_make_cb_group(18),
-	smmu_make_cb_group(19),
-	smmu_make_cb_group(20),
-	smmu_make_cb_group(21),
-	smmu_make_cb_group(22),
-	smmu_make_cb_group(23),
-	smmu_make_cb_group(24),
-	smmu_make_cb_group(25),
-	smmu_make_cb_group(26),
-	smmu_make_cb_group(27),
-	smmu_make_cb_group(28),
-	smmu_make_cb_group(29),
-	smmu_make_cb_group(30),
-	smmu_make_cb_group(31),
-	smmu_make_cb_group(32),
-	smmu_make_cb_group(33),
-	smmu_make_cb_group(34),
-	smmu_make_cb_group(35),
-	smmu_make_cb_group(36),
-	smmu_make_cb_group(37),
-	smmu_make_cb_group(38),
-	smmu_make_cb_group(39),
-	smmu_make_cb_group(40),
-	smmu_make_cb_group(41),
-	smmu_make_cb_group(42),
-	smmu_make_cb_group(43),
-	smmu_make_cb_group(44),
-	smmu_make_cb_group(45),
-	smmu_make_cb_group(46),
-	smmu_make_cb_group(47),
-	smmu_make_cb_group(48),
-	smmu_make_cb_group(49),
-	smmu_make_cb_group(50),
-	smmu_make_cb_group(51),
-	smmu_make_cb_group(52),
-	smmu_make_cb_group(53),
-	smmu_make_cb_group(54),
-	smmu_make_cb_group(55),
-	smmu_make_cb_group(56),
-	smmu_make_cb_group(57),
-	smmu_make_cb_group(58),
-	smmu_make_cb_group(59),
-	smmu_make_cb_group(60),
-	smmu_make_cb_group(61),
-	smmu_make_cb_group(62),
-	smmu_make_cb_group(63),
+	smmu_make_cfg(TEGRA_SMMU0_BASE),
+	smmu_make_cfg(TEGRA_SMMU2_BASE),
 	smmu_bypass_cfg,	/* TBU settings */
 	_END_OF_TABLE_,
 };
diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
index 33c7e6f78..696a5774e 100644
--- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
@@ -12,7 +12,7 @@
 
 #define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
 #define TEGRA194_STATE_SYSTEM_RESUME	0x600D
-#define TEGRA194_SMMU_CTX_SIZE		0x490
+#define TEGRA194_SMMU_CTX_SIZE		0x80B
 
 	.align 4
 	.globl	tegra194_cpu_reset_handler