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| author | Samuel Holland <samuel@sholland.org> | 2019-10-20 14:18:48 -0500 |
|---|---|---|
| committer | Samuel Holland <samuel@sholland.org> | 2019-12-04 01:54:48 -0600 |
| commit | 5cffedcec2c0dda50e4172e0cfd769b0e6ad665c (patch) | |
| tree | f290f7a7a60c1b30366c09006d7831b0a04fef41 /plat | |
| parent | 87b582ef5b31c5893a470b61c217931fc7602da3 (diff) | |
| download | platform_external_arm-trusted-firmware-5cffedcec2c0dda50e4172e0cfd769b0e6ad665c.tar.gz platform_external_arm-trusted-firmware-5cffedcec2c0dda50e4172e0cfd769b0e6ad665c.tar.bz2 platform_external_arm-trusted-firmware-5cffedcec2c0dda50e4172e0cfd769b0e6ad665c.zip | |
allwinner: Fix incorrect ARISC code patch offset check
The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/allwinner/common/include/sunxi_private.h | 5 | ||||
| -rw-r--r-- | plat/allwinner/common/sunxi_common.c | 8 | ||||
| -rw-r--r-- | plat/allwinner/common/sunxi_cpu_ops.c | 2 |
3 files changed, 6 insertions, 9 deletions
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h index 11668797b..1f410559f 100644 --- a/plat/allwinner/common/include/sunxi_private.h +++ b/plat/allwinner/common/include/sunxi_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,6 @@ void sunxi_security_setup(void); uint16_t sunxi_read_soc_id(void); void sunxi_set_gpio_out(char port, int pin, bool level_high); int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb); -void sunxi_execute_arisc_code(uint32_t *code, size_t size, - int patch_offset, uint16_t param); +void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param); #endif /* SUNXI_PRIVATE_H */ diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 3b44aab68..0797452a6 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -172,8 +172,7 @@ DEFINE_BAKERY_LOCK(arisc_lock); * in SRAM, put the address of that into the reset vector and release the * arisc reset line. The SCP will execute that code and pull the line up again. */ -void sunxi_execute_arisc_code(uint32_t *code, size_t size, - int patch_offset, uint16_t param) +void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) { uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; @@ -187,8 +186,7 @@ void sunxi_execute_arisc_code(uint32_t *code, size_t size, } while (1); /* Patch up the code to feed in an input parameter. */ - if (patch_offset >= 0 && patch_offset <= (size - 4)) - code[patch_offset] = (code[patch_offset] & ~0xffff) | param; + code[0] = (code[0] & ~0xffff) | param; clean_dcache_range((uintptr_t)code, size); /* diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c index b4c9fcc18..6e29b69bf 100644 --- a/plat/allwinner/common/sunxi_cpu_ops.c +++ b/plat/allwinner/common/sunxi_cpu_ops.c @@ -78,7 +78,7 @@ void sunxi_cpu_off(u_register_t mpidr) * patched into the first instruction. */ sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), - 0, BIT_32(core)); + BIT_32(core)); } void sunxi_cpu_on(u_register_t mpidr) |