Merge changes from topic "platform-refactor" into integration

* changes:
  intel: Refactor common platform code [4/5]
  intel: Refactor common platform code [3/5]
  intel: Refactor common platform code [2/5]
  intel: Refactor common platform code [1/5]

34 files changed, 210 insertions, 1117 deletions

diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index e9ab92850..ece7b9c70 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -15,19 +15,18 @@
 #include <drivers/ti/uart/uart_16550.h>
 #include <lib/xlat_tables/xlat_tables.h>
 #include <platform_def.h>
-#include <socfpga_private.h>
 
 #include "agilex_clock_manager.h"
-#include "agilex_handoff.h"
-#include "agilex_mailbox.h"
 #include "agilex_memory_controller.h"
 #include "agilex_pinmux.h"
-#include "agilex_private.h"
 #include "agilex_reset_manager.h"
 #include "agilex_system_manager.h"
 
 #include "ccu/ncore_ccu.h"
 #include "qspi/cadence_qspi.h"
+#include "socfpga_handoff.h"
+#include "socfpga_mailbox.h"
+#include "socfpga_private.h"
 #include "wdt/watchdog.h"
 
 
@@ -59,7 +58,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
 
 	generic_delay_timer_init();
 
-	if (agilex_get_handoff(&reverse_handoff_ptr))
+	if (socfpga_get_handoff(&reverse_handoff_ptr))
 		return;
 	config_pinmux(&reverse_handoff_ptr);
 	boot_source = reverse_handoff_ptr.boot_source;
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index c8765e857..e7852cfab 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -67,15 +67,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 }
 
 static const interrupt_prop_t s10_interrupt_props[] = {
-	PLAT_INTEL_AGX_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
-	PLAT_INTEL_AGX_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
+	PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
+	PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
 };
 
 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
 
 static const gicv2_driver_data_t plat_gicv2_gic_data = {
-	.gicd_base = PLAT_INTEL_AGX_GICD_BASE,
-	.gicc_base = PLAT_INTEL_AGX_GICC_BASE,
+	.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
+	.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
 	.interrupt_props = s10_interrupt_props,
 	.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
 	.target_masks = target_mask_array,
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index 0822290aa..8af6a60bc 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -7,7 +7,7 @@
 #ifndef CLOCKMANAGER_H
 #define CLOCKMANAGER_H
 
-#include "agilex_handoff.h"
+#include "socfpga_handoff.h"
 
 /* Clock Manager Registers */
 #define CLKMGR_OFFSET				0xffd10000
diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h
index e6a7b341d..fe01062c0 100644
--- a/plat/intel/soc/agilex/include/agilex_pinmux.h
+++ b/plat/intel/soc/agilex/include/agilex_pinmux.h
@@ -12,7 +12,7 @@
 #define AGX_PINMUX_PINMUX_EMAC0_USEFPGA	0xffd13300
 #define AGX_PINMUX_IO0_DELAY		0xffd13400
 
-#include "agilex_handoff.h"
+#include "socfpga_handoff.h"
 
 void config_pinmux(handoff *handoff);
 
diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h
deleted file mode 100644
index fc0e9fddf..000000000
--- a/plat/intel/soc/agilex/include/agilex_private.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_PRIVATE_H
-#define AGX_PRIVATE_H
-
-#define AGX_MMC_REG_BASE	0xff808000
-
-#define EMMC_DESC_SIZE		(1<<20)
-#define EMMC_INIT_PARAMS(base, clk)		\
-	{	.bus_width = MMC_BUS_WIDTH_4,	\
-		.clk_rate = (clk),		\
-		.desc_base = (base),		\
-		.desc_size = EMMC_DESC_SIZE,	\
-		.flags = 0,			\
-		.reg_base = AGX_MMC_REG_BASE	\
-	}
-
-typedef enum {
-	BOOT_SOURCE_FPGA = 0,
-	BOOT_SOURCE_SDMMC,
-	BOOT_SOURCE_NAND,
-	BOOT_SOURCE_RSVD,
-	BOOT_SOURCE_QSPI
-} boot_source_type;
-
-void enable_nonsecure_access(void);
-void socfpga_io_setup(int boot_source);
-
-#endif
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
new file mode 100644
index 000000000..a346cb5f8
--- /dev/null
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SOCFPGA_DEF_H
+#define PLAT_SOCFPGA_DEF_H
+
+#include <platform_def.h>
+
+/* Platform Setting */
+#define PLATFORM_MODEL				PLAT_SOCFPGA_AGILEX
+
+/* Register Mapping */
+#define SOCFPGA_MMC_REG_BASE			0xff808000
+
+#define SOCFPGA_RSTMGR_OFST			0xffd11000
+#define SOCFPGA_RSTMGR_MPUMODRST_OFST		0xffd11020
+
+#endif /* PLAT_SOCFPGA_DEF_H */
+
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index d1ea62915..dc56ac8ba 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -37,17 +37,17 @@ BL2_SOURCES     +=	\
 		drivers/intel/soc/stratix10/io/s10_memmap_qspi.c	\
 		lib/cpus/aarch64/cortex_a53.S				\
 		plat/intel/soc/agilex/bl2_plat_setup.c			\
-		plat/intel/soc/agilex/socfpga_storage.c			\
+		plat/intel/soc/common/socfpga_storage.c			\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/agilex/soc/agilex_reset_manager.c	\
-		plat/intel/soc/agilex/soc/agilex_handoff.c		\
 		plat/intel/soc/agilex/soc/agilex_clock_manager.c	\
 		plat/intel/soc/agilex/soc/agilex_pinmux.c		\
 		plat/intel/soc/agilex/soc/agilex_memory_controller.c	\
+		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
 		plat/intel/soc/common/socfpga_image_load.c		\
 		plat/intel/soc/agilex/soc/agilex_system_manager.c	\
-		plat/intel/soc/agilex/soc/agilex_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c		\
 		plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -57,16 +57,15 @@ BL31_SOURCES	+=	\
 		lib/cpus/aarch64/cortex_a53.S				\
 		lib/cpus/aarch64/aem_generic.S				\
 		plat/common/plat_psci_common.c				\
-		plat/intel/soc/agilex/socfpga_sip_svc.c			\
+		plat/intel/soc/common/socfpga_sip_svc.c			\
 		plat/intel/soc/agilex/bl31_plat_setup.c 		\
-		plat/intel/soc/agilex/socfpga_psci.c			\
+		plat/intel/soc/common/socfpga_psci.c			\
 		plat/intel/soc/common/socfpga_topology.c		\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
 		plat/intel/soc/agilex/soc/agilex_reset_manager.c	\
 		plat/intel/soc/agilex/soc/agilex_pinmux.c		\
 		plat/intel/soc/agilex/soc/agilex_clock_manager.c	\
-		plat/intel/soc/agilex/soc/agilex_handoff.c		\
-		plat/intel/soc/agilex/soc/agilex_mailbox.c
+		plat/intel/soc/common/soc/socfpga_mailbox.c
 
 PROGRAMMABLE_RESET_ADDRESS	:= 0
 BL2_AT_EL3			:= 1
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 06891ff93..96b669cfd 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -11,8 +11,8 @@
 #include <lib/mmio.h>
 
 #include "agilex_clock_manager.h"
-#include "agilex_handoff.h"
 #include "agilex_system_manager.h"
+#include "socfpga_handoff.h"
 
 
 uint32_t wait_pll_lock(void)
diff --git a/plat/intel/soc/common/aarch64/platform_common.c b/plat/intel/soc/common/aarch64/platform_common.c
index 6d3d817d6..b79a63c86 100644
--- a/plat/intel/soc/common/aarch64/platform_common.c
+++ b/plat/intel/soc/common/aarch64/platform_common.c
@@ -8,7 +8,8 @@
 #include <arch_helpers.h>
 #include <platform_def.h>
 #include <plat/common/platform.h>
-#include <socfpga_private.h>
+
+#include "socfpga_private.h"
 
 
 unsigned int plat_get_syscnt_freq2(void)
diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 277862a30..e57aafb6a 100644
--- a/plat/intel/soc/agilex/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -13,6 +13,8 @@
 #include <common/tbbr/tbbr_img_def.h>
 #include <plat/common/common_def.h>
 
+#define PLAT_SOCFPGA_STRATIX10			1
+#define PLAT_SOCFPGA_AGILEX			2
 
 #define PLAT_CPUID_RELEASE			0xffe1b000
 #define PLAT_SEC_ENTRY				0xffe1b008
@@ -27,7 +29,7 @@
 #define PLATFORM_LINKER_FORMAT			"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH			aarch64
 
-/* Agilex supports up to 124GB RAM */
+/* SoCFPGA supports up to 124GB RAM */
 #define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 39)
 #define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 39)
 
@@ -56,18 +58,18 @@
 
 /* Interrupt related constant */
 
-#define INTEL_AGX_IRQ_SEC_PHY_TIMER		29
+#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER		29
 
-#define INTEL_AGX_IRQ_SEC_SGI_0			8
-#define INTEL_AGX_IRQ_SEC_SGI_1			9
-#define INTEL_AGX_IRQ_SEC_SGI_2			10
-#define INTEL_AGX_IRQ_SEC_SGI_3			11
-#define INTEL_AGX_IRQ_SEC_SGI_4			12
-#define INTEL_AGX_IRQ_SEC_SGI_5			13
-#define INTEL_AGX_IRQ_SEC_SGI_6			14
-#define INTEL_AGX_IRQ_SEC_SGI_7			15
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_0			8
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_1			9
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_2			10
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_3			11
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_4			12
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_5			13
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_6			14
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_7			15
 
-#define TSP_IRQ_SEC_PHY_TIMER		INTEL_AGX_IRQ_SEC_PHY_TIMER
+#define TSP_IRQ_SEC_PHY_TIMER		INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
 #define TSP_SEC_MEM_BASE		BL32_BASE
 #define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE + 1)
 /*******************************************************************************
@@ -158,35 +160,35 @@
 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ	(400)
 
-#define PLAT_INTEL_AGX_GICD_BASE	PLAT_GICD_BASE
-#define PLAT_INTEL_AGX_GICC_BASE	PLAT_GICC_BASE
+#define PLAT_INTEL_SOCFPGA_GICD_BASE	PLAT_GICD_BASE
+#define PLAT_INTEL_SOCFPGA_GICC_BASE	PLAT_GICC_BASE
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
-			grp, GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE)
-
-#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp)
+#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \
+			GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE)
+
+#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
 
 #define MAX_IO_HANDLES			4
 #define MAX_IO_DEVICES			4
diff --git a/plat/intel/soc/agilex/include/agilex_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h
index 201640611..889d13767 100644
--- a/plat/intel/soc/agilex/include/agilex_handoff.h
+++ b/plat/intel/soc/common/include/socfpga_handoff.h
@@ -15,6 +15,8 @@
 #define HANDOFF_MAGIC_CLOCK		0x434c4b53	/* CLKS */
 #define HANDOFF_MAGIC_MISC		0x4d495343	/* MISC */
 
+#include <socfpga_plat_def.h>
+
 typedef struct handoff_t {
 	/* header */
 	uint32_t	header_magic;
@@ -47,6 +49,44 @@ typedef struct handoff_t {
 	uint32_t	pinmux_iodelay_array[96];	/* offset, value */
 
 	/* clock configuration */
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+	uint32_t	clock_magic;
+	uint32_t	clock_length;
+	uint32_t	_pad_0x588_0x590[2];
+	uint32_t	main_pll_mpuclk;
+	uint32_t	main_pll_nocclk;
+	uint32_t	main_pll_cntr2clk;
+	uint32_t	main_pll_cntr3clk;
+	uint32_t	main_pll_cntr4clk;
+	uint32_t	main_pll_cntr5clk;
+	uint32_t	main_pll_cntr6clk;
+	uint32_t	main_pll_cntr7clk;
+	uint32_t	main_pll_cntr8clk;
+	uint32_t	main_pll_cntr9clk;
+	uint32_t	main_pll_nocdiv;
+	uint32_t	main_pll_pllglob;
+	uint32_t	main_pll_fdbck;
+	uint32_t	main_pll_pllc0;
+	uint32_t	main_pll_pllc1;
+	uint32_t	_pad_0x5cc_0x5d0[1];
+	uint32_t	per_pll_cntr2clk;
+	uint32_t	per_pll_cntr3clk;
+	uint32_t	per_pll_cntr4clk;
+	uint32_t	per_pll_cntr5clk;
+	uint32_t	per_pll_cntr6clk;
+	uint32_t	per_pll_cntr7clk;
+	uint32_t	per_pll_cntr8clk;
+	uint32_t	per_pll_cntr9clk;
+	uint32_t	per_pll_emacctl;
+	uint32_t	per_pll_gpiodiv;
+	uint32_t	per_pll_pllglob;
+	uint32_t	per_pll_fdbck;
+	uint32_t	per_pll_pllc0;
+	uint32_t	per_pll_pllc1;
+	uint32_t	hps_osc_clk_h;
+	uint32_t	fpga_clk_hz;
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
 	uint32_t	clock_magic;
 	uint32_t	clock_length;
 	uint32_t	_pad_0x588_0x590[2];
@@ -80,7 +120,7 @@ typedef struct handoff_t {
 	uint32_t	hps_osc_clk_h;
 	uint32_t	fpga_clk_hz;
 	uint32_t	_pad_0x604_0x610[3];
-
+#endif
 	/* misc configuration */
 	uint32_t	misc_magic;
 	uint32_t	misc_length;
@@ -89,7 +129,7 @@ typedef struct handoff_t {
 } handoff;
 
 int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
-int agilex_get_handoff(handoff *hoff_ptr);
+int socfpga_get_handoff(handoff *hoff_ptr);
 
 #endif
 
diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index cd8be2894..db4c84104 100644
--- a/plat/intel/soc/agilex/include/agilex_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef AGX_MBOX_H
-#define AGX_MBOX_H
+#ifndef SOCFPGA_MBOX_H
+#define SOCFPGA_MBOX_H
 
 #include <lib/utils_def.h>
 
@@ -124,4 +124,4 @@ int mailbox_read_response(int job_id, uint32_t *response);
 int mailbox_get_qspi_clock(void);
 void mailbox_reset_cold(void);
 
-#endif
+#endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index 6ab14090f..375484443 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -4,12 +4,38 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef PLATFORM_PRIVATE_H
-#define PLATFORM_PRIVATE_H
+#ifndef SOCFPGA_PRIVATE_H
+#define SOCFPGA_PRIVATE_H
+
+#include "socfpga_plat_def.h"
+
+#define EMMC_DESC_SIZE		(1<<20)
+
+#define EMMC_INIT_PARAMS(base, clk)			\
+	{	.bus_width = MMC_BUS_WIDTH_4,		\
+		.clk_rate = (clk),			\
+		.desc_base = (base),			\
+		.desc_size = EMMC_DESC_SIZE,		\
+		.flags = 0,				\
+		.reg_base = SOCFPGA_MMC_REG_BASE	\
+	}
+
+typedef enum {
+	BOOT_SOURCE_FPGA = 0,
+	BOOT_SOURCE_SDMMC,
+	BOOT_SOURCE_NAND,
+	BOOT_SOURCE_RSVD,
+	BOOT_SOURCE_QSPI
+} boot_source_type;
 
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
+
+void enable_nonsecure_access(void);
+
+void socfpga_io_setup(int boot_source);
+
 void socfgpa_configure_mmu_el3(unsigned long total_base,
 			unsigned long total_size,
 			unsigned long ro_start,
@@ -36,4 +62,4 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void);
 unsigned long socfpga_get_ns_image_entrypoint(void);
 
 
-#endif /* PLATFORM_PRIVATE_H */
+#endif /* SOCFPGA_PRIVATE_H */
diff --git a/plat/intel/soc/agilex/soc/agilex_handoff.c b/plat/intel/soc/common/soc/socfpga_handoff.c
index a458686f1..4bb3a9619 100644
--- a/plat/intel/soc/agilex/soc/agilex_handoff.c
+++ b/plat/intel/soc/common/soc/socfpga_handoff.c
@@ -4,15 +4,14 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <platform_def.h>
 #include <string.h>
 
-#include "agilex_handoff.h"
+#include "socfpga_handoff.h"
 
 #define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) |	\
 				(((x) & 0x0000FF00) << 8) | ((x) << 24))
 
-int agilex_get_handoff(handoff *reverse_hoff_ptr)
+int socfpga_get_handoff(handoff *reverse_hoff_ptr)
 {
 	int i;
 	uint32_t *buffer;
diff --git a/plat/intel/soc/agilex/soc/agilex_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index ebfea6148..27838bfe7 100644
--- a/plat/intel/soc/agilex/soc/agilex_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -7,7 +7,7 @@
 #include <lib/mmio.h>
 #include <common/debug.h>
 
-#include "agilex_mailbox.h"
+#include "socfpga_mailbox.h"
 
 static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
 					int len)
diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 12060ef08..e29836173 100644
--- a/plat/intel/soc/agilex/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -11,13 +11,11 @@
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 
-#include "agilex_reset_manager.h"
-#include "agilex_mailbox.h"
+#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
 
-#define AGX_RSTMGR_OFST			0xffd11000
-#define AGX_RSTMGR_MPUMODRST_OFST	0x20
 
-uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
+uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
 uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
 
 /*******************************************************************************
@@ -50,8 +48,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr)
 	*cpuid_release = cpu_id;
 
 	/* release core reset */
-	mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
-		1 << cpu_id);
+	mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
 	return PSCI_E_SUCCESS;
 }
 
@@ -81,8 +78,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
 		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
 			__func__, i, target_state->pwr_domain_state[i]);
 	/* assert core reset */
-	mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
-		1 << cpu_id);
+	mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
 
 }
 
@@ -121,8 +117,7 @@ void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
 			__func__, i, target_state->pwr_domain_state[i]);
 
 	/* release core reset */
-	mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
-		1 << cpu_id);
+	mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
 }
 
 /*******************************************************************************
@@ -137,9 +132,6 @@ static void __dead2 socfpga_system_off(void)
 
 static void __dead2 socfpga_system_reset(void)
 {
-	INFO("assert Peripheral from Reset\r\n");
-
-	deassert_peripheral_reset();
 	mailbox_reset_cold();
 
 	while (1)
@@ -191,7 +183,7 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const struct plat_psci_ops **psci_ops)
 {
 	/* Save warm boot entrypoint.*/
-	*agilex_sec_entry = sec_entrypoint;
+	*socfpga_sec_entry = sec_entrypoint;
 
 	*psci_ops = &socfpga_psci_pm_ops;
 	return 0;
diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 6a1c957c3..88750d771 100644
--- a/plat/intel/soc/agilex/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -9,7 +9,7 @@
 #include <common/runtime_svc.h>
 #include <tools_share/uuid.h>
 
-#include "agilex_mailbox.h"
+#include "socfpga_mailbox.h"
 
 /* Number of SiP Calls implemented */
 #define SIP_NUM_CALLS		0x3
@@ -360,7 +360,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
 }
 
 DECLARE_RT_SVC(
-	agilex_sip_svc,
+	socfpga_sip_svc,
 	OEN_SIP_START,
 	OEN_SIP_END,
 	SMC_TYPE_FAST,
@@ -369,7 +369,7 @@ DECLARE_RT_SVC(
 );
 
 DECLARE_RT_SVC(
-	agilex_sip_svc_std,
+	socfpga_sip_svc_std,
 	OEN_SIP_START,
 	OEN_SIP_END,
 	SMC_TYPE_YIELD,
diff --git a/plat/intel/soc/agilex/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index 76dd81f75..a2f2c184c 100644
--- a/plat/intel/soc/agilex/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -19,7 +19,7 @@
 #include <lib/mmio.h>
 #include <tools_share/firmware_image_package.h>
 
-#include "agilex_private.h"
+#include "socfpga_private.h"
 
 #define PLAT_FIP_BASE		(0)
 #define PLAT_FIP_MAX_SIZE	(0x1000000)
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index f24bbdec4..7376b4143 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -19,7 +19,6 @@
 #include <common/image_decompress.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
-#include <socfpga_private.h>
 #include <drivers/synopsys/dw_mmc.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables.h>
@@ -27,11 +26,11 @@
 #include "s10_memory_controller.h"
 #include "s10_reset_manager.h"
 #include "s10_clock_manager.h"
-#include "s10_handoff.h"
 #include "s10_pinmux.h"
-#include "stratix10_private.h"
-#include "include/s10_mailbox.h"
 #include "qspi/cadence_qspi.h"
+#include "socfpga_handoff.h"
+#include "socfpga_mailbox.h"
+#include "socfpga_private.h"
 #include "wdt/watchdog.h"
 
 
@@ -63,7 +62,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
 
 	generic_delay_timer_init();
 
-	if (s10_get_handoff(&reverse_handoff_ptr))
+	if (socfpga_get_handoff(&reverse_handoff_ptr))
 		return;
 	config_pinmux(&reverse_handoff_ptr);
 	boot_source = reverse_handoff_ptr.boot_source;
@@ -115,7 +114,7 @@ void bl2_el3_plat_arch_setup(void)
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		dw_mmc_init(&params, &info);
-		stratix10_io_setup(boot_source);
+		socfpga_io_setup(boot_source);
 		break;
 
 	case BOOT_SOURCE_QSPI:
@@ -124,7 +123,7 @@ void bl2_el3_plat_arch_setup(void)
 		cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
 			QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
 			QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
-		stratix10_io_setup(boot_source);
+		socfpga_io_setup(boot_source);
 		break;
 
 	default:
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 7c9833b33..9887cb1d5 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -16,14 +16,12 @@
 #include <drivers/ti/uart/uart_16550.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/arm/gicv2.h>
-#include <s10_mailbox.h>
 #include <lib/xlat_tables/xlat_tables.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
 
-#include "stratix10_private.h"
-#include "s10_handoff.h"
+#include "socfpga_private.h"
 #include "s10_reset_manager.h"
 #include "s10_memory_controller.h"
 #include "s10_pinmux.h"
@@ -82,15 +80,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 }
 
 static const interrupt_prop_t s10_interrupt_props[] = {
-	PLAT_INTEL_S10_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
-	PLAT_INTEL_S10_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
+	PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
+	PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
 };
 
 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
 
 static const gicv2_driver_data_t plat_gicv2_gic_data = {
-	.gicd_base = PLAT_INTEL_S10_GICD_BASE,
-	.gicc_base = PLAT_INTEL_S10_GICC_BASE,
+	.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
+	.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
 	.interrupt_props = s10_interrupt_props,
 	.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
 	.target_masks = target_mask_array,
diff --git a/plat/intel/soc/stratix10/include/platform_def.h b/plat/intel/soc/stratix10/include/platform_def.h
deleted file mode 100644
index a753acd20..000000000
--- a/plat/intel/soc/stratix10/include/platform_def.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
-
-#include <arch.h>
-#include <common/bl_common.h>
-#include <common/interrupt_props.h>
-#include <common/tbbr/tbbr_img_def.h>
-#include <drivers/arm/gic_common.h>
-#include <plat/common/common_def.h>
-
-
-#define PLAT_CPUID_RELEASE			0xffe1b000
-#define PLAT_SEC_ENTRY				0xffe1b008
-
-/* Define next boot image name and offset */
-#define PLAT_NS_IMAGE_OFFSET			0x50000
-#define PLAT_HANDOFF_OFFSET			0xFFE3F000
-
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT			"elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH			aarch64
-
-/* Stratix 10 supports up to 124GB RAM */
-#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 39)
-#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 39)
-
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-#define PLAT_PRIMARY_CPU			0
-#define PLAT_SECONDARY_ENTRY_BASE		0x01f78bf0
-
-/* Size of cacheable stacks */
-#define PLATFORM_STACK_SIZE			0x2000
-
-/* PSCI related constant */
-#define PLAT_NUM_POWER_DOMAINS		5
-#define PLAT_MAX_PWR_LVL		1
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
-#define PLATFORM_SYSTEM_COUNT			1
-#define PLATFORM_CLUSTER_COUNT			1
-#define PLATFORM_CLUSTER0_CORE_COUNT		4
-#define PLATFORM_CLUSTER1_CORE_COUNT		0
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-					PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER		4
-
-/* Interrupt related constant */
-
-#define INTEL_S10_IRQ_SEC_PHY_TIMER		29
-
-#define INTEL_S10_IRQ_SEC_SGI_0		8
-#define INTEL_S10_IRQ_SEC_SGI_1		9
-#define INTEL_S10_IRQ_SEC_SGI_2		10
-#define INTEL_S10_IRQ_SEC_SGI_3		11
-#define INTEL_S10_IRQ_SEC_SGI_4		12
-#define INTEL_S10_IRQ_SEC_SGI_5		13
-#define INTEL_S10_IRQ_SEC_SGI_6		14
-#define INTEL_S10_IRQ_SEC_SGI_7		15
-
-#define TSP_IRQ_SEC_PHY_TIMER		INTEL_S10_IRQ_SEC_PHY_TIMER
-#define TSP_SEC_MEM_BASE		BL32_BASE
-#define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE + 1)
-/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define DRAM_BASE				(0x0)
-#define DRAM_SIZE				(0x80000000)
-
-#define OCRAM_BASE				(0xFFE00000)
-#define OCRAM_SIZE				(0x00040000)
-
-#define MEM64_BASE				(0x0100000000)
-#define MEM64_SIZE				(0x1F00000000)
-
-#define DEVICE1_BASE				(0x80000000)
-#define DEVICE1_SIZE				(0x60000000)
-
-#define DEVICE2_BASE				(0xF7000000)
-#define DEVICE2_SIZE				(0x08E00000)
-
-#define DEVICE3_BASE				(0xFFFC0000)
-#define DEVICE3_SIZE				(0x00008000)
-
-#define DEVICE4_BASE				(0x2000000000)
-#define DEVICE4_SIZE				(0x0100000000)
-
-/*******************************************************************************
- * BL31 specific defines.
- ******************************************************************************/
-/*
- * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
- * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
- * little space for growth.
- */
-
-
-#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
-
-#define BL1_RO_BASE	(0xffe00000)
-#define BL1_RO_LIMIT	(0xffe0f000)
-#define BL1_RW_BASE	(0xffe10000)
-#define BL1_RW_LIMIT	(0xffe1ffff)
-#define BL1_RW_SIZE	(0x14000)
-
-#define BL2_BASE	(0xffe00000)
-#define BL2_LIMIT	(0xffe1b000)
-
-#define BL31_BASE	(0xffe1c000)
-#define BL31_LIMIT	(0xffe3bfff)
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define MAX_XLAT_TABLES			8
-#define MAX_MMAP_REGIONS		16
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT			6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
-
-#define PLAT_GIC_BASE			(0xFFFC0000)
-#define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE			0
-
-/*******************************************************************************
- * UART related constants
- ******************************************************************************/
-#define PLAT_UART0_BASE		(0xFFC02000)
-#define PLAT_UART1_BASE		(0xFFC02100)
-
-#define CRASH_CONSOLE_BASE	PLAT_UART0_BASE
-
-#define PLAT_BAUDRATE			(115200)
-#define PLAT_UART_CLOCK		(100000000)
-
-/*******************************************************************************
- * System counter frequency related constants
- ******************************************************************************/
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ	(400)
-
-#define PLAT_INTEL_S10_GICD_BASE	PLAT_GICD_BASE
-#define PLAT_INTEL_S10_GICC_BASE	PLAT_GICC_BASE
-
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
-			grp, GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE)
-
-#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp)
-
-#define MAX_IO_HANDLES                   4
-#define MAX_IO_DEVICES                  4
-#define MAX_IO_BLOCK_DEVICES             2
-
-
-#endif /* __PLATFORM_DEF_H__ */
-
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h
index c800b9cf7..acc700a07 100644
--- a/plat/intel/soc/stratix10/include/s10_clock_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h
@@ -7,7 +7,7 @@
 #ifndef __CLOCKMANAGER_H__
 #define __CLOCKMANAGER_H__
 
-#include "s10_handoff.h"
+#include "socfpga_handoff.h"
 
 #define ALT_CLKMGR				0xffd10000
 
diff --git a/plat/intel/soc/stratix10/include/s10_handoff.h b/plat/intel/soc/stratix10/include/s10_handoff.h
deleted file mode 100644
index 1cc8d09d2..000000000
--- a/plat/intel/soc/stratix10/include/s10_handoff.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef	_HANDOFF_H_
-#define	_HANDOFF_H_
-
-#define HANDOFF_MAGIC_HEADER	0x424f4f54	/* BOOT */
-#define HANDOFF_MAGIC_PINMUX_SEL	0x504d5558	/* PMUX */
-#define HANDOFF_MAGIC_IOCTLR	0x494f4354	/* IOCT */
-#define HANDOFF_MAGIC_FPGA		0x46504741	/* FPGA */
-#define HANDOFF_MAGIC_IODELAY	0x444c4159	/* DLAY */
-#define HANDOFF_MAGIC_CLOCK		0x434c4b53	/* CLKS */
-#define HANDOFF_MAGIC_MISC		0x4d495343	/* MISC */
-
-typedef struct handoff_t {
-	/* header */
-	uint32_t	header_magic;
-	uint32_t	header_device;
-	uint32_t	_pad_0x08_0x10[2];
-
-	/* pinmux configuration - select */
-	uint32_t	pinmux_sel_magic;
-	uint32_t	pinmux_sel_length;
-	uint32_t	_pad_0x18_0x20[2];
-	uint32_t	pinmux_sel_array[96];	/* offset, value */
-
-	/* pinmux configuration - io control */
-	uint32_t	pinmux_io_magic;
-	uint32_t	pinmux_io_length;
-	uint32_t	_pad_0x1a8_0x1b0[2];
-	uint32_t	pinmux_io_array[96];	/* offset, value */
-
-	/* pinmux configuration - use fpga switch */
-	uint32_t	pinmux_fpga_magic;
-	uint32_t	pinmux_fpga_length;
-	uint32_t	_pad_0x338_0x340[2];
-	uint32_t	pinmux_fpga_array[42];	/* offset, value */
-	uint32_t	_pad_0x3e8_0x3f0[2];
-
-	/* pinmux configuration - io delay */
-	uint32_t	pinmux_delay_magic;
-	uint32_t	pinmux_delay_length;
-	uint32_t	_pad_0x3f8_0x400[2];
-	uint32_t	pinmux_iodelay_array[96];	/* offset, value */
-
-	/* clock configuration */
-	uint32_t	clock_magic;
-	uint32_t	clock_length;
-	uint32_t	_pad_0x588_0x590[2];
-	uint32_t	main_pll_mpuclk;
-	uint32_t	main_pll_nocclk;
-	uint32_t	main_pll_cntr2clk;
-	uint32_t	main_pll_cntr3clk;
-	uint32_t	main_pll_cntr4clk;
-	uint32_t	main_pll_cntr5clk;
-	uint32_t	main_pll_cntr6clk;
-	uint32_t	main_pll_cntr7clk;
-	uint32_t	main_pll_cntr8clk;
-	uint32_t	main_pll_cntr9clk;
-	uint32_t	main_pll_nocdiv;
-	uint32_t	main_pll_pllglob;
-	uint32_t	main_pll_fdbck;
-	uint32_t	main_pll_pllc0;
-	uint32_t	main_pll_pllc1;
-	uint32_t	_pad_0x5cc_0x5d0[1];
-	uint32_t	per_pll_cntr2clk;
-	uint32_t	per_pll_cntr3clk;
-	uint32_t	per_pll_cntr4clk;
-	uint32_t	per_pll_cntr5clk;
-	uint32_t	per_pll_cntr6clk;
-	uint32_t	per_pll_cntr7clk;
-	uint32_t	per_pll_cntr8clk;
-	uint32_t	per_pll_cntr9clk;
-	uint32_t	per_pll_emacctl;
-	uint32_t	per_pll_gpiodiv;
-	uint32_t	per_pll_pllglob;
-	uint32_t	per_pll_fdbck;
-	uint32_t	per_pll_pllc0;
-	uint32_t	per_pll_pllc1;
-	uint32_t	hps_osc_clk_h;
-	uint32_t	fpga_clk_hz;
-
-	/* misc configuration */
-	uint32_t	misc_magic;
-	uint32_t	misc_length;
-	uint32_t	_pad_0x618_0x620[2];
-	uint32_t	boot_source;
-} handoff;
-
-int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
-int s10_get_handoff(handoff *hoff_ptr);
-
-#endif
-
-
diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h
deleted file mode 100644
index 554c26566..000000000
--- a/plat/intel/soc/stratix10/include/s10_mailbox.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __S10_MBOX__
-#define __S10_MBOX__
-
-#define MBOX_OFFSET		0xffa30000
-
-#define MBOX_ATF_CLIENT_ID	0x1
-#define MBOX_JOB_ID		0x1
-
-/* Mailbox interrupt flags and masks */
-#define MBOX_INT_FLAG_COE	0x1
-#define MBOX_INT_FLAG_RIE	0x2
-#define MBOX_INT_FLAG_UAE	0x100
-#define MBOX_COE_BIT(INTERRUPT)	((INTERRUPT) & 0x3)
-#define MBOX_UAE_BIT(INTERRUPT)	(((INTERRUPT) & (1<<4)))
-
-/* Mailbox response and status */
-#define MBOX_RESP_BUFFER_SIZE	16
-#define MBOX_RESP_ERR(BUFFER)	((BUFFER) & 0x00000fff)
-#define MBOX_RESP_LEN(BUFFER)	(((BUFFER) & 0x007ff000) >> 12)
-#define MBOX_RESP_CLIENT_ID(BUFFER)	(((BUFFER) & 0xf0000000) >> 28)
-#define MBOX_RESP_JOB_ID(BUFFER)	(((BUFFER) & 0x0f000000) >> 24)
-#define MBOX_STATUS_UA_MASK	(1<<8)
-
-/* Mailbox command and response */
-#define MBOX_CMD_FREE_OFFSET	0x14
-#define MBOX_CMD_BUFFER_SIZE	32
-#define MBOX_CLIENT_ID_CMD(CLIENT_ID)	((CLIENT_ID) << 28)
-#define MBOX_JOB_ID_CMD(JOB_ID)	(JOB_ID<<24)
-#define MBOX_CMD_LEN_CMD(CMD_LEN)	((CMD_LEN) << 12)
-#define MBOX_INDIRECT			(1 << 11)
-#define MBOX_INSUFFICIENT_BUFFER	-2
-#define MBOX_CIN			0x00
-#define MBOX_ROUT			0x04
-#define MBOX_URG			0x08
-#define MBOX_INT			0x0C
-#define MBOX_COUT			0x20
-#define MBOX_RIN			0x24
-#define MBOX_STATUS			0x2C
-#define MBOX_CMD_BUFFER			0x40
-#define MBOX_RESP_BUFFER		0xC0
-
-#define MBOX_RESP_BUFFER_SIZE		16
-#define MBOX_RESP_OK			0
-#define MBOX_RESP_INVALID_CMD		1
-#define MBOX_RESP_UNKNOWN_BR		2
-#define MBOX_RESP_UNKNOWN		3
-#define MBOX_RESP_NOT_CONFIGURED	256
-
-/* Mailbox SDM doorbell */
-#define MBOX_DOORBELL_TO_SDM		0x400
-#define MBOX_DOORBELL_FROM_SDM		0x480
-
-/* Mailbox QSPI commands */
-#define MBOX_CMD_RESTART		2
-#define MBOX_CMD_QSPI_OPEN		50
-#define MBOX_CMD_QSPI_CLOSE		51
-#define MBOX_CMD_QSPI_DIRECT		59
-#define MBOX_CMD_GET_IDCODE		16
-#define MBOX_CMD_QSPI_SET_CS		52
-
-/* Mailbox REBOOT commands */
-#define MBOX_CMD_REBOOT_HPS		71
-
-/* Generic error handling */
-#define MBOX_TIMEOUT			-2047
-#define MBOX_NO_RESPONSE		-2
-#define MBOX_WRONG_ID			-3
-
-/* Mailbox status */
-#define RECONFIG_STATUS_STATE		0
-#define RECONFIG_STATUS_PIN_STATUS	2
-#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
-#define PIN_STATUS_NSTATUS		(1U << 31)
-#define SOFTFUNC_STATUS_SEU_ERROR	(1 << 3)
-#define SOFTFUNC_STATUS_INIT_DONE	(1 << 1)
-#define SOFTFUNC_STATUS_CONF_DONE	(1 << 0)
-#define MBOX_CFGSTAT_STATE_CONFIG	0x10000000
-
-/* SMC function IDs for SiP Service queries */
-#define SIP_SVC_CALL_COUNT	0x8200ff00
-#define SIP_SVC_UID		0x8200ff01
-#define SIP_SVC_VERSION		0x8200ff03
-
-/* SiP Service Calls version numbers */
-#define SIP_SVC_VERSION_MAJOR	0
-#define SIP_SVC_VERSION_MINOR	1
-
-/* Mailbox reconfiguration commands */
-#define MBOX_RECONFIG		6
-#define MBOX_RECONFIG_DATA	8
-#define MBOX_RECONFIG_STATUS	9
-
-/* Sip get memory */
-#define INTEL_SIP_SMC_FPGA_CONFIG_START			0xC2000001
-#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM		0xC2000005
-#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE		0xC2000004
-#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE			0x42000002
-#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE	0xC2000003
-#define INTEL_SIP_SMC_STATUS_OK				0
-#define INTEL_SIP_SMC_STATUS_ERROR			0x4
-#define INTEL_SIP_SMC_STATUS_BUSY			0x1
-#define INTEL_SIP_SMC_STATUS_REJECTED			0x2
-#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR			0x1000
-#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE			16777216
-
-void mailbox_set_int(int interrupt_input);
-int mailbox_init(void);
-void mailbox_set_qspi_close(void);
-void mailbox_set_qspi_open(void);
-void mailbox_set_qspi_direct(void);
-int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
-				int len, int urgent, uint32_t *response);
-void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
-				int len, int urgent);
-int mailbox_read_response(int job_id, uint32_t *response);
-int mailbox_get_qspi_clock(void);
-void mailbox_reset_cold(void);
-
-#endif
diff --git a/plat/intel/soc/stratix10/include/s10_pinmux.h b/plat/intel/soc/stratix10/include/s10_pinmux.h
index a1ba29ef9..82367d74f 100644
--- a/plat/intel/soc/stratix10/include/s10_pinmux.h
+++ b/plat/intel/soc/stratix10/include/s10_pinmux.h
@@ -12,7 +12,7 @@
 #define S10_PINMUX_PINMUX_EMAC0_USEFPGA	0xffd13300
 #define S10_PINMUX_IO0_DELAY		0xffd13400
 
-#include "s10_handoff.h"
+#include "socfpga_handoff.h"
 
 void config_pinmux(handoff *handoff);
 
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
new file mode 100644
index 000000000..ab723f79d
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SOCFPGA_DEF_H
+#define PLAT_SOCFPGA_DEF_H
+
+#include <platform_def.h>
+
+/* Platform Setting */
+#define PLATFORM_MODEL		PLAT_SOCFPGA_STRATIX10
+
+/* Register Mapping */
+#define SOCFPGA_MMC_REG_BASE                    0xff808000
+
+#define SOCFPGA_RSTMGR_OFST                     0xffd11000
+#define SOCFPGA_RSTMGR_MPUMODRST_OFST           0xffd11020
+
+#endif /* PLATSOCFPGA_DEF_H */
+
diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h
deleted file mode 100644
index 85aff3aa7..000000000
--- a/plat/intel/soc/stratix10/include/stratix10_private.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __S10_PRIVATE_H__
-#define __S10_PRIVATE_H__
-
-#define S10_MMC_REG_BASE	0xff808000
-
-#define EMMC_DESC_SIZE		(1<<20)
-#define EMMC_INIT_PARAMS(base, clk)			\
-	{	.bus_width = MMC_BUS_WIDTH_4,	\
-		.clk_rate = (clk),		\
-		.desc_base = (base),		\
-		.desc_size = EMMC_DESC_SIZE,	\
-		.flags = 0,			\
-		.reg_base = S10_MMC_REG_BASE,	\
-		\
-	}
-
-typedef enum {
-	BOOT_SOURCE_FPGA = 0,
-	BOOT_SOURCE_SDMMC,
-	BOOT_SOURCE_NAND,
-	BOOT_SOURCE_RSVD,
-	BOOT_SOURCE_QSPI,
-} boot_source_type;
-
-void enable_nonsecure_access(void);
-void stratix10_io_setup(int boot_source);
-
-#endif
diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c
index f4a970e75..73389c95d 100644
--- a/plat/intel/soc/stratix10/plat_psci.c
+++ b/plat/intel/soc/stratix10/plat_psci.c
@@ -16,7 +16,7 @@
 
 #include "platform_def.h"
 #include "s10_reset_manager.h"
-#include "s10_mailbox.h"
+#include "socfpga_mailbox.h"
 
 #define S10_RSTMGR_OFST			0xffd11000
 #define S10_RSTMGR_MPUMODRST_OFST	0x20
diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c
index 2c2332ba9..23a009d12 100644
--- a/plat/intel/soc/stratix10/plat_sip_svc.c
+++ b/plat/intel/soc/stratix10/plat_sip_svc.c
@@ -8,7 +8,7 @@
 #include <common/debug.h>
 #include <common/runtime_svc.h>
 #include <lib/mmio.h>
-#include <s10_mailbox.h>
+#include <socfpga_mailbox.h>
 #include <tools_share/uuid.h>
 
 /* Number of SiP Calls implemented */
diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c
deleted file mode 100644
index 0b8b9cd2a..000000000
--- a/plat/intel/soc/stratix10/plat_storage.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/debug.h>
-#include <drivers/mmc.h>
-#include <tools_share/firmware_image_package.h>
-#include <drivers/io/io_block.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_fip.h>
-#include <drivers/io/io_memmap.h>
-#include <drivers/io/io_storage.h>
-#include <lib/mmio.h>
-#include <drivers/partition/partition.h>
-#include <lib/semihosting.h>
-#include <string.h>
-#include <lib/utils.h>
-#include <common/tbbr/tbbr_img_def.h>
-#include "platform_def.h"
-#include "stratix10_private.h"
-
-#define STRATIX10_FIP_BASE		(0)
-#define STRATIX10_FIP_MAX_SIZE		(0x1000000)
-#define STRATIX10_MMC_DATA_BASE		(0xffe3c000)
-#define STRATIX10_MMC_DATA_SIZE		(0x2000)
-#define STRATIX10_QSPI_DATA_BASE	(0x3C00000)
-#define STRATIX10_QSPI_DATA_SIZE	(0x1000000)
-
-
-static const io_dev_connector_t *fip_dev_con;
-static const io_dev_connector_t *boot_dev_con;
-
-static uintptr_t fip_dev_handle;
-static uintptr_t boot_dev_handle;
-
-static const io_uuid_spec_t bl2_uuid_spec = {
-	.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
-};
-
-static const io_uuid_spec_t bl31_uuid_spec = {
-	.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
-};
-
-static const io_uuid_spec_t bl33_uuid_spec = {
-	.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
-};
-
-uintptr_t a2_lba_offset;
-const char a2[] = {0xa2, 0x0};
-
-static const io_block_spec_t gpt_block_spec = {
-	.offset = 0,
-	.length = MMC_BLOCK_SIZE
-};
-
-static int check_fip(const uintptr_t spec);
-static int check_dev(const uintptr_t spec);
-
-static io_block_dev_spec_t boot_dev_spec;
-static int (*register_io_dev)(const io_dev_connector_t **);
-
-static io_block_spec_t fip_spec = {
-	.offset		= STRATIX10_FIP_BASE,
-	.length		= STRATIX10_FIP_MAX_SIZE,
-};
-
-struct plat_io_policy {
-	uintptr_t       *dev_handle;
-	uintptr_t       image_spec;
-	int             (*check)(const uintptr_t spec);
-};
-
-static const struct plat_io_policy policies[] = {
-	[FIP_IMAGE_ID] = {
-		&boot_dev_handle,
-		(uintptr_t)&fip_spec,
-		check_dev
-	},
-	[BL2_IMAGE_ID] = {
-	  &fip_dev_handle,
-	  (uintptr_t)&bl2_uuid_spec,
-	  check_fip
-	},
-	[BL31_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t)&bl31_uuid_spec,
-		check_fip
-	},
-	[BL33_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t) &bl33_uuid_spec,
-		check_fip
-	},
-	[GPT_IMAGE_ID] = {
-		&boot_dev_handle,
-		(uintptr_t) &gpt_block_spec,
-		check_dev
-	},
-};
-
-static int check_dev(const uintptr_t spec)
-{
-	int result;
-	uintptr_t local_handle;
-
-	result = io_dev_init(boot_dev_handle, (uintptr_t)NULL);
-	if (result == 0) {
-		result = io_open(boot_dev_handle, spec, &local_handle);
-		if (result == 0)
-			io_close(local_handle);
-	}
-	return result;
-}
-
-static int check_fip(const uintptr_t spec)
-{
-	int result;
-	uintptr_t local_image_handle;
-
-	result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
-	if (result == 0) {
-		result = io_open(fip_dev_handle, spec, &local_image_handle);
-		if (result == 0)
-			io_close(local_image_handle);
-	}
-	return result;
-}
-
-void stratix10_io_setup(int boot_source)
-{
-	int result;
-
-	switch (boot_source) {
-	case BOOT_SOURCE_SDMMC:
-		register_io_dev = &register_io_dev_block;
-		boot_dev_spec.buffer.offset	= STRATIX10_MMC_DATA_BASE;
-		boot_dev_spec.buffer.length	= MMC_BLOCK_SIZE;
-		boot_dev_spec.ops.read		= mmc_read_blocks;
-		boot_dev_spec.ops.write		= mmc_write_blocks;
-		boot_dev_spec.block_size	= MMC_BLOCK_SIZE;
-		break;
-
-	case BOOT_SOURCE_QSPI:
-		register_io_dev = &register_io_dev_memmap;
-		fip_spec.offset = fip_spec.offset + STRATIX10_QSPI_DATA_BASE;
-		break;
-
-	default:
-		ERROR("Unsupported boot source\n");
-		panic();
-		break;
-	}
-
-	result = (*register_io_dev)(&boot_dev_con);
-	assert(result == 0);
-
-	result = register_io_dev_fip(&fip_dev_con);
-	assert(result == 0);
-
-	result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec,
-			&boot_dev_handle);
-	assert(result == 0);
-
-	result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
-	assert(result == 0);
-
-	if (boot_source == BOOT_SOURCE_SDMMC) {
-		partition_init(GPT_IMAGE_ID);
-		fip_spec.offset = get_partition_entry(a2)->start;
-	}
-
-	(void)result;
-}
-
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
-			uintptr_t *image_spec)
-{
-	int result;
-	const struct plat_io_policy *policy;
-
-	assert(image_id < ARRAY_SIZE(policies));
-
-	policy = &policies[image_id];
-	result = policy->check(policy->image_spec);
-	assert(result == 0);
-
-	*image_spec = policy->image_spec;
-	*dev_handle = *(policy->dev_handle);
-
-	return result;
-}
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 34674b0cd..5bf8f6555 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -34,10 +34,10 @@ BL2_SOURCES     +=	\
 		drivers/gpio/gpio.c					\
 		drivers/intel/soc/stratix10/io/s10_memmap_qspi.c	\
 		plat/intel/soc/stratix10/bl2_plat_setup.c		\
-		plat/intel/soc/stratix10/plat_storage.c			\
+		plat/intel/soc/common/socfpga_storage.c			\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/stratix10/soc/s10_reset_manager.c	\
-		plat/intel/soc/stratix10/soc/s10_handoff.c		\
+		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
 		plat/intel/soc/stratix10/soc/s10_pinmux.c		\
 		plat/intel/soc/stratix10/soc/s10_memory_controller.c	\
@@ -46,7 +46,7 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/common/socfpga_image_load.c		\
 		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
 		common/desc_image_load.c				\
-		plat/intel/soc/stratix10/soc/s10_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 
@@ -55,16 +55,15 @@ BL31_SOURCES	+=	drivers/arm/cci/cci.c				\
 			lib/cpus/aarch64/aem_generic.S			\
 			lib/cpus/aarch64/cortex_a53.S			\
 			plat/common/plat_psci_common.c			\
-			plat/intel/soc/stratix10/plat_sip_svc.c		\
+			plat/intel/soc/common/socfpga_sip_svc.c		\
 			plat/intel/soc/stratix10/bl31_plat_setup.c 	\
-			plat/intel/soc/stratix10/plat_psci.c		\
+			plat/intel/soc/common/socfpga_psci.c		\
 			plat/intel/soc/common/socfpga_topology.c	\
 			plat/intel/soc/common/socfpga_delay_timer.c	\
 			plat/intel/soc/stratix10/soc/s10_reset_manager.c\
 			plat/intel/soc/stratix10/soc/s10_pinmux.c	\
 			plat/intel/soc/stratix10/soc/s10_clock_manager.c\
-			plat/intel/soc/stratix10/soc/s10_handoff.c	\
-			plat/intel/soc/stratix10/soc/s10_mailbox.c
+			plat/intel/soc/common/soc/socfpga_mailbox.c
 
 PROGRAMMABLE_RESET_ADDRESS	:= 0
 BL2_AT_EL3			:= 1
diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
index ed65c2ba8..e4ff7acf2 100644
--- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
@@ -12,8 +12,8 @@
 #include <platform_def.h>
 
 #include "s10_clock_manager.h"
-#include "s10_handoff.h"
 #include "s10_system_manager.h"
+#include "socfpga_handoff.h"
 
 
 void wait_pll_lock(void)
diff --git a/plat/intel/soc/stratix10/soc/s10_handoff.c b/plat/intel/soc/stratix10/soc/s10_handoff.c
deleted file mode 100644
index 1a4d5c326..000000000
--- a/plat/intel/soc/stratix10/soc/s10_handoff.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <drivers/arm/gicv2.h>
-#include <assert.h>
-#include <common/bl_common.h>
-#include <lib/mmio.h>
-#include <string.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-#include "s10_handoff.h"
-
-#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) |	\
-				(((x) & 0x0000FF00) << 8) | ((x) << 24))
-
-int s10_get_handoff(handoff *reverse_hoff_ptr)
-{
-	int i;
-	uint32_t *buffer;
-	handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET;
-
-	memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff));
-	buffer = (uint32_t *)reverse_hoff_ptr;
-
-	/* convert big indian to little indian */
-	for (i = 0; i < sizeof(handoff) / 4; i++)
-		buffer[i] = SWAP_UINT32(buffer[i]);
-
-	if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
-		return -1;
-	if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
-		return -1;
-	if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
-		return -1;
-	if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
-		return -1;
-	if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
-		return -1;
-
-	return 0;
-}
diff --git a/plat/intel/soc/stratix10/soc/s10_mailbox.c b/plat/intel/soc/stratix10/soc/s10_mailbox.c
deleted file mode 100644
index 00a07f33a..000000000
--- a/plat/intel/soc/stratix10/soc/s10_mailbox.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <common/debug.h>
-#include "s10_mailbox.h"
-
-static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
-					int len)
-{
-	uint32_t cmd_free_offset;
-	int i;
-
-	cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
-
-	if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
-		INFO("Insufficient buffer in mailbox\n");
-		return MBOX_INSUFFICIENT_BUFFER;
-	}
-
-
-	mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4),
-			header_cmd);
-
-
-	for (i = 0; i < len; i++) {
-		cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
-		mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER +
-				(cmd_free_offset++ * 4), args[i]);
-	}
-
-	cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
-	mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset);
-
-	return 0;
-}
-
-int mailbox_read_response(int job_id, uint32_t *response)
-{
-	int rin = 0;
-	int rout = 0;
-	int response_length = 0;
-	int resp = 0;
-	int total_resp_len = 0;
-	int timeout = 100000;
-
-	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
-
-	while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) {
-		if (timeout-- < 0)
-			return MBOX_NO_RESPONSE;
-	}
-
-	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
-
-	rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
-	rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
-
-	while (rout != rin) {
-		resp = mmio_read_32(MBOX_OFFSET +
-				    MBOX_RESP_BUFFER + ((rout++)*4));
-
-		rout %= MBOX_RESP_BUFFER_SIZE;
-		mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
-
-		if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID ||
-		   MBOX_RESP_JOB_ID(resp) != job_id) {
-			return MBOX_WRONG_ID;
-		}
-
-		if (MBOX_RESP_ERR(resp) > 0) {
-			INFO("Error in response: %x\n", resp);
-			return -resp;
-		}
-		response_length = MBOX_RESP_LEN(resp);
-
-		while (response_length) {
-
-			response_length--;
-			resp = mmio_read_32(MBOX_OFFSET +
-						MBOX_RESP_BUFFER +
-						(rout)*4);
-			if (response) {
-				*(response + total_resp_len) = resp;
-				total_resp_len++;
-			}
-			rout++;
-			rout %= MBOX_RESP_BUFFER_SIZE;
-			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
-		}
-		return total_resp_len;
-	}
-
-	return MBOX_NO_RESPONSE;
-}
-
-
-int mailbox_poll_response(int job_id, int urgent, uint32_t *response)
-{
-	int timeout = 80000;
-	int rin = 0;
-	int rout = 0;
-	int response_length = 0;
-	int resp = 0;
-	int total_resp_len = 0;
-
-	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
-
-	while (1) {
-		while (timeout > 0 &&
-			mmio_read_32(MBOX_OFFSET +
-				MBOX_DOORBELL_FROM_SDM) != 1) {
-			timeout--;
-		}
-
-		if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) {
-			INFO("Timed out waiting for SDM");
-			return MBOX_TIMEOUT;
-		}
-
-		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
-
-		if (urgent & 1) {
-			if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
-				MBOX_STATUS_UA_MASK) ^
-				(urgent & MBOX_STATUS_UA_MASK)) {
-				mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
-				return 0;
-			}
-
-			mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
-			INFO("Error: Mailbox did not get UA");
-			return -1;
-		}
-
-		rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
-		rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
-
-		while (rout != rin) {
-			resp = mmio_read_32(MBOX_OFFSET +
-					    MBOX_RESP_BUFFER + ((rout++)*4));
-
-			rout %= MBOX_RESP_BUFFER_SIZE;
-			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
-
-			if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID ||
-			   MBOX_RESP_JOB_ID(resp) != job_id)
-				continue;
-
-			if (MBOX_RESP_ERR(resp) > 0) {
-				INFO("Error in response: %x\n", resp);
-				return -MBOX_RESP_ERR(resp);
-			}
-			response_length = MBOX_RESP_LEN(resp);
-
-			while (response_length) {
-
-				response_length--;
-				resp = mmio_read_32(MBOX_OFFSET +
-							MBOX_RESP_BUFFER +
-							(rout)*4);
-				if (response) {
-					*(response + total_resp_len) = resp;
-					total_resp_len++;
-				}
-				rout++;
-				rout %= MBOX_RESP_BUFFER_SIZE;
-				mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
-			}
-			return total_resp_len;
-		}
-	}
-}
-
-void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
-			  int len, int urgent)
-{
-	if (urgent)
-		mmio_write_32(MBOX_OFFSET + MBOX_URG, 1);
-
-	fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
-					MBOX_JOB_ID_CMD(job_id) |
-					MBOX_CMD_LEN_CMD(len) |
-					MBOX_INDIRECT |
-					cmd, args, len);
-}
-
-int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
-			  int len, int urgent, uint32_t *response)
-{
-	int status;
-
-	if (urgent) {
-		urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
-					MBOX_STATUS_UA_MASK;
-		mmio_write_32(MBOX_OFFSET + MBOX_URG, 1);
-	}
-
-	status = fill_mailbox_circular_buffer(
-			MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
-			MBOX_JOB_ID_CMD(job_id) |
-			cmd, args, len);
-
-	if (status)
-		return status;
-
-	return mailbox_poll_response(job_id, urgent, response);
-}
-
-void mailbox_set_int(int interrupt)
-{
-
-	mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) |
-			MBOX_UAE_BIT(interrupt));
-}
-
-
-void mailbox_set_qspi_open(void)
-{
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0);
-}
-
-void mailbox_set_qspi_direct(void)
-{
-	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0);
-}
-
-void mailbox_set_qspi_close(void)
-{
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0);
-}
-
-int mailbox_get_qspi_clock(void)
-{
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0);
-}
-
-void mailbox_qspi_set_cs(int device_select)
-{
-	uint32_t cs_setting = device_select;
-
-	/* QSPI device select settings at 31:28 */
-	cs_setting = (cs_setting << 28);
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting,
-		1, 0, 0);
-}
-
-void mailbox_reset_cold(void)
-{
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0);
-}
-
-int mailbox_init(void)
-{
-	int status = 0;
-
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-	status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0);
-
-	if (status)
-		return status;
-
-	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
-
-	return 0;
-}
-