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| * | | | Tegra194: drivers: SE and RNG1/PKA1 context save supportSteven Kao2019-11-286-30/+338
| * | | | Tegra194: rename secure scratch register macrosSteven Kao2019-11-286-17/+22
| * | | | Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violationAnthony Zhou2019-11-282-1/+4
| * | | | Tegra194: mce: remove unsupported functionalityVarun Wadekar2019-11-284-329/+10
| * | | | Tegra194: sanity check target cluster during core power onVarun Wadekar2019-11-281-1/+1
| * | | | Tegra194: fix defects flagged by MISRA scanAnthony Zhou2019-11-287-242/+277
| * | | | Tegra194: mce: fix defects flagged by MISRA scanAnthony Zhou2019-11-283-66/+66
| * | | | Tegra194: remove the GPU reset register macroSteven Kao2019-11-281-2/+0
| * | | | Tegra194: MC registers to allow CPU accesses to TZRAMVarun Wadekar2019-11-281-1/+5
| * | | | Tegra194: increase MAX_MMAP_REGIONS macro valueSteven Kao2019-11-281-1/+1
| * | | | Tegra194: update nvg header to v6.1Steven Kao2019-11-283-147/+215
| * | | | Tegra194: update cache operations supported by the ROCSteven Kao2019-11-283-19/+62
| * | | | Tegra194: memctrl: platform handlers to reprogram MSSVarun Wadekar2019-11-284-179/+328
| * | | | Tegra194: core and cluster count valuesVarun Wadekar2019-11-282-2/+6
| * | | | Tegra194: correct the TEGRA_CAR_RESET_BASE macro valueSteven Kao2019-11-281-1/+1
| * | | | Tegra194: add MC_SECURITY mask definesHarvey Hsieh2019-11-281-0/+4
| * | | | Tegra194: Update wake mask, wake time for cpu offliningKrishna Sitaraman2019-11-281-2/+15
| * | | | Tegra194: program stream ids for XUSBAjay Gupta2019-11-284-6/+77
| * | | | Tegra194: Update checks for c-state statsKrishna Sitaraman2019-11-282-3/+14
| * | | | Tegra194: smmu: fix mask for board revision idPritesh Raithatha2019-11-281-1/+1
| * | | | Tegra194: smmu: ISO supportSteven Kao2019-11-283-6/+31
| * | | | Tegra194: Initialize smmu on system suspend exitVignesh Radhakrishnan2019-11-281-0/+2
| * | | | Tegra194: Update cpu core-id calculationKrishna Sitaraman2019-11-281-1/+1
| * | | | Tegra194: read-modify-write ACTLR_ELx registersSteven Kao2019-11-282-15/+4
| * | | | Tegra194: Enable fake system suspendVignesh Radhakrishnan2019-11-282-10/+68
| * | | | Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bitsVarun Wadekar2019-11-281-2/+2
| * | | | Tegra194: platform support for memctrl/smmu driversVarun Wadekar2019-11-284-321/+177
| * | | | Tegra194: Support for cpu suspendKrishna Sitaraman2019-11-281-3/+10
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* / | | plat/st: Fix incorrect return valueLionel Debieve2019-11-271-1/+1
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* | | Merge changes I5693ad56,I9ddc077a into integrationSoby Mathew2019-11-253-41/+123
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| * | | mediatek: mt8183: Fix AARCH64 init fail on CPU0James Liao2019-11-251-8/+18
| * | | mediatek: mt8183: refine GIC driver for low power scenarioskenny liang2019-11-253-34/+106
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* | | Merge "mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM" into...joanna.farley2019-11-222-0/+31
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| * | | mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPMRoger Lu2019-11-052-0/+31
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* | | Merge "Fix multithreaded FVP power domain tree" into integrationAlexei Fedorov2019-11-201-2/+3
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| * | | Fix multithreaded FVP power domain treeImre Kis2019-11-151-2/+3
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* | / GIC-600: Fix include ordering according to the coding styleMax Shvetsov2019-11-191-1/+1
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* | Merge changes from topic "tegra-downstream-092319" into integrationSandrine Bailleux2019-11-195-42/+40
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| * | Tegra194: remove L2 ECC parity protection settingHarvey Hsieh2019-11-131-37/+0
| * | Tegra194: sip_calls: mark unused parameter as constVarun Wadekar2019-11-131-1/+1
| * | Tegra194: implement handler to retrieve power domain treeVarun Wadekar2019-11-131-0/+8
| * | Tegra194: mce: fix function declaration conflictsAnthony Zhou2019-11-131-3/+3
| * | Tegra194: add macros to read GPU reset statusVarun Wadekar2019-11-131-0/+2
| * | Tegra194: skip notifying MCE in fake system suspendVignesh Radhakrishnan2019-11-131-17/+23
| * | Tegra194: Enable system suspendTejal Kudav2019-11-131-1/+20
* | | Merge changes from topic "lm/improve_memory_layout" into integrationSandrine Bailleux2019-11-182-6/+10
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| * | ROMLIB: Optimize memory layout when ROMLIB is usedLouis Mayencourt2019-11-182-6/+10
* | | Merge changes from topic "tegra-downstream-092319" into integrationSandrine Bailleux2019-11-1317-58/+3135
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| * | | Tegra194: add macros for security carveout configuration registersVarun Wadekar2019-10-241-24/+22
| * | | Tegra194: add 'TEGRA_TMRUS_SIZE' macroSteven Kao2019-10-241-0/+1
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