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| author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2017-07-14 13:51:44 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-11-28 11:14:21 -0800 |
| commit | cda7d91f67bced518d12dd6ccf52b5619beb307b (patch) | |
| tree | dbf3d82a145528e07734266e06618e820816da9b /plat | |
| parent | bc0190416e2f3d3c8d637f5017a31459806d7de9 (diff) | |
| download | platform_external_arm-trusted-firmware-cda7d91f67bced518d12dd6ccf52b5619beb307b.tar.gz platform_external_arm-trusted-firmware-cda7d91f67bced518d12dd6ccf52b5619beb307b.tar.bz2 platform_external_arm-trusted-firmware-cda7d91f67bced518d12dd6ccf52b5619beb307b.zip | |
Tegra194: Update wake mask, wake time for cpu offlining
This patch updates the wake mask and wake time to indicate to the
mce/mts that the cpu is powering down. Wake time is set to highest
possible value and wake mask is set to zero.
Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 14af725ea..d77842984 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -216,11 +216,20 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, /* Enable cluster powerdn from last CPU in the cluster */ if (cluster_powerdn) { - /* Enable CC7 state and turn off wake mask */ + /* Enable CC6 */ + /* todo */ - } else { + /* If cluster group needs to be railgated, request CG7 */ + /* todo */ + + /* Turn off wake mask */ + cstate_info.update_wake_mask = 1U; + mce_update_cstate_info(&cstate_info); + } else { /* Turn off wake_mask */ + cstate_info.update_wake_mask = 1U; + mce_update_cstate_info(&cstate_info); } } @@ -347,12 +356,16 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + int32_t ret = 0; /* Disable Denver's DCO operations */ if (impl == DENVER_IMPL) denver_disable_dco(); /* Turn off CPU */ + ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + assert(ret == 0); return PSCI_E_SUCCESS; } |