aboutsummaryrefslogtreecommitdiffstats
path: root/plat
diff options
context:
space:
mode:
authorAnthony Zhou <anzhou@nvidia.com>2017-10-25 18:17:08 +0800
committerVarun Wadekar <vwadekar@nvidia.com>2019-11-28 11:14:21 -0800
commit159baa4802e7ff1039e4f9451f854bda5ddeea41 (patch)
tree8f0dafd9c3d5c17fe1043f7573da8bde76345e3f /plat
parent08c085dc2ee6a8e48fb3ed06271dd374331826b1 (diff)
downloadplatform_external_arm-trusted-firmware-159baa4802e7ff1039e4f9451f854bda5ddeea41.tar.gz
platform_external_arm-trusted-firmware-159baa4802e7ff1039e4f9451f854bda5ddeea41.tar.bz2
platform_external_arm-trusted-firmware-159baa4802e7ff1039e4f9451f854bda5ddeea41.zip
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Rule 8.4, A compatible declaration shall be visible when an object or function with external linkage is defined. Add function delaration to the header file. Add suffix U to the unsigned constant define. Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h3
-rw-r--r--plat/nvidia/tegra/soc/t194/plat_sip_calls.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 32e7a532a..966c90bb3 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -50,6 +50,9 @@ uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
+int32_t nvg_roc_clean_cache(void);
+int32_t nvg_roc_flush_cache(void);
+int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
void nvg_set_request_data(uint64_t req, uint64_t data);
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 04602f046..03dad8540 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -23,7 +23,7 @@ extern bool tegra_fake_system_suspend;
/*******************************************************************************
* Tegra186 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03
+#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls