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| author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2017-05-24 17:21:22 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-11-28 11:14:21 -0800 |
| commit | 68d13a2eb84393b2e8bbf94b16783954d2544638 (patch) | |
| tree | 3346929185ac035467893ef612985ec5d51314ad /plat | |
| parent | 6907891de5f3d439621738b4247a0c616333cb9f (diff) | |
| download | platform_external_arm-trusted-firmware-68d13a2eb84393b2e8bbf94b16783954d2544638.tar.gz platform_external_arm-trusted-firmware-68d13a2eb84393b2e8bbf94b16783954d2544638.tar.bz2 platform_external_arm-trusted-firmware-68d13a2eb84393b2e8bbf94b16783954d2544638.zip | |
Tegra194: Update checks for c-state stats
This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.
Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h | 5 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 12 |
2 files changed, 14 insertions, 3 deletions
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index cc32ec416..3ac5333a0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -46,6 +46,11 @@ #define CACHE_CLEAN_INVAL_SET (1UL << 1) #define CACHE_CLEAN_INVAL_TR_SET (1UL << 2) +/******************************************************************************* + * C-state statistics macros + ******************************************************************************/ +#define MCE_STAT_ID_SHIFT 16UL + /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); int32_t nvg_enable_power_perf_mode(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index c797a0cf7..c7f659186 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -187,9 +187,15 @@ int32_t nvg_set_cstate_stat_query_value(uint64_t data) { int32_t ret = 0; - /* sanity check stat id */ - if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { - ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data); + /* sanity check stat id and core id*/ + if ((data >> MCE_STAT_ID_SHIFT) > + (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { + ERROR("%s: unknown stat id (%d)\n", __func__, + (uint32_t)(data >> MCE_STAT_ID_SHIFT)); + ret = EINVAL; + } else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) { + ERROR("%s: unknown core id (%d)\n", __func__, + (uint32_t)(data & MCE_CORE_ID_MASK)); ret = EINVAL; } else { nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); |