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| author | joanna.farley <joanna.farley@arm.com> | 2019-11-22 12:25:55 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-11-22 12:25:55 +0000 |
| commit | 82262970a0ffa765039260775b07b20b2ba5759c (patch) | |
| tree | 68779e8dbe21af9d85087329d69335aee2db16e1 /plat | |
| parent | 0ff3fb32f4d055b9de1463e5cb1823095e9286e8 (diff) | |
| parent | 658cb0725f6afa5838736137fec0d6171fbc23b8 (diff) | |
| download | platform_external_arm-trusted-firmware-82262970a0ffa765039260775b07b20b2ba5759c.tar.gz platform_external_arm-trusted-firmware-82262970a0ffa765039260775b07b20b2ba5759c.tar.bz2 platform_external_arm-trusted-firmware-82262970a0ffa765039260775b07b20b2ba5759c.zip | |
Merge "mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM" into integration
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/mediatek/mt8183/drivers/spm/spm.c | 24 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/platform_def.h | 7 |
2 files changed, 31 insertions, 0 deletions
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c index dcafd55fd..547af5781 100644 --- a/plat/mediatek/mt8183/drivers/spm/spm.c +++ b/plat/mediatek/mt8183/drivers/spm/spm.c @@ -12,6 +12,21 @@ DEFINE_BAKERY_LOCK(spm_lock); +/* CLK_SCP_CFG_0 */ +#define SPM_CK_OFF_CONTROL (0x3FF) + +/* CLK_SCP_CFG_1 */ +#define SPM_AXI_26M_SEL (0x1) + +/* AP_PLL_CON3 */ +#define SPM_PLL_CONTROL (0x7FAAAAF) + +/* AP_PLL_CON4 */ +#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A) + +/* AP_PLL_CON6 */ +#define PLL_DLY (0x20000) + const char *wakeup_src_str[32] = { [0] = "R12_PCM_TIMER", [1] = "R12_SSPM_WDT_EVENT_B", @@ -324,5 +339,14 @@ void spm_boot_init(void) spm_lock_init(); mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + /* switch ck_off/axi_26m control to SPM */ + mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL); + mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL); + + /* switch PLL/CLKSQ control to SPM */ + mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL); + mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL); + mmio_clrbits_32(AP_PLL_CON6, PLL_DLY); + NOTICE("%s() end\n", __func__); } diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index 0a1e038b3..ad81a3331 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -39,7 +39,14 @@ #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define TOPCKGEN_BASE (IO_PHYS + 0x0) +#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) +#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204) + #define APMIXEDSYS (IO_PHYS + 0xC000) +#define AP_PLL_CON3 (APMIXEDSYS + 0xC) +#define AP_PLL_CON4 (APMIXEDSYS + 0x10) +#define AP_PLL_CON6 (APMIXEDSYS + 0x18) #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) #define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) |