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* intel: mailbox: Ensure time out duration is predictiveChee Hong Ang2020-10-272-2/+4
| | | | | | | | For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
* intel: clear 'PLAT_SEC_ENTRY' in early platform setupChee Hong Ang2020-10-241-2/+4
| | | | | | | | | | Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a
* intel: platform: Include GICv2 makefileAbdul Halim, Muhammad Hadi Asyrafi2020-08-191-4/+8
| | | | | | | | | This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes from commit #1322dc94f7. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48
* plat: intel: Add FPGAINTF configuration to when configuring pinmuxTien Hock Loh2020-06-081-0/+8
| | | | | | | FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
* plat: intel: set DRVSEL and SMPLSEL for DWMMCTien Hock Loh2020-06-085-0/+30
| | | | | | | | DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
* plat: intel: Fix clock configuration bugsTien Hock Loh2020-06-081-34/+42
| | | | | | | | | | | | This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70
* Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integrationSandrine Bailleux2020-02-282-4/+7
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| * intel: Enable EMAC PHY in Intel FPGA platformTien Hock, Loh2020-02-252-4/+7
| | | | | | | | | | | | | | | | This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
* | 16550: Use generic console_t data structureAndre Przywara2020-02-252-2/+2
|/ | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "intel: Change boot source selection" into integrationSandrine Bailleux2020-02-122-2/+2
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| * intel: Change boot source selectionHadi Asyrafi2020-02-032-2/+2
| | | | | | | | | | | | | | | | Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6
* | intel: Extend SiP service to support mailbox's RSUHadi Asyrafi2020-02-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c
* | intel: agilex: Enable uboot BL31 loadingHadi Asyrafi2020-01-291-8/+24
|/ | | | | | | | This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
* intel: Add function to check fpga readinessHadi Asyrafi2020-01-161-1/+3
| | | | | | | | Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
* intel: Add bridge control for FPGA reconfigHadi Asyrafi2020-01-161-0/+1
| | | | | | | | | This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
* intel: System Manager refactoringHadi Asyrafi2020-01-166-198/+14
| | | | | | | Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
* intel: Refactor reset manager driverHadi Asyrafi2020-01-165-234/+3
| | | | | | | | | Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
* intel: Enable bridge access in Intel platformHadi Asyrafi2020-01-165-5/+81
| | | | | | | | | Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
* intel: Modify non secure access functionHadi Asyrafi2020-01-163-1/+9
| | | | | | | | Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
* Merge "intel: Fix memory calibration" into integrationManish Pandey2020-01-141-4/+3
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| * intel: Fix memory calibrationHadi Asyrafi2019-12-301-4/+3
| | | | | | | | | | | | | | | | Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4
* | Remove redundant declarations.Madhukar Pappireddy2020-01-081-1/+0
|/ | | | | | | | In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* intel: Refactor common platform code [5/5]Hadi Asyrafi2019-11-283-25/+16
| | | | | | | | | Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
* intel: Refactor common platform code [4/5]Hadi Asyrafi2019-11-283-578/+2
| | | | | | | | | Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd
* intel: Refactor common platform code [3/5]Hadi Asyrafi2019-11-286-412/+5
| | | | | | | | Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
* intel: Refactor common platform code [2/5]Hadi Asyrafi2019-11-284-230/+2
| | | | | | | | Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
* intel: Refactor common platform code [1/5]Hadi Asyrafi2019-11-2810-343/+33
| | | | | | | | | | | Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
* Invalidate dcache build option for bl2 entry at EL3Hadi Asyrafi2019-09-121-0/+1
| | | | | | | | | | Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
* intel: agilex: Fix psci power domain offHadi Asyrafi2019-09-121-8/+2
| | | | | | | | Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
* Merge "intel: agilex: Clear PLL lostlock bypass mode" into integrationPaul Beesley2019-08-282-0/+13
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| * intel: agilex: Clear PLL lostlock bypass modeHadi Asyrafi2019-08-192-0/+13
| | | | | | | | | | | | | | To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
* | intel: agilex: HMC driver calculate DDR sizeHadi Asyrafi2019-08-191-10/+8
|/ | | | | | | Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
* Merge "intel: agilex: Fix memory controller driver" into integrationPaul Beesley2019-08-152-11/+22
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| * intel: agilex: Fix memory controller driverHadi Asyrafi2019-08-152-11/+22
| | | | | | | | | | | | | | | | Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
* | intel: agilex: Fix reliance on hard coded clock informationHadi Asyrafi2019-08-145-78/+159
|/ | | | | | | Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
* Merge changes from topic "intel-plat-refactor" into integrationSandrine Bailleux2019-08-0711-464/+11
|\ | | | | | | | | | | * changes: intel: Platform common code refactor intel: Platform common code refactor
| * intel: Platform common code refactorHadi Asyrafi2019-08-077-241/+6
| | | | | | | | | | | | | | Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
| * intel: Platform common code refactorHadi Asyrafi2019-08-015-223/+5
| | | | | | | | | | | | | | Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
* | intel: agilex: Fix BL31 memory mappingHadi Asyrafi2019-07-301-1/+1
|/ | | | | | | Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1
* intel: agilex: Fix build errorAmbroise Vincent2019-07-241-1/+3
| | | | | | | | | | | "result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eba8ca ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* intel: Adds support for Agilex platformHadi Asyrafi2019-07-1731-0/+4002
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-16 01:00:28 +0000