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* PSCI: fix limit of 256 CPUs caused by cast to unsigned charGraeme Gregory2020-12-221-2/+12
| | | | | | | | | | | | | | | | | | | | In psci_setup.c psci_init_pwr_domain_node() takes an unsigned char as node_idx which limits it to initialising only the first 256 CPUs. As the calling function does not check for a limit of 256 I think this is a bug so change the unsigned char to uint16_t and change the cast from the calling site in populate_power_domain_tree(). Also update the non_cpu_pwr_domain_node structure lock_index to uint16_t and update the function signature for psci_lock_init() appropriately. Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot exceed the index value. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
* Unify type of "cpu_idx" across PSCI module.Deepika Bhavnani2020-01-101-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
* adding support to enable different personality of the same soc.Pankaj Gupta2019-11-261-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | Same SoC has different personality by creating different number of: - cores - clusters. As a result, the platform specific power domain tree will be created after identify the personality of the SoC. Hence, platform specific power domain tree may not be same for all the personality of the soc. Thus, psci library code will deduce the 'plat_core_count', while populating the power domain tree topology and return the number of cores. PLATFORM_CORE_COUNT will still be valid for a SoC, such that psci_plat_core_count <= PLATFORM_CORE_COUNT. PLATFORM_CORE_COUNT will continued to be defined by platform to create the data structures. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I1f5c47647631cae2dcdad540d64cf09757db7185
* Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov2019-09-131-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-041-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Mark BL31 initialization functionsDaniel Boulby2018-10-031-4/+4
| | | | | | | | | Mark the initialization functions in BL31, such as context management, EHF, RAS and PSCI as __init so that they can be reclaimed by the platform when no longer needed Change-Id: I7446aeee3dde8950b0f410cb766b7a2312c20130 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* PSCI: Fix MISRA defects in common and setup codeAntonio Nino Diaz2018-07-241-34/+36
| | | | | | | MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7. Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* ARMv7 may not support Generic Timer ExtensionEtienne Carriere2017-11-081-0/+2
| | | | | | | | If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* reset2: Add PSCI system_reset2 functionRoberto Vargas2017-10-131-0/+2
| | | | | | | | | | | | This patch implements PSCI_SYSTEM_RESET2 API as defined in PSCI v1.1 specification. The specification allows architectural and vendor-specific resets via this API. In the current specification, there is only one architectural reset, the warm reset. This reset is intended to provide a fast reboot path that guarantees not to reset system main memory. Change-Id: I057bb81a60cd0fe56465dbb5791d8e1cca025bd3 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* mem_protect: Add mem_protect APIRoberto Vargas2017-09-251-0/+5
| | | | | | | | | | This patch adds the generic code that links the psci smc handler with the platform function that implements the mem_protect and mem_check_range functionalities. These functions are optional APIs added in PSCI v1.1 (ARM DEN022D). Change-Id: I3bac1307a5ce2c7a196ace76db8317e8d8c8bb3f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* Use SPDX license identifiersdp-arm2017-05-031-25/+1
| | | | | | | | | | | | To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
* PSCI: Introduce cache and barrier wrappersJeenu Viswambharan2017-03-021-3/+3
| | | | | | | | | | | | | | | | | | | | The PSCI implementation performs cache maintenance operations on its data structures to ensure their visibility to both cache-coherent and non-cache-coherent participants. These cache maintenance operations can be skipped if all PSCI participants are cache-coherent. When HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI participants are cache-coherent. For usage abstraction, this patch introduces wrappers for PSCI cache maintenance and barrier operations used for state coordination: they are effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are applied otherwise. Also refactor local state usage and associated cache operations to make it clearer. Change-Id: I77f17a90cba41085b7188c1345fe5731c99fad87 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Report errata workaround status to consoleJeenu Viswambharan2017-01-301-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The errata reporting policy is as follows: - If an errata workaround is enabled: - If it applies (i.e. the CPU is affected by the errata), an INFO message is printed, confirming that the errata workaround has been applied. - If it does not apply, a VERBOSE message is printed, confirming that the errata workaround has been skipped. - If an errata workaround is not enabled, but would have applied had it been, a WARN message is printed, alerting that errata workaround is missing. The CPU errata messages are printed by both BL1 (primary CPU only) and runtime firmware on debug builds, once for each CPU/errata combination. Relevant output from Juno r1 console when ARM Trusted Firmware is built with PLAT=juno LOG_LEVEL=50 DEBUG=1: VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL1: cortex_a57: errata workaround for 826974 was missing! WARNING: BL1: cortex_a57: errata workaround for 826977 was missing! WARNING: BL1: cortex_a57: errata workaround for 828024 was missing! WARNING: BL1: cortex_a57: errata workaround for 829520 was missing! WARNING: BL1: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL31: cortex_a57: errata workaround for 826974 was missing! WARNING: BL31: cortex_a57: errata workaround for 826977 was missing! WARNING: BL31: cortex_a57: errata workaround for 828024 was missing! WARNING: BL31: cortex_a57: errata workaround for 829520 was missing! WARNING: BL31: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied Also update documentation. Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* PSCI: Introduce PSCI Library argument structureSoby Mathew2016-09-221-3/+4
| | | | | | | | | | | | | | | | | This patch introduces a `psci_lib_args_t` structure which must be passed into `psci_setup()` which is then used to initialize the PSCI library. The `psci_lib_args_t` is a versioned structure so as to enable compatibility checks during library initialization. Both BL31 and SP_MIN are modified to use the new structure. SP_MIN is also modified to add version string and build message as part of its cold boot log just like the other BLs in Trusted Firmware. NOTE: Please be aware that this patch modifies the prototype of `psci_setup()`, which breaks compatibility with EL3 Runtime Firmware (excluding BL31 and SP_MIN) integrated with the PSCI Library. Change-Id: Ic3761db0b790760a7ad664d8a437c72ea5edbcd6
* Merge pull request #702 from jeenu-arm/psci-node-hw-statedanh-arm2016-09-191-0/+2
|\ | | | | Support for PSCI NODE_HW_STATE
| * PSCI: Add support for PSCI NODE_HW_STATE APIJeenu Viswambharan2016-09-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NODE_HW_STATE PSCI API by introducing a new PSCI platform hook (get_node_hw_state). The implementation validates supplied arguments, and then invokes this platform-defined hook and returns its result to the caller. PSCI capabilities are updated accordingly. Also updates porting and firmware design guides. Change-Id: I808e55bdf0c157002a7c104b875779fe50a68a30
* | Flush `psci_plat_pm_ops` after initializationSoby Mathew2016-09-091-0/+7
|/ | | | | | | | | | | | The `psci_plat_pm_ops` global pointer is initialized during cold boot by the primary CPU and will be accessed by the secondary CPUs before enabling data cache during warm boot. This patch adds a missing data cache flush of `psci_plat_psci_ops` after initialization during psci_setup() so that secondaries can see the updated `psci_plat_psci_ops` pointer. Fixes ARM-software/tf-issues#424 Change-Id: Id4554800b5646302b944115a33be69507d53cedb
* AArch32: Add support to PSCI libSoby Mathew2016-08-101-0/+12
| | | | | | | | | | | | | | | | This patch adds AArch32 support to PSCI library, as follows : * The `psci_helpers.S` is implemented for AArch32. * AArch32 version of internal helper function `psci_get_ns_ep_info()` is defined. * The PSCI Library is responsible for the Non Secure context initialization. Hence a library interface `psci_prepare_next_non_secure_ctx()` is introduced to enable EL3 runtime firmware to initialize the non secure context without invoking context management library APIs. Change-Id: I25595b0cc2dbfdf39dbf7c589b875cba33317b9d
* Introduce PSCI Library InterfaceSoby Mathew2016-07-191-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the PSCI Library interface. The major changes introduced are as follows: * Earlier BL31 was responsible for Architectural initialization during cold boot via bl31_arch_setup() whereas PSCI was responsible for the same during warm boot. This functionality is now consolidated by the PSCI library and it does Architectural initialization via psci_arch_setup() during both cold and warm boots. * Earlier the warm boot entry point was always `psci_entrypoint()`. This was not flexible enough as a library interface. Now PSCI expects the runtime firmware to provide the entry point via `psci_setup()`. A new function `bl31_warm_entrypoint` is introduced in BL31 and the previous `psci_entrypoint()` is deprecated. * The `smc_helpers.h` is reorganized to separate the SMC Calling Convention defines from the Trusted Firmware SMC helpers. The former is now in a new header file `smcc.h` and the SMC helpers are moved to Architecture specific header. * The CPU context is used by PSCI for context initialization and restoration after power down (PSCI Context). It is also used by BL31 for SMC handling and context management during Normal-Secure world switch (SMC Context). The `psci_smc_handler()` interface is redefined to not use SMC helper macros thus enabling to decouple the PSCI context from EL3 runtime firmware SMC context. This enables PSCI to be integrated with other runtime firmware using a different SMC context. NOTE: With this patch the architectural setup done in `bl31_arch_setup()` is done as part of `psci_setup()` and hence `bl31_platform_setup()` will be invoked prior to architectural setup. It is highly unlikely that the platform setup will depend on architectural setup and cause any failure. Please be be aware of this change in sequence. Change-Id: I7f497a08d33be234bbb822c28146250cb20dab73
* Introduce `el3_runtime` and `PSCI` librariesSoby Mathew2016-07-181-0/+261
This patch moves the PSCI services and BL31 frameworks like context management and per-cpu data into new library components `PSCI` and `el3_runtime` respectively. This enables PSCI to be built independently from BL31. A new `psci_lib.mk` makefile is introduced which adds the relevant PSCI library sources and gets included by `bl31.mk`. Other changes which are done as part of this patch are: * The runtime services framework is now moved to the `common/` folder to enable reuse. * The `asm_macros.S` and `assert_macros.S` helpers are moved to architecture specific folder. * The `plat_psci_common.c` is moved from the `plat/common/aarch64/` folder to `plat/common` folder. The original file location now has a stub which just includes the file from new location to maintain platform compatibility. Most of the changes wouldn't affect platform builds as they just involve changes to the generic bl1.mk and bl31.mk makefiles. NOTE: THE `plat_psci_common.c` FILE HAS MOVED LOCATION AND THE STUB FILE AT THE ORIGINAL LOCATION IS NOW DEPRECATED. PLATFORMS SHOULD MODIFY THEIR MAKEFILES TO INCLUDE THE FILE FROM THE NEW LOCATION. Change-Id: I6bd87d5b59424995c6a65ef8076d4fda91ad5e86
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