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| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-01-06 14:58:11 +0000 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-03-02 11:00:20 +0000 |
| commit | a10d3632acbd1135648f07c2a998cba8c5c77cfd (patch) | |
| tree | a3e1102a480787af436c363424e7a7821a7695d2 /lib/psci/psci_setup.c | |
| parent | d4593e4713617b455929960eb616c9c09e446dc4 (diff) | |
| download | platform_external_arm-trusted-firmware-a10d3632acbd1135648f07c2a998cba8c5c77cfd.tar.gz platform_external_arm-trusted-firmware-a10d3632acbd1135648f07c2a998cba8c5c77cfd.tar.bz2 platform_external_arm-trusted-firmware-a10d3632acbd1135648f07c2a998cba8c5c77cfd.zip | |
PSCI: Introduce cache and barrier wrappers
The PSCI implementation performs cache maintenance operations on its
data structures to ensure their visibility to both cache-coherent and
non-cache-coherent participants. These cache maintenance operations
can be skipped if all PSCI participants are cache-coherent. When
HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI
participants are cache-coherent.
For usage abstraction, this patch introduces wrappers for PSCI cache
maintenance and barrier operations used for state coordination: they are
effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are
applied otherwise.
Also refactor local state usage and associated cache operations to make
it clearer.
Change-Id: I77f17a90cba41085b7188c1345fe5731c99fad87
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'lib/psci/psci_setup.c')
| -rw-r--r-- | lib/psci/psci_setup.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index 7327b92ed..323dc62cb 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -86,7 +86,7 @@ static void psci_init_pwr_domain_node(unsigned int node_idx, /* Set the power state to OFF state */ svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; - flush_dcache_range((uintptr_t)svc_cpu_data, + psci_flush_dcache_range((uintptr_t)svc_cpu_data, sizeof(*svc_cpu_data)); cm_set_context_by_index(node_idx, @@ -242,9 +242,9 @@ int psci_setup(const psci_lib_args_t *lib_args) /* * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs - * during warm boot before data cache is enabled. + * during warm boot, possibly before data cache is enabled. */ - flush_dcache_range((uintptr_t)&psci_plat_pm_ops, + psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops, sizeof(psci_plat_pm_ops)); /* Initialize the psci capability */ |