From a10d3632acbd1135648f07c2a998cba8c5c77cfd Mon Sep 17 00:00:00 2001 From: Jeenu Viswambharan Date: Fri, 6 Jan 2017 14:58:11 +0000 Subject: PSCI: Introduce cache and barrier wrappers The PSCI implementation performs cache maintenance operations on its data structures to ensure their visibility to both cache-coherent and non-cache-coherent participants. These cache maintenance operations can be skipped if all PSCI participants are cache-coherent. When HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI participants are cache-coherent. For usage abstraction, this patch introduces wrappers for PSCI cache maintenance and barrier operations used for state coordination: they are effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are applied otherwise. Also refactor local state usage and associated cache operations to make it clearer. Change-Id: I77f17a90cba41085b7188c1345fe5731c99fad87 Signed-off-by: Jeenu Viswambharan --- lib/psci/psci_setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/psci/psci_setup.c') diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index 7327b92ed..323dc62cb 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -86,7 +86,7 @@ static void psci_init_pwr_domain_node(unsigned int node_idx, /* Set the power state to OFF state */ svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; - flush_dcache_range((uintptr_t)svc_cpu_data, + psci_flush_dcache_range((uintptr_t)svc_cpu_data, sizeof(*svc_cpu_data)); cm_set_context_by_index(node_idx, @@ -242,9 +242,9 @@ int psci_setup(const psci_lib_args_t *lib_args) /* * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs - * during warm boot before data cache is enabled. + * during warm boot, possibly before data cache is enabled. */ - flush_dcache_range((uintptr_t)&psci_plat_pm_ops, + psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops, sizeof(psci_plat_pm_ops)); /* Initialize the psci capability */ -- cgit v1.2.3