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* fconf: necessary modifications to support fconf in BL31 & SP_MINMadhukar Pappireddy2020-03-111-12/+28
| | | | | | | | | | | | | | | | | | | | Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN. Created few populator() functions which parse HW_CONFIG device tree and registered them with fconf framework. Many of the changes are only applicable for fvp platform. This patch: 1. Adds necessary symbols and sections in BL31, SP_MIN linker script 2. Adds necessary memory map entry for translation in BL31, SP_MIN 3. Creates an abstraction layer for hardware configuration based on fconf framework 4. Adds necessary changes to build flow (makefiles) 5. Minimal callback to read hw_config dtb for capturing properties related to GIC(interrupt-controller node) 6. updates the fconf documentation Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge "Necessary fix in drivers to upgrade to mbedtls-2.18.0" into integrationMark Dykes2020-03-101-1/+1
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| * Necessary fix in drivers to upgrade to mbedtls-2.18.0Madhukar Pappireddy2020-03-081-1/+1
| | | | | | | | | | | | | | Include x509.h header file explicitly. Update docs. Change-Id: If2e52c2cd3056654406b7b6779b67eea5cc04a48 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | docs: qemu: Add instructions to boot using FIP imageSumit Garg2020-03-091-1/+52
| | | | | | | | | | | | | | | | | | Update qemu documentation with instructions to boot using FIP image. Also, add option to build TF-A with TBBR and firmware encryption enabled. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: Ib3af485d413cd595352034c82c2268d7f4cb120a
* | docs: Update docs with firmware encryption featureSumit Garg2020-03-096-1/+122
| | | | | | | | | | | | | | Update documentation with optional firmware encryption feature. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I26691b18e1ee52a73090954260f26f2865c4e05a
* | drivers: crypto: Add authenticated decryption frameworkSumit Garg2020-03-061-0/+6
|/ | | | | | | | | | Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
* Merge "Update pathnames in maintainers.rst file" into integrationSandrine Bailleux2020-03-031-9/+6
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| * Update pathnames in maintainers.rst fileSandrine Bailleux2020-02-261-9/+6
| | | | | | | | | | | | | | | | | | | | | | The maintainers.rst file lists files and directories that each contributor looks after in the TF-A source tree. As files and directories move around over time, some pathnames had become invalid. Fix them, either by updating the path if it has just moved, or deleting it altogether if it doesn't seem to exist anymore. Change-Id: Idb6ff4d8d0b593138d4f555ec206abcf68b0064f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | doc: Fix variables names in TBBR CoT documentationSandrine Bailleux2020-03-021-14/+14
| | | | | | | | | | | | | | | | | | | | In commit 516beb585c23056820a854b12c77a6f62cbc5c8b ("TBB: apply TBBR naming convention to certificates and extensions"), some of the variables used in the TBBR chain of trust got renamed but the documentation did not get properly updated everywhere to reflect these changes. Change-Id: Ie8e2146882c2d3538c5b8c968d1bdaf5ea2a6e53 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Add Cortex-A65/AE to the supported FVP listImre Kis2020-02-271-1/+3
| | | | | | | | | | | | | | | | Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the supported Arm Fixed Virtual Platforms. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: Ibfcaec11bc75549d60455e96858d79b679e71e5e
* | Merge "change-log: Add fconf entry" into integrationSandrine Bailleux2020-02-271-0/+1
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| * | change-log: Add fconf entryLouis Mayencourt2020-02-261-0/+1
| | | | | | | | | | | | | | | Change-Id: I6686f172d0c24f6c457a39cdf4debcbf05475540 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge "amlogic/axg: Add documentation page to the index" into integrationSandrine Bailleux2020-02-261-1/+2
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| * | | amlogic/axg: Add documentation page to the indexSandrine Bailleux2020-02-261-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | It is needed to make it appear in the table of contents. Right now, all Amlogic documentation pages appear under the "Platform ports" section, except the AXG one. Change-Id: Ibcfc3b156888d2a9574953578978b629e185c708 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | Merge "tools: Small improvement to print_memory_map script" into integrationSandrine Bailleux2020-02-261-0/+5
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| * | tools: Small improvement to print_memory_map scriptLouis Mayencourt2020-02-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch: - Add the __COHERENT_RAM_START__ and __COHERENT_RAM_END__ symbols. - Improve how the symbols are found with a regex. - Add a build option to revert the memory layout output. Change-Id: I54ec660261431bc98d78acb0f80e3d95bc5397ac Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge "SPMD: generate and add Secure Partition blobs into FIP" into integrationSandrine Bailleux2020-02-251-0/+5
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| * | SPMD: generate and add Secure Partition blobs into FIPManish Pandey2020-02-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now TF-A allows limited number of external images to be made part of FIP. With SPM coming along, there may exist multiple SP packages which need to be inserted into FIP. To achieve this we need a more scalable approach to feed SP packages to FIP. This patch introduces changes in build system to generate and add SP packages into FIP based on information provided by platform. Platform provides information in form of JSON which contains layout description of available Secure Partitions. JSON parser script is invoked by build system early on and generates a makefile which updates FIP, SPTOOL and FDT arguments which will be used by build system later on for final packaging. "SP_LAYOUT_FILE" passed as a build argument and can be outside of TF-A tree. This option will be used only when SPD=spmd. For each SP, generated makefile will have following entries - FDT_SOURCES += sp1.dts - SPTOOL_ARGS += -i sp1.img:sp1.dtb -o sp1.pkg - FIP_ARGS += --blob uuid=XXXX-XXX...,file=SP1.pkg Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib6a9c064400caa3cd825d9886008a3af67741af7
* | | cpus: higher performance non-cacheable load forwardingVarun Wadekar2020-02-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | Merge "Update docs with PMU security information" into integrationManish Pandey2020-02-194-3/+261
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| * | Update docs with PMU security informationPetre-Ionut Tudor2020-02-124-3/+261
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds information on the PMU configuration registers and security considerations related to the PMU. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I36b15060b9830a77d3f47f293c0a6dafa3c581fb
* | | FVP: Fix BL31 load address and image size for RESET_TO_BL31=1Alexei Fedorov2020-02-181-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When TF-A is built with RESET_TO_BL31=1 option, BL31 is the first image to be run and should have all the memory allocated to it except for the memory reserved for Shared RAM at the start of Trusted SRAM. This patch fixes FVP BL31 load address and its image size for RESET_TO_BL31=1 option. BL31 startup address should be set to 0x400_1000 and its maximum image size to the size of Trusted SRAM minus the first 4KB of shared memory. Loading BL31 at 0x0402_0000 as it is currently stated in '\docs\plat\arm\fvp\index.rst' causes EL3 exception when the image size gets increased (i.e. building with LOG_LEVEL=50) but doesn't exceed 0x3B000 not causing build error. Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | Merge "doc: debugfs remove references section and add topic to components ↵Mark Dykes2020-02-122-15/+9
|\ \ \ | |_|/ |/| | | | | index" into integration
| * | doc: debugfs remove references section and add topic to components indexOlivier Deprez2020-02-122-15/+9
| |/ | | | | | | | | Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I8c2e6dc98f2f30a81f4f80cc0ca1232fed7a53c9
* | Merge changes from topic "lm/fconf" into integrationSandrine Bailleux2020-02-117-0/+192
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: arm-io: Panic in case of io setup failure MISRA fix: Use boolean essential type fconf: Add documentation fconf: Move platform io policies into fconf fconf: Add mbedtls shared heap as property fconf: Add TBBR disable_authentication property fconf: Add dynamic config DTBs info as property fconf: Populate properties from dtb during bl2 setup fconf: Load config dtb from bl1 fconf: initial commit
| * | fconf: Add documentationLouis Mayencourt2020-02-076-0/+187
| | | | | | | | | | | | | | | Change-Id: I606f9491fb6deebc6845c5b9d7db88fc5c895bd9 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * | fconf: Move platform io policies into fconfLouis Mayencourt2020-02-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the firmware configuration framework to store the io_policies information inside the configuration device tree instead of the static structure in the code base. The io_policies required by BL1 can't be inside the dtb, as this one is loaded by BL1, and only available at BL2. This change currently only applies to FVP platform. Change-Id: Ic9c1ac3931a4a136aa36f7f58f66d3764c1bfca1 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge "Make PAC demangling more generic" into integrationMark Dykes2020-02-101-1/+1
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| * | | Make PAC demangling more genericAlexei Fedorov2020-02-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, address demangling is only used by the backtrace functionality. However, at some point, other parts of the TF-A codebase may want to use it. The 'demangle_address' function is replaced with a single XPACI instruction which is also added in 'do_crash_reporting()'. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I4424dcd54d5bf0a5f9b2a0a84c4e565eec7329ec
* | | | Merge changes from topic "amlogic/axg" into integrationManish Pandey2020-02-102-0/+35
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: amlogic: axg: Add a build flag when using ATOS as BL32 amlogic: axg: Add support for the A113D (AXG) platform
| * | | | amlogic: axg: Add a build flag when using ATOS as BL32Carlo Caione2020-02-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used. Since we are not aware of any Amlogic platform shipping a 64bit version of ATOS we can hardcode OPTEE_AARCH32 / MODE_RW_32 when using ATOS. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Iaea47cf6dc48bf8a646056761f02fb81b41c78a3
| * | | | amlogic: axg: Add support for the A113D (AXG) platformCarlo Caione2020-02-062-0/+34
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the preliminary support for the Amlogic A113D (AXG) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot, Linux and chainloading BL32 (ATOS). Tested on a A113D board. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809
* | / / plat/arm/sgi: introduce number of chips macroVijayenthiran Subramaniam2020-02-071-0/+5
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with multi-chip support to define number of chiplets on the platform. By default, this flag is set to 1 and does not affect the existing single chip platforms. For multi-chip platforms, override the default value of CSS_SGI_CHIP_COUNT with the number of chiplets supported on the platform. As an example, the command below sets the number of chiplets to two on the RD-N1-Edge multi-chip platform: export CROSS_COMPILE=<path-to-cross-compiler> make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* | | Merge "Adds option to read ROTPK from registers for FVP" into integrationSandrine Bailleux2020-02-073-15/+20
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| * | Adds option to read ROTPK from registers for FVPMax Shvetsov2020-02-063-16/+21
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables usage of ARM_ROTPK_LOCATION=regs for FVP board. Removes hard-coded developer keys. Instead, setting ARM_ROTPK_LOCATION=devel_* takes keys from default directory. In case of ROT_KEY specified - generates a new hash and replaces the original. Note: Juno board was tested by original feature author and was not tested for this patch since we don't have access to the private key. Juno implementation was moved to board-specific file without changing functionality. It is not known whether byte-swapping is still needed for this platform. Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* | doc: Split and expand coding style documentationPaul Beesley2020-02-066-331/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch expands the coding style documentation, splitting it into two documents: the core style rules and extended guidelines. Note that it does not redefine or change the coding style (aside from section 4.6.2) - generally, it is only documenting the existing style in more detail. The aim is for the coding style to be more readable and, in turn, for it to be followed by more people. We can use this as a more concrete reference when discussing the accepted style with external contributors. Change-Id: I87405ace9a879d7f81e6b0b91b93ca69535e50ff Signed-off-by: Paul Beesley <paul.beesley@arm.com> Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
* | Merge "doc: Remove backquotes from external hyperlinks" into integrationGyörgy Szing2020-02-062-5/+5
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| * doc: Remove backquotes from external hyperlinksImre Kis2020-02-032-5/+5
| | | | | | | | | | | | | | | | | | | | Since Sphinx 2.3.0 backquotes are replaced to \textasciigrave{} during building latexpdf. Using this element in a \sphinxhref{} breaks the build. In order to avoid this error backquotes must not be used in external hyperlinks. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: Ie3cf454427e3d5a7b7f9829b42be45aebda7f0dd
* | doc: qemu: fix and update documentationMasahiro Yamada2020-02-031-5/+5
|/ | | | | | | | | | | | | | | | | | | | | | The current URL for QEMU_EFI.fd is not found. Update the link to point to the new one. If you run the shell command as instructed, you will see this error: qemu-system-aarch64: keep_bootcon: Could not open 'keep_bootcon': No such file or directory The part "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" is the kernel parameter, so it must be quoted. As of writing, QEMU v4.2.0 is the latest, but it does not work for TF-A (It has been fixed in the mainline.) QEMU v4.1.0 works fine. With those issues addressed, I succeeded in booting the latest kernel. Tested with QEMU v4.1.0 and Linux 5.5 (defconfig with no modification). Update the tested versions. Change-Id: Ic85db0e688d67b1803ff890047d37de3f3db2daa Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge "Add support for documentation build as a target in Makefile" into ↵Sandrine Bailleux2020-01-312-8/+15
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| * Add support for documentation build as a target in MakefileMadhukar Pappireddy2020-01-292-8/+15
| | | | | | | | | | | | | | | | Command to build HTML-formatted pages from docs: make doc Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge changes from topic "sb/select-cot" into integrationSandrine Bailleux2020-01-301-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: Introduce COT build option cert_create: Remove references to TBBR in common code cert_create: Introduce COT build option cert_create: Introduce TBBR CoT makefile
| * | Introduce COT build optionSandrine Bailleux2020-01-291-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | Allows to select the chain of trust to use when the Trusted Boot feature is enabled. This affects both the cert_create tool and the firmware itself. Right now, the only available CoT is TBBR. Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Merge changes I0fb7cf79,Ia8eb4710 into integrationSoby Mathew2020-01-291-0/+4
|\ \ | | | | | | | | | | | | | | | * changes: qemu: Implement qemu_system_off via semihosting. qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
| * | qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.Andrew Walbran2020-01-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This lets the Linux kernel or any other image which expects an FDT in x0 be loaded directly as BL33 without a separate bootloader on QEMU. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
* | | Measured Boot: add function for hash calculationAlexei Fedorov2020-01-281-0/+5
| |/ |/| | | | | | | | | | | | | This patch adds 'calc_hash' function using Mbed TLS library required for Measured Boot support. Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge "Neovers N1: added support to update presence of External LLC" into ↵Manish Pandey2020-01-281-0/+5
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| * | Neovers N1: added support to update presence of External LLCManish Pandey2020-01-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
* | | TSP: add PIE supportMasahiro Yamada2020-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | This implementation simply mimics that of BL31. Change-Id: Ibbaa4ca012d38ac211c52b0b3e97449947160e07 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | BL2_AT_EL3: add PIE supportMasahiro Yamada2020-01-241-1/+1
|/ / | | | | | | | | | | | | | | | | | | This implementation simply mimics that of BL31. I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case. It would make the linker script a bit uglier. Change-Id: If3215abd99f2758dfb232e44b50320d04eba808b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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