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authorManish Pandey <manish.pandey2@arm.com>2020-01-24 11:54:44 +0000
committerManish Pandey <manish.pandey2@arm.com>2020-01-27 14:44:35 +0000
commitf2d6b4ee5740245a92fd511180f7eebc6736a80b (patch)
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parent9054018bd5c12b16ef55ea41fcf8cdb15a24ae18 (diff)
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Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
Diffstat (limited to 'docs')
-rw-r--r--docs/design/cpu-specific-build-macros.rst5
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7fa027f42..f3096b418 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired.
as recommended in section "4.7 Non-Temporal Loads/Stores" of the
`Cortex-A57 Software Optimization Guide`_.
+- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+ level cache(LLC) is present in the system, and that the DataSource field
+ on the master CHI interface indicates when data is returned from the LLC.
+ This is used to control how the LL_CACHE* PMU events count.
+
--------------
*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*