diff options
| author | Manish Pandey <manish.pandey2@arm.com> | 2020-01-28 08:18:56 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-01-28 08:18:56 +0000 |
| commit | 91ff490d75a89607a0b19577275e8134b8ffa74d (patch) | |
| tree | 209911c71f5cd6436ad6e1cdf89582013f8caefc /docs | |
| parent | 0281e60c3d59d7552a589ecae1b1223b9dededd1 (diff) | |
| parent | f2d6b4ee5740245a92fd511180f7eebc6736a80b (diff) | |
| download | platform_external_arm-trusted-firmware-91ff490d75a89607a0b19577275e8134b8ffa74d.tar.gz platform_external_arm-trusted-firmware-91ff490d75a89607a0b19577275e8134b8ffa74d.tar.bz2 platform_external_arm-trusted-firmware-91ff490d75a89607a0b19577275e8134b8ffa74d.zip | |
Merge "Neovers N1: added support to update presence of External LLC" into integration
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 7fa027f42..f3096b418 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired. as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_. +- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last + level cache(LLC) is present in the system, and that the DataSource field + on the master CHI interface indicates when data is returned from the LLC. + This is used to control how the LL_CACHE* PMU events count. + -------------- *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* |