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* xilinx: versal: PLM to ATF handoverVenkatesh Yadav Abbarapu2020-01-231-0/+8
| | | | | | | | Parse the parameter structure the PLM populates, to populate the bl32 and bl33 image structures. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
* plat: xilinx: versal: Make silicon default build targetSiva Durga Prasad Paladugu2020-01-151-1/+1
| | | | | | | | | | This patch makes default build target as silicon instead of QEMU. The default can be overwritten by specifying it through build flag VERSAL_PLATFORM. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ia4cb1df1f206db3e514e8ce969acca875e973ace
* doc: Reformat platform port documentsPaul Beesley2019-05-221-0/+35
The platform port documents are not very standardised right now and they don't integrate properly into the document tree so: 1) Make sure each port has a proper name and title (incl. owner) 2) Correct use of headings, subheadings, etc in each port 3) Resolve any naming conflicts between documents Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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