Commit message (Expand) | Author | Age | Files | Lines | |
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* | xilinx: versal: PLM to ATF handover | Venkatesh Yadav Abbarapu | 2020-01-23 | 1 | -0/+8 |
* | plat: xilinx: versal: Make silicon default build target | Siva Durga Prasad Paladugu | 2020-01-15 | 1 | -1/+1 |
* | doc: Reformat platform port documents | Paul Beesley | 2019-05-22 | 1 | -0/+35 |