diff options
Diffstat (limited to 'plat/nvidia/tegra/include')
22 files changed, 727 insertions, 1659 deletions
diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h index a0d02c949..401a07a24 100644 --- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h +++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h @@ -19,11 +19,6 @@ #define TEGRA_RESET_ID_GPCDMA U(70) /** - * Clock identifier for the SE device - */ -#define TEGRA_CLK_SE U(124) - -/** * Function to initialise the IPC with the bpmp */ int32_t tegra_bpmp_ipc_init(void); diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h index 54336b044..e5ab600b4 100644 --- a/plat/nvidia/tegra/include/drivers/flowctrl.h +++ b/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,8 @@ #include <lib/mmio.h> +#include <stdbool.h> + #include <tegra_def.h> #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h index 4470b6b8b..5f1bb4f28 100644 --- a/plat/nvidia/tegra/include/drivers/mce.h +++ b/plat/nvidia/tegra/include/drivers/mce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,7 +69,6 @@ int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); -int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); void mce_update_cstate_info(const mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index d5ef60d0c..cc8509526 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +11,6 @@ void tegra_memctrl_setup(void); void tegra_memctrl_restore_settings(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); -void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_disable_ahb_redirection(void); void tegra_memctrl_clear_pending_interrupts(void); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index a4085e247..9af3027ea 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,58 +8,9 @@ #ifndef MEMCTRL_V2_H #define MEMCTRL_V2_H -#include <tegra_def.h> - -#ifndef __ASSEMBLER__ - -#include <lib/mmio.h> -#include <stdint.h> - -/******************************************************************************* - * Structure to hold the transaction override settings to use to override - * client inputs - ******************************************************************************/ -typedef struct mc_txn_override_cfg { - uint32_t offset; - uint8_t cgid_tag; -} mc_txn_override_cfg_t; - -#define mc_make_txn_override_cfg(off, val) \ - { \ - .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ - .cgid_tag = MC_TXN_OVERRIDE_ ## val \ - } - -/******************************************************************************* - * Structure to hold the Stream ID to use to override client inputs - ******************************************************************************/ -typedef struct mc_streamid_override_cfg { - uint32_t offset; - uint8_t stream_id; -} mc_streamid_override_cfg_t; +#include <arch.h> -/******************************************************************************* - * Structure to hold the Stream ID Security Configuration settings - ******************************************************************************/ -typedef struct mc_streamid_security_cfg { - char *name; - uint32_t offset; - int override_enable; - int override_client_inputs; - int override_client_ns_flag; -} mc_streamid_security_cfg_t; - -#define OVERRIDE_DISABLE 1U -#define OVERRIDE_ENABLE 0U -#define CLIENT_FLAG_SECURE 0U -#define CLIENT_FLAG_NON_SECURE 1U -#define CLIENT_INPUTS_OVERRIDE 1U -#define CLIENT_INPUTS_NO_OVERRIDE 0U -/******************************************************************************* - * StreamID to indicate no SMMU translations (requests to be steered on the - * SMMU bypass path) - ******************************************************************************/ -#define MC_STREAM_ID_MAX 0x7FU +#include <tegra_def.h> /******************************************************************************* * Memory Controller SMMU Bypass config register @@ -74,29 +26,38 @@ typedef struct mc_streamid_security_cfg { #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) -#define mc_make_sec_cfg(off, ns, ovrrd, access) \ +#ifndef __ASSEMBLER__ + +#include <assert.h> + +typedef struct mc_regs { + uint32_t reg; + uint32_t val; +} mc_regs_t; + +#define mc_smmu_bypass_cfg \ { \ - .name = # off, \ - .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ - MC_STREAMID_OVERRIDE_CFG_ ## off), \ - .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ - .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ - .override_enable = OVERRIDE_ ## access \ + .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ + .val = 0x00000000U, \ } -/******************************************************************************* - * Structure to hold Memory Controller's Configuration settings - ******************************************************************************/ -typedef struct tegra_mc_settings { - const uint32_t *streamid_override_cfg; - uint32_t num_streamid_override_cfgs; - const mc_streamid_security_cfg_t *streamid_security_cfg; - uint32_t num_streamid_security_cfgs; - const mc_txn_override_cfg_t *txn_override_cfg; - uint32_t num_txn_override_cfgs; - void (*reconfig_mss_clients)(void); - void (*set_txn_overrides)(void); -} tegra_mc_settings_t; +#define _START_OF_TABLE_ \ + { \ + .reg = 0xCAFE05C7U, \ + .val = 0x00000000U, \ + } + +#define _END_OF_TABLE_ \ + { \ + .reg = 0xFFFFFFFFU, \ + .val = 0xFFFFFFFFU, \ + } + +#endif /* __ASSEMBLER__ */ + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> static inline uint32_t tegra_mc_read_32(uint32_t off) { @@ -108,6 +69,7 @@ static inline void tegra_mc_write_32(uint32_t off, uint32_t val) mmio_write_32(TEGRA_MC_BASE + off, val); } +#if defined(TEGRA_MC_STREAMID_BASE) static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) { return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); @@ -116,54 +78,21 @@ static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) { mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); + assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val); } +#endif -#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ - ((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ - MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) - -#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \ - MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED +void plat_memctrl_setup(void); -#define mc_set_tsa_passthrough(client) \ - { \ - mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ - (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ - (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ - (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ - } - -#define mc_set_tsa_w_passthrough(client) \ - { \ - mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ - (TSA_CONFIG_STATIC0_CSW_RESET_W & \ - (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ - (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ - } - -#define mc_set_tsa_r_passthrough(client) \ - { \ - mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \ - (TSA_CONFIG_STATIC0_CSR_RESET_R & \ - (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ - (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ - } - -#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \ - { \ - tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ - MC_TXN_OVERRIDE_##normal_axi_id | \ - MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \ - MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \ - MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ - } +void plat_memctrl_restore(void); +mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void); /******************************************************************************* - * Handler to read memory configuration settings + * Handler to save MC settings before "System Suspend" to TZDRAM * - * Implemented by SoCs under tegra/soc/txxx + * Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl ******************************************************************************/ -tegra_mc_settings_t *tegra_get_mc_settings(void); +void tegra_mc_save_context(uint64_t mc_ctx_addr); /******************************************************************************* * Handler to program the scratch registers with TZDRAM settings for the diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h index 32252a28b..8752b84c6 100644 --- a/plat/nvidia/tegra/include/drivers/pmc.h +++ b/plat/nvidia/tegra/include/drivers/pmc.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,27 +19,37 @@ #define PMC_DPD_ENABLE_0 U(0x24) #define PMC_PWRGATE_STATUS U(0x38) #define PMC_PWRGATE_TOGGLE U(0x30) -#define PMC_SECURE_SCRATCH0 U(0xb0) -#define PMC_SECURE_SCRATCH5 U(0xc4) +#define PMC_SCRATCH1 U(0x54) #define PMC_CRYPTO_OP_0 U(0xf4) #define PMC_TOGGLE_START U(0x100) +#define PMC_SCRATCH31 U(0x118) +#define PMC_SCRATCH32 U(0x11C) +#define PMC_SCRATCH33 U(0x120) #define PMC_SCRATCH39 U(0x138) +#define PMC_SCRATCH40 U(0x13C) #define PMC_SCRATCH41 U(0x140) -#define PMC_SECURE_SCRATCH6 U(0x224) -#define PMC_SECURE_SCRATCH7 U(0x228) -#define PMC_SECURE_DISABLE2 U(0x2c4) +#define PMC_SCRATCH42 U(0x144) +#define PMC_SCRATCH43 U(0x22C) +#define PMC_SCRATCH44 U(0x230) +#define PMC_SCRATCH45 U(0x234) +#define PMC_SCRATCH46 U(0x238) +#define PMC_SCRATCH47 U(0x23C) +#define PMC_SCRATCH48 U(0x240) +#define PMC_SCRATCH50 U(0x248) +#define PMC_SCRATCH51 U(0x24C) +#define PMC_TSC_MULT_0 U(0x2B4) +#define PMC_STICKY_BIT U(0x2C0) +#define PMC_SECURE_DISABLE2 U(0x2C4) #define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) -#define PMC_SECURE_SCRATCH8 U(0x300) -#define PMC_SECURE_SCRATCH79 U(0x41c) #define PMC_FUSE_CONTROL_0 U(0x450) -#define PMC_SECURE_SCRATCH22 U(0x338) -#define PMC_SECURE_DISABLE3 U(0x2d8) +#define PMC_SECURE_DISABLE3 U(0x2D8) #define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) #define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) +#define PMC_SECURE_SCRATCH22 U(0x338) #define PMC_SECURE_SCRATCH34 U(0x368) #define PMC_SECURE_SCRATCH35 U(0x36c) -#define PMC_SECURE_SCRATCH80 U(0xa98) -#define PMC_SECURE_SCRATCH119 U(0xb34) +#define PMC_SCRATCH56 U(0x600) +#define PMC_SCRATCH57 U(0x604) #define PMC_SCRATCH201 U(0x844) static inline uint32_t tegra_pmc_read_32(uint32_t off) diff --git a/plat/nvidia/tegra/include/drivers/security_engine.h b/plat/nvidia/tegra/include/drivers/security_engine.h index 8a249249b..5ae625793 100644 --- a/plat/nvidia/tegra/include/drivers/security_engine.h +++ b/plat/nvidia/tegra/include/drivers/security_engine.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,5 +55,6 @@ void tegra_se_init(void); int tegra_se_suspend(void); void tegra_se_resume(void); int tegra_se_save_tzram(void); +int32_t tegra_se_save_sha256_hash(uint64_t bl31_base, uint32_t src_len_inbyte); #endif /* SECURITY_ENGINE_H */ diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h index 424a91aea..1de9af6e5 100644 --- a/plat/nvidia/tegra/include/drivers/smmu.h +++ b/plat/nvidia/tegra/include/drivers/smmu.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,566 +13,7 @@ #include <memctrl_v2.h> #include <tegra_def.h> -/******************************************************************************* - * SMMU Register constants - ******************************************************************************/ -#define SMMU_CBn_SCTLR (0x0U) -#define SMMU_CBn_SCTLR_STAGE2 (0x0U) #define SMMU_CBn_ACTLR (0x4U) -#define SMMU_CBn_RESUME (0x8U) -#define SMMU_CBn_TCR2 (0x10U) -#define SMMU_CBn_TTBR0_LO (0x20U) -#define SMMU_CBn_TTBR0_HI (0x24U) -#define SMMU_CBn_TTBR1_LO (0x28U) -#define SMMU_CBn_TTBR1_HI (0x2cU) -#define SMMU_CBn_TCR_LPAE (0x30U) -#define SMMU_CBn_TCR (0x30U) -#define SMMU_CBn_TCR_EAE_1 (0x30U) -#define SMMU_CBn_TCR (0x30U) -#define SMMU_CBn_CONTEXTIDR (0x34U) -#define SMMU_CBn_CONTEXTIDR_EAE_1 (0x34U) -#define SMMU_CBn_PRRR_MAIR0 (0x38U) -#define SMMU_CBn_NMRR_MAIR1 (0x3cU) -#define SMMU_CBn_SMMU_CBn_PAR (0x50U) -#define SMMU_CBn_SMMU_CBn_PAR0 (0x50U) -#define SMMU_CBn_SMMU_CBn_PAR1 (0x54U) -/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x50U) */ -/* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x54U) */ -#define SMMU_CBn_FSR (0x58U) -#define SMMU_CBn_FSRRESTORE (0x5cU) -#define SMMU_CBn_FAR_LO (0x60U) -#define SMMU_CBn_FAR_HI (0x64U) -#define SMMU_CBn_FSYNR0 (0x68U) -#define SMMU_CBn_IPAFAR_LO (0x70U) -#define SMMU_CBn_IPAFAR_HI (0x74U) -#define SMMU_CBn_TLBIVA_LO (0x600U) -#define SMMU_CBn_TLBIVA_HI (0x604U) -#define SMMU_CBn_TLBIVA_AARCH_32 (0x600U) -#define SMMU_CBn_TLBIVAA_LO (0x608U) -#define SMMU_CBn_TLBIVAA_HI (0x60cU) -#define SMMU_CBn_TLBIVAA_AARCH_32 (0x608U) -#define SMMU_CBn_TLBIASID (0x610U) -#define SMMU_CBn_TLBIALL (0x618U) -#define SMMU_CBn_TLBIVAL_LO (0x620U) -#define SMMU_CBn_TLBIVAL_HI (0x624U) -#define SMMU_CBn_TLBIVAL_AARCH_32 (0x618U) -#define SMMU_CBn_TLBIVAAL_LO (0x628U) -#define SMMU_CBn_TLBIVAAL_HI (0x62cU) -#define SMMU_CBn_TLBIVAAL_AARCH_32 (0x628U) -#define SMMU_CBn_TLBIIPAS2_LO (0x630U) -#define SMMU_CBn_TLBIIPAS2_HI (0x634U) -#define SMMU_CBn_TLBIIPAS2L_LO (0x638U) -#define SMMU_CBn_TLBIIPAS2L_HI (0x63cU) -#define SMMU_CBn_TLBSYNC (0x7f0U) -#define SMMU_CBn_TLBSTATUS (0x7f4U) -#define SMMU_CBn_ATSR (0x800U) -#define SMMU_CBn_PMEVCNTR0 (0xe00U) -#define SMMU_CBn_PMEVCNTR1 (0xe04U) -#define SMMU_CBn_PMEVCNTR2 (0xe08U) -#define SMMU_CBn_PMEVCNTR3 (0xe0cU) -#define SMMU_CBn_PMEVTYPER0 (0xe80U) -#define SMMU_CBn_PMEVTYPER1 (0xe84U) -#define SMMU_CBn_PMEVTYPER2 (0xe88U) -#define SMMU_CBn_PMEVTYPER3 (0xe8cU) -#define SMMU_CBn_PMCFGR (0xf00U) -#define SMMU_CBn_PMCR (0xf04U) -#define SMMU_CBn_PMCEID (0xf20U) -#define SMMU_CBn_PMCNTENSE (0xf40U) -#define SMMU_CBn_PMCNTENCLR (0xf44U) -#define SMMU_CBn_PMCNTENSET (0xf48U) -#define SMMU_CBn_PMINTENCLR (0xf4cU) -#define SMMU_CBn_PMOVSCLR (0xf50U) -#define SMMU_CBn_PMOVSSET (0xf58U) -#define SMMU_CBn_PMAUTHSTATUS (0xfb8U) -#define SMMU_GNSR0_CR0 (0x0U) -#define SMMU_GNSR0_CR2 (0x8U) -#define SMMU_GNSR0_ACR (0x10U) -#define SMMU_GNSR0_IDR0 (0x20U) -#define SMMU_GNSR0_IDR1 (0x24U) -#define SMMU_GNSR0_IDR2 (0x28U) -#define SMMU_GNSR0_IDR7 (0x3cU) -#define SMMU_GNSR0_GFAR_LO (0x40U) -#define SMMU_GNSR0_GFAR_HI (0x44U) -#define SMMU_GNSR0_GFSR (0x48U) -#define SMMU_GNSR0_GFSRRESTORE (0x4cU) -#define SMMU_GNSR0_GFSYNR0 (0x50U) -#define SMMU_GNSR0_GFSYNR1 (0x54U) -#define SMMU_GNSR0_GFSYNR1_v2 (0x54U) -#define SMMU_GNSR0_TLBIVMID (0x64U) -#define SMMU_GNSR0_TLBIALLNSNH (0x68U) -#define SMMU_GNSR0_TLBIALLH (0x6cU) -#define SMMU_GNSR0_TLBGSYNC (0x70U) -#define SMMU_GNSR0_TLBGSTATUS (0x74U) -#define SMMU_GNSR0_TLBIVAH_LO (0x78U) -#define SMMU_GNSR0_TLBIVALH64_LO (0xb0U) -#define SMMU_GNSR0_TLBIVALH64_HI (0xb4U) -#define SMMU_GNSR0_TLBIVMIDS1 (0xb8U) -#define SMMU_GNSR0_TLBIVAH64_LO (0xc0U) -#define SMMU_GNSR0_TLBIVAH64_HI (0xc4U) -#define SMMU_GNSR0_SMR0 (0x800U) -#define SMMU_GNSR0_SMRn (0x800U) -#define SMMU_GNSR0_SMR1 (0x804U) -#define SMMU_GNSR0_SMR2 (0x808U) -#define SMMU_GNSR0_SMR3 (0x80cU) -#define SMMU_GNSR0_SMR4 (0x810U) -#define SMMU_GNSR0_SMR5 (0x814U) -#define SMMU_GNSR0_SMR6 (0x818U) -#define SMMU_GNSR0_SMR7 (0x81cU) -#define SMMU_GNSR0_SMR8 (0x820U) -#define SMMU_GNSR0_SMR9 (0x824U) -#define SMMU_GNSR0_SMR10 (0x828U) -#define SMMU_GNSR0_SMR11 (0x82cU) -#define SMMU_GNSR0_SMR12 (0x830U) -#define SMMU_GNSR0_SMR13 (0x834U) -#define SMMU_GNSR0_SMR14 (0x838U) -#define SMMU_GNSR0_SMR15 (0x83cU) -#define SMMU_GNSR0_SMR16 (0x840U) -#define SMMU_GNSR0_SMR17 (0x844U) -#define SMMU_GNSR0_SMR18 (0x848U) -#define SMMU_GNSR0_SMR19 (0x84cU) -#define SMMU_GNSR0_SMR20 (0x850U) -#define SMMU_GNSR0_SMR21 (0x854U) -#define SMMU_GNSR0_SMR22 (0x858U) -#define SMMU_GNSR0_SMR23 (0x85cU) -#define SMMU_GNSR0_SMR24 (0x860U) -#define SMMU_GNSR0_SMR25 (0x864U) -#define SMMU_GNSR0_SMR26 (0x868U) -#define SMMU_GNSR0_SMR27 (0x86cU) -#define SMMU_GNSR0_SMR28 (0x870U) -#define SMMU_GNSR0_SMR29 (0x874U) -#define SMMU_GNSR0_SMR30 (0x878U) -#define SMMU_GNSR0_SMR31 (0x87cU) -#define SMMU_GNSR0_SMR32 (0x880U) -#define SMMU_GNSR0_SMR33 (0x884U) -#define SMMU_GNSR0_SMR34 (0x888U) -#define SMMU_GNSR0_SMR35 (0x88cU) -#define SMMU_GNSR0_SMR36 (0x890U) -#define SMMU_GNSR0_SMR37 (0x894U) -#define SMMU_GNSR0_SMR38 (0x898U) -#define SMMU_GNSR0_SMR39 (0x89cU) -#define SMMU_GNSR0_SMR40 (0x8a0U) -#define SMMU_GNSR0_SMR41 (0x8a4U) -#define SMMU_GNSR0_SMR42 (0x8a8U) -#define SMMU_GNSR0_SMR43 (0x8acU) -#define SMMU_GNSR0_SMR44 (0x8b0U) -#define SMMU_GNSR0_SMR45 (0x8b4U) -#define SMMU_GNSR0_SMR46 (0x8b8U) -#define SMMU_GNSR0_SMR47 (0x8bcU) -#define SMMU_GNSR0_SMR48 (0x8c0U) -#define SMMU_GNSR0_SMR49 (0x8c4U) -#define SMMU_GNSR0_SMR50 (0x8c8U) -#define SMMU_GNSR0_SMR51 (0x8ccU) -#define SMMU_GNSR0_SMR52 (0x8d0U) -#define SMMU_GNSR0_SMR53 (0x8d4U) -#define SMMU_GNSR0_SMR54 (0x8d8U) -#define SMMU_GNSR0_SMR55 (0x8dcU) -#define SMMU_GNSR0_SMR56 (0x8e0U) -#define SMMU_GNSR0_SMR57 (0x8e4U) -#define SMMU_GNSR0_SMR58 (0x8e8U) -#define SMMU_GNSR0_SMR59 (0x8ecU) -#define SMMU_GNSR0_SMR60 (0x8f0U) -#define SMMU_GNSR0_SMR61 (0x8f4U) -#define SMMU_GNSR0_SMR62 (0x8f8U) -#define SMMU_GNSR0_SMR63 (0x8fcU) -#define SMMU_GNSR0_SMR64 (0x900U) -#define SMMU_GNSR0_SMR65 (0x904U) -#define SMMU_GNSR0_SMR66 (0x908U) -#define SMMU_GNSR0_SMR67 (0x90cU) -#define SMMU_GNSR0_SMR68 (0x910U) -#define SMMU_GNSR0_SMR69 (0x914U) -#define SMMU_GNSR0_SMR70 (0x918U) -#define SMMU_GNSR0_SMR71 (0x91cU) -#define SMMU_GNSR0_SMR72 (0x920U) -#define SMMU_GNSR0_SMR73 (0x924U) -#define SMMU_GNSR0_SMR74 (0x928U) -#define SMMU_GNSR0_SMR75 (0x92cU) -#define SMMU_GNSR0_SMR76 (0x930U) -#define SMMU_GNSR0_SMR77 (0x934U) -#define SMMU_GNSR0_SMR78 (0x938U) -#define SMMU_GNSR0_SMR79 (0x93cU) -#define SMMU_GNSR0_SMR80 (0x940U) -#define SMMU_GNSR0_SMR81 (0x944U) -#define SMMU_GNSR0_SMR82 (0x948U) -#define SMMU_GNSR0_SMR83 (0x94cU) -#define SMMU_GNSR0_SMR84 (0x950U) -#define SMMU_GNSR0_SMR85 (0x954U) -#define SMMU_GNSR0_SMR86 (0x958U) -#define SMMU_GNSR0_SMR87 (0x95cU) -#define SMMU_GNSR0_SMR88 (0x960U) -#define SMMU_GNSR0_SMR89 (0x964U) -#define SMMU_GNSR0_SMR90 (0x968U) -#define SMMU_GNSR0_SMR91 (0x96cU) -#define SMMU_GNSR0_SMR92 (0x970U) -#define SMMU_GNSR0_SMR93 (0x974U) -#define SMMU_GNSR0_SMR94 (0x978U) -#define SMMU_GNSR0_SMR95 (0x97cU) -#define SMMU_GNSR0_SMR96 (0x980U) -#define SMMU_GNSR0_SMR97 (0x984U) -#define SMMU_GNSR0_SMR98 (0x988U) -#define SMMU_GNSR0_SMR99 (0x98cU) -#define SMMU_GNSR0_SMR100 (0x990U) -#define SMMU_GNSR0_SMR101 (0x994U) -#define SMMU_GNSR0_SMR102 (0x998U) -#define SMMU_GNSR0_SMR103 (0x99cU) -#define SMMU_GNSR0_SMR104 (0x9a0U) -#define SMMU_GNSR0_SMR105 (0x9a4U) -#define SMMU_GNSR0_SMR106 (0x9a8U) -#define SMMU_GNSR0_SMR107 (0x9acU) -#define SMMU_GNSR0_SMR108 (0x9b0U) -#define SMMU_GNSR0_SMR109 (0x9b4U) -#define SMMU_GNSR0_SMR110 (0x9b8U) -#define SMMU_GNSR0_SMR111 (0x9bcU) -#define SMMU_GNSR0_SMR112 (0x9c0U) -#define SMMU_GNSR0_SMR113 (0x9c4U) -#define SMMU_GNSR0_SMR114 (0x9c8U) -#define SMMU_GNSR0_SMR115 (0x9ccU) -#define SMMU_GNSR0_SMR116 (0x9d0U) -#define SMMU_GNSR0_SMR117 (0x9d4U) -#define SMMU_GNSR0_SMR118 (0x9d8U) -#define SMMU_GNSR0_SMR119 (0x9dcU) -#define SMMU_GNSR0_SMR120 (0x9e0U) -#define SMMU_GNSR0_SMR121 (0x9e4U) -#define SMMU_GNSR0_SMR122 (0x9e8U) -#define SMMU_GNSR0_SMR123 (0x9ecU) -#define SMMU_GNSR0_SMR124 (0x9f0U) -#define SMMU_GNSR0_SMR125 (0x9f4U) -#define SMMU_GNSR0_SMR126 (0x9f8U) -#define SMMU_GNSR0_SMR127 (0x9fcU) -#define SMMU_GNSR0_S2CR0 (0xc00U) -#define SMMU_GNSR0_S2CRn (0xc00U) -#define SMMU_GNSR0_S2CRn (0xc00U) -#define SMMU_GNSR0_S2CR1 (0xc04U) -#define SMMU_GNSR0_S2CR2 (0xc08U) -#define SMMU_GNSR0_S2CR3 (0xc0cU) -#define SMMU_GNSR0_S2CR4 (0xc10U) -#define SMMU_GNSR0_S2CR5 (0xc14U) -#define SMMU_GNSR0_S2CR6 (0xc18U) -#define SMMU_GNSR0_S2CR7 (0xc1cU) -#define SMMU_GNSR0_S2CR8 (0xc20U) -#define SMMU_GNSR0_S2CR9 (0xc24U) -#define SMMU_GNSR0_S2CR10 (0xc28U) -#define SMMU_GNSR0_S2CR11 (0xc2cU) -#define SMMU_GNSR0_S2CR12 (0xc30U) -#define SMMU_GNSR0_S2CR13 (0xc34U) -#define SMMU_GNSR0_S2CR14 (0xc38U) -#define SMMU_GNSR0_S2CR15 (0xc3cU) -#define SMMU_GNSR0_S2CR16 (0xc40U) -#define SMMU_GNSR0_S2CR17 (0xc44U) -#define SMMU_GNSR0_S2CR18 (0xc48U) -#define SMMU_GNSR0_S2CR19 (0xc4cU) -#define SMMU_GNSR0_S2CR20 (0xc50U) -#define SMMU_GNSR0_S2CR21 (0xc54U) -#define SMMU_GNSR0_S2CR22 (0xc58U) -#define SMMU_GNSR0_S2CR23 (0xc5cU) -#define SMMU_GNSR0_S2CR24 (0xc60U) -#define SMMU_GNSR0_S2CR25 (0xc64U) -#define SMMU_GNSR0_S2CR26 (0xc68U) -#define SMMU_GNSR0_S2CR27 (0xc6cU) -#define SMMU_GNSR0_S2CR28 (0xc70U) -#define SMMU_GNSR0_S2CR29 (0xc74U) -#define SMMU_GNSR0_S2CR30 (0xc78U) -#define SMMU_GNSR0_S2CR31 (0xc7cU) -#define SMMU_GNSR0_S2CR32 (0xc80U) -#define SMMU_GNSR0_S2CR33 (0xc84U) -#define SMMU_GNSR0_S2CR34 (0xc88U) -#define SMMU_GNSR0_S2CR35 (0xc8cU) -#define SMMU_GNSR0_S2CR36 (0xc90U) -#define SMMU_GNSR0_S2CR37 (0xc94U) -#define SMMU_GNSR0_S2CR38 (0xc98U) -#define SMMU_GNSR0_S2CR39 (0xc9cU) -#define SMMU_GNSR0_S2CR40 (0xca0U) -#define SMMU_GNSR0_S2CR41 (0xca4U) -#define SMMU_GNSR0_S2CR42 (0xca8U) -#define SMMU_GNSR0_S2CR43 (0xcacU) -#define SMMU_GNSR0_S2CR44 (0xcb0U) -#define SMMU_GNSR0_S2CR45 (0xcb4U) -#define SMMU_GNSR0_S2CR46 (0xcb8U) -#define SMMU_GNSR0_S2CR47 (0xcbcU) -#define SMMU_GNSR0_S2CR48 (0xcc0U) -#define SMMU_GNSR0_S2CR49 (0xcc4U) -#define SMMU_GNSR0_S2CR50 (0xcc8U) -#define SMMU_GNSR0_S2CR51 (0xcccU) -#define SMMU_GNSR0_S2CR52 (0xcd0U) -#define SMMU_GNSR0_S2CR53 (0xcd4U) -#define SMMU_GNSR0_S2CR54 (0xcd8U) -#define SMMU_GNSR0_S2CR55 (0xcdcU) -#define SMMU_GNSR0_S2CR56 (0xce0U) -#define SMMU_GNSR0_S2CR57 (0xce4U) -#define SMMU_GNSR0_S2CR58 (0xce8U) -#define SMMU_GNSR0_S2CR59 (0xcecU) -#define SMMU_GNSR0_S2CR60 (0xcf0U) -#define SMMU_GNSR0_S2CR61 (0xcf4U) -#define SMMU_GNSR0_S2CR62 (0xcf8U) -#define SMMU_GNSR0_S2CR63 (0xcfcU) -#define SMMU_GNSR0_S2CR64 (0xd00U) -#define SMMU_GNSR0_S2CR65 (0xd04U) -#define SMMU_GNSR0_S2CR66 (0xd08U) -#define SMMU_GNSR0_S2CR67 (0xd0cU) -#define SMMU_GNSR0_S2CR68 (0xd10U) -#define SMMU_GNSR0_S2CR69 (0xd14U) -#define SMMU_GNSR0_S2CR70 (0xd18U) -#define SMMU_GNSR0_S2CR71 (0xd1cU) -#define SMMU_GNSR0_S2CR72 (0xd20U) -#define SMMU_GNSR0_S2CR73 (0xd24U) -#define SMMU_GNSR0_S2CR74 (0xd28U) -#define SMMU_GNSR0_S2CR75 (0xd2cU) -#define SMMU_GNSR0_S2CR76 (0xd30U) -#define SMMU_GNSR0_S2CR77 (0xd34U) -#define SMMU_GNSR0_S2CR78 (0xd38U) -#define SMMU_GNSR0_S2CR79 (0xd3cU) -#define SMMU_GNSR0_S2CR80 (0xd40U) -#define SMMU_GNSR0_S2CR81 (0xd44U) -#define SMMU_GNSR0_S2CR82 (0xd48U) -#define SMMU_GNSR0_S2CR83 (0xd4cU) -#define SMMU_GNSR0_S2CR84 (0xd50U) -#define SMMU_GNSR0_S2CR85 (0xd54U) -#define SMMU_GNSR0_S2CR86 (0xd58U) -#define SMMU_GNSR0_S2CR87 (0xd5cU) -#define SMMU_GNSR0_S2CR88 (0xd60U) -#define SMMU_GNSR0_S2CR89 (0xd64U) -#define SMMU_GNSR0_S2CR90 (0xd68U) -#define SMMU_GNSR0_S2CR91 (0xd6cU) -#define SMMU_GNSR0_S2CR92 (0xd70U) -#define SMMU_GNSR0_S2CR93 (0xd74U) -#define SMMU_GNSR0_S2CR94 (0xd78U) -#define SMMU_GNSR0_S2CR95 (0xd7cU) -#define SMMU_GNSR0_S2CR96 (0xd80U) -#define SMMU_GNSR0_S2CR97 (0xd84U) -#define SMMU_GNSR0_S2CR98 (0xd88U) -#define SMMU_GNSR0_S2CR99 (0xd8cU) -#define SMMU_GNSR0_S2CR100 (0xd90U) -#define SMMU_GNSR0_S2CR101 (0xd94U) -#define SMMU_GNSR0_S2CR102 (0xd98U) -#define SMMU_GNSR0_S2CR103 (0xd9cU) -#define SMMU_GNSR0_S2CR104 (0xda0U) -#define SMMU_GNSR0_S2CR105 (0xda4U) -#define SMMU_GNSR0_S2CR106 (0xda8U) -#define SMMU_GNSR0_S2CR107 (0xdacU) -#define SMMU_GNSR0_S2CR108 (0xdb0U) -#define SMMU_GNSR0_S2CR109 (0xdb4U) -#define SMMU_GNSR0_S2CR110 (0xdb8U) -#define SMMU_GNSR0_S2CR111 (0xdbcU) -#define SMMU_GNSR0_S2CR112 (0xdc0U) -#define SMMU_GNSR0_S2CR113 (0xdc4U) -#define SMMU_GNSR0_S2CR114 (0xdc8U) -#define SMMU_GNSR0_S2CR115 (0xdccU) -#define SMMU_GNSR0_S2CR116 (0xdd0U) -#define SMMU_GNSR0_S2CR117 (0xdd4U) -#define SMMU_GNSR0_S2CR118 (0xdd8U) -#define SMMU_GNSR0_S2CR119 (0xddcU) -#define SMMU_GNSR0_S2CR120 (0xde0U) -#define SMMU_GNSR0_S2CR121 (0xde4U) -#define SMMU_GNSR0_S2CR122 (0xde8U) -#define SMMU_GNSR0_S2CR123 (0xdecU) -#define SMMU_GNSR0_S2CR124 (0xdf0U) -#define SMMU_GNSR0_S2CR125 (0xdf4U) -#define SMMU_GNSR0_S2CR126 (0xdf8U) -#define SMMU_GNSR0_S2CR127 (0xdfcU) -#define SMMU_GNSR0_PIDR0 (0xfe0U) -#define SMMU_GNSR0_PIDR1 (0xfe4U) -#define SMMU_GNSR0_PIDR2 (0xfe8U) -#define SMMU_GNSR0_PIDR3 (0xfecU) -#define SMMU_GNSR0_PIDR4 (0xfd0U) -#define SMMU_GNSR0_PIDR5 (0xfd4U) -#define SMMU_GNSR0_PIDR6 (0xfd8U) -#define SMMU_GNSR0_PIDR7 (0xfdcU) -#define SMMU_GNSR0_CIDR0 (0xff0U) -#define SMMU_GNSR0_CIDR1 (0xff4U) -#define SMMU_GNSR0_CIDR2 (0xff8U) -#define SMMU_GNSR0_CIDR3 (0xffcU) -#define SMMU_GNSR1_CBAR0 (0x0U) -#define SMMU_GNSR1_CBARn (0x0U) -#define SMMU_GNSR1_CBFRSYNRA0 (0x400U) -#define SMMU_GNSR1_CBA2R0 (0x800U) -#define SMMU_GNSR1_CBAR1 (0x4U) -#define SMMU_GNSR1_CBFRSYNRA1 (0x404U) -#define SMMU_GNSR1_CBA2R1 (0x804U) -#define SMMU_GNSR1_CBAR2 (0x8U) -#define SMMU_GNSR1_CBFRSYNRA2 (0x408U) -#define SMMU_GNSR1_CBA2R2 (0x808U) -#define SMMU_GNSR1_CBAR3 (0xcU) -#define SMMU_GNSR1_CBFRSYNRA3 (0x40cU) -#define SMMU_GNSR1_CBA2R3 (0x80cU) -#define SMMU_GNSR1_CBAR4 (0x10U) -#define SMMU_GNSR1_CBFRSYNRA4 (0x410U) -#define SMMU_GNSR1_CBA2R4 (0x810U) -#define SMMU_GNSR1_CBAR5 (0x14U) -#define SMMU_GNSR1_CBFRSYNRA5 (0x414U) -#define SMMU_GNSR1_CBA2R5 (0x814U) -#define SMMU_GNSR1_CBAR6 (0x18U) -#define SMMU_GNSR1_CBFRSYNRA6 (0x418U) -#define SMMU_GNSR1_CBA2R6 (0x818U) -#define SMMU_GNSR1_CBAR7 (0x1cU) -#define SMMU_GNSR1_CBFRSYNRA7 (0x41cU) -#define SMMU_GNSR1_CBA2R7 (0x81cU) -#define SMMU_GNSR1_CBAR8 (0x20U) -#define SMMU_GNSR1_CBFRSYNRA8 (0x420U) -#define SMMU_GNSR1_CBA2R8 (0x820U) -#define SMMU_GNSR1_CBAR9 (0x24U) -#define SMMU_GNSR1_CBFRSYNRA9 (0x424U) -#define SMMU_GNSR1_CBA2R9 (0x824U) -#define SMMU_GNSR1_CBAR10 (0x28U) -#define SMMU_GNSR1_CBFRSYNRA10 (0x428U) -#define SMMU_GNSR1_CBA2R10 (0x828U) -#define SMMU_GNSR1_CBAR11 (0x2cU) -#define SMMU_GNSR1_CBFRSYNRA11 (0x42cU) -#define SMMU_GNSR1_CBA2R11 (0x82cU) -#define SMMU_GNSR1_CBAR12 (0x30U) -#define SMMU_GNSR1_CBFRSYNRA12 (0x430U) -#define SMMU_GNSR1_CBA2R12 (0x830U) -#define SMMU_GNSR1_CBAR13 (0x34U) -#define SMMU_GNSR1_CBFRSYNRA13 (0x434U) -#define SMMU_GNSR1_CBA2R13 (0x834U) -#define SMMU_GNSR1_CBAR14 (0x38U) -#define SMMU_GNSR1_CBFRSYNRA14 (0x438U) -#define SMMU_GNSR1_CBA2R14 (0x838U) -#define SMMU_GNSR1_CBAR15 (0x3cU) -#define SMMU_GNSR1_CBFRSYNRA15 (0x43cU) -#define SMMU_GNSR1_CBA2R15 (0x83cU) -#define SMMU_GNSR1_CBAR16 (0x40U) -#define SMMU_GNSR1_CBFRSYNRA16 (0x440U) -#define SMMU_GNSR1_CBA2R16 (0x840U) -#define SMMU_GNSR1_CBAR17 (0x44U) -#define SMMU_GNSR1_CBFRSYNRA17 (0x444U) -#define SMMU_GNSR1_CBA2R17 (0x844U) -#define SMMU_GNSR1_CBAR18 (0x48U) -#define SMMU_GNSR1_CBFRSYNRA18 (0x448U) -#define SMMU_GNSR1_CBA2R18 (0x848U) -#define SMMU_GNSR1_CBAR19 (0x4cU) -#define SMMU_GNSR1_CBFRSYNRA19 (0x44cU) -#define SMMU_GNSR1_CBA2R19 (0x84cU) -#define SMMU_GNSR1_CBAR20 (0x50U) -#define SMMU_GNSR1_CBFRSYNRA20 (0x450U) -#define SMMU_GNSR1_CBA2R20 (0x850U) -#define SMMU_GNSR1_CBAR21 (0x54U) -#define SMMU_GNSR1_CBFRSYNRA21 (0x454U) -#define SMMU_GNSR1_CBA2R21 (0x854U) -#define SMMU_GNSR1_CBAR22 (0x58U) -#define SMMU_GNSR1_CBFRSYNRA22 (0x458U) -#define SMMU_GNSR1_CBA2R22 (0x858U) -#define SMMU_GNSR1_CBAR23 (0x5cU) -#define SMMU_GNSR1_CBFRSYNRA23 (0x45cU) -#define SMMU_GNSR1_CBA2R23 (0x85cU) -#define SMMU_GNSR1_CBAR24 (0x60U) -#define SMMU_GNSR1_CBFRSYNRA24 (0x460U) -#define SMMU_GNSR1_CBA2R24 (0x860U) -#define SMMU_GNSR1_CBAR25 (0x64U) -#define SMMU_GNSR1_CBFRSYNRA25 (0x464U) -#define SMMU_GNSR1_CBA2R25 (0x864U) -#define SMMU_GNSR1_CBAR26 (0x68U) -#define SMMU_GNSR1_CBFRSYNRA26 (0x468U) -#define SMMU_GNSR1_CBA2R26 (0x868U) -#define SMMU_GNSR1_CBAR27 (0x6cU) -#define SMMU_GNSR1_CBFRSYNRA27 (0x46cU) -#define SMMU_GNSR1_CBA2R27 (0x86cU) -#define SMMU_GNSR1_CBAR28 (0x70U) -#define SMMU_GNSR1_CBFRSYNRA28 (0x470U) -#define SMMU_GNSR1_CBA2R28 (0x870U) -#define SMMU_GNSR1_CBAR29 (0x74U) -#define SMMU_GNSR1_CBFRSYNRA29 (0x474U) -#define SMMU_GNSR1_CBA2R29 (0x874U) -#define SMMU_GNSR1_CBAR30 (0x78U) -#define SMMU_GNSR1_CBFRSYNRA30 (0x478U) -#define SMMU_GNSR1_CBA2R30 (0x878U) -#define SMMU_GNSR1_CBAR31 (0x7cU) -#define SMMU_GNSR1_CBFRSYNRA31 (0x47cU) -#define SMMU_GNSR1_CBA2R31 (0x87cU) -#define SMMU_GNSR1_CBAR32 (0x80U) -#define SMMU_GNSR1_CBFRSYNRA32 (0x480U) -#define SMMU_GNSR1_CBA2R32 (0x880U) -#define SMMU_GNSR1_CBAR33 (0x84U) -#define SMMU_GNSR1_CBFRSYNRA33 (0x484U) -#define SMMU_GNSR1_CBA2R33 (0x884U) -#define SMMU_GNSR1_CBAR34 (0x88U) -#define SMMU_GNSR1_CBFRSYNRA34 (0x488U) -#define SMMU_GNSR1_CBA2R34 (0x888U) -#define SMMU_GNSR1_CBAR35 (0x8cU) -#define SMMU_GNSR1_CBFRSYNRA35 (0x48cU) -#define SMMU_GNSR1_CBA2R35 (0x88cU) -#define SMMU_GNSR1_CBAR36 (0x90U) -#define SMMU_GNSR1_CBFRSYNRA36 (0x490U) -#define SMMU_GNSR1_CBA2R36 (0x890U) -#define SMMU_GNSR1_CBAR37 (0x94U) -#define SMMU_GNSR1_CBFRSYNRA37 (0x494U) -#define SMMU_GNSR1_CBA2R37 (0x894U) -#define SMMU_GNSR1_CBAR38 (0x98U) -#define SMMU_GNSR1_CBFRSYNRA38 (0x498U) -#define SMMU_GNSR1_CBA2R38 (0x898U) -#define SMMU_GNSR1_CBAR39 (0x9cU) -#define SMMU_GNSR1_CBFRSYNRA39 (0x49cU) -#define SMMU_GNSR1_CBA2R39 (0x89cU) -#define SMMU_GNSR1_CBAR40 (0xa0U) -#define SMMU_GNSR1_CBFRSYNRA40 (0x4a0U) -#define SMMU_GNSR1_CBA2R40 (0x8a0U) -#define SMMU_GNSR1_CBAR41 (0xa4U) -#define SMMU_GNSR1_CBFRSYNRA41 (0x4a4U) -#define SMMU_GNSR1_CBA2R41 (0x8a4U) -#define SMMU_GNSR1_CBAR42 (0xa8U) -#define SMMU_GNSR1_CBFRSYNRA42 (0x4a8U) -#define SMMU_GNSR1_CBA2R42 (0x8a8U) -#define SMMU_GNSR1_CBAR43 (0xacU) -#define SMMU_GNSR1_CBFRSYNRA43 (0x4acU) -#define SMMU_GNSR1_CBA2R43 (0x8acU) -#define SMMU_GNSR1_CBAR44 (0xb0U) -#define SMMU_GNSR1_CBFRSYNRA44 (0x4b0U) -#define SMMU_GNSR1_CBA2R44 (0x8b0U) -#define SMMU_GNSR1_CBAR45 (0xb4U) -#define SMMU_GNSR1_CBFRSYNRA45 (0x4b4U) -#define SMMU_GNSR1_CBA2R45 (0x8b4U) -#define SMMU_GNSR1_CBAR46 (0xb8U) -#define SMMU_GNSR1_CBFRSYNRA46 (0x4b8U) -#define SMMU_GNSR1_CBA2R46 (0x8b8U) -#define SMMU_GNSR1_CBAR47 (0xbcU) -#define SMMU_GNSR1_CBFRSYNRA47 (0x4bcU) -#define SMMU_GNSR1_CBA2R47 (0x8bcU) -#define SMMU_GNSR1_CBAR48 (0xc0U) -#define SMMU_GNSR1_CBFRSYNRA48 (0x4c0U) -#define SMMU_GNSR1_CBA2R48 (0x8c0U) -#define SMMU_GNSR1_CBAR49 (0xc4U) -#define SMMU_GNSR1_CBFRSYNRA49 (0x4c4U) -#define SMMU_GNSR1_CBA2R49 (0x8c4U) -#define SMMU_GNSR1_CBAR50 (0xc8U) -#define SMMU_GNSR1_CBFRSYNRA50 (0x4c8U) -#define SMMU_GNSR1_CBA2R50 (0x8c8U) -#define SMMU_GNSR1_CBAR51 (0xccU) -#define SMMU_GNSR1_CBFRSYNRA51 (0x4ccU) -#define SMMU_GNSR1_CBA2R51 (0x8ccU) -#define SMMU_GNSR1_CBAR52 (0xd0U) -#define SMMU_GNSR1_CBFRSYNRA52 (0x4d0U) -#define SMMU_GNSR1_CBA2R52 (0x8d0U) -#define SMMU_GNSR1_CBAR53 (0xd4U) -#define SMMU_GNSR1_CBFRSYNRA53 (0x4d4U) -#define SMMU_GNSR1_CBA2R53 (0x8d4U) -#define SMMU_GNSR1_CBAR54 (0xd8U) -#define SMMU_GNSR1_CBFRSYNRA54 (0x4d8U) -#define SMMU_GNSR1_CBA2R54 (0x8d8U) -#define SMMU_GNSR1_CBAR55 (0xdcU) -#define SMMU_GNSR1_CBFRSYNRA55 (0x4dcU) -#define SMMU_GNSR1_CBA2R55 (0x8dcU) -#define SMMU_GNSR1_CBAR56 (0xe0U) -#define SMMU_GNSR1_CBFRSYNRA56 (0x4e0U) -#define SMMU_GNSR1_CBA2R56 (0x8e0U) -#define SMMU_GNSR1_CBAR57 (0xe4U) -#define SMMU_GNSR1_CBFRSYNRA57 (0x4e4U) -#define SMMU_GNSR1_CBA2R57 (0x8e4U) -#define SMMU_GNSR1_CBAR58 (0xe8U) -#define SMMU_GNSR1_CBFRSYNRA58 (0x4e8U) -#define SMMU_GNSR1_CBA2R58 (0x8e8U) -#define SMMU_GNSR1_CBAR59 (0xecU) -#define SMMU_GNSR1_CBFRSYNRA59 (0x4ecU) -#define SMMU_GNSR1_CBA2R59 (0x8ecU) -#define SMMU_GNSR1_CBAR60 (0xf0U) -#define SMMU_GNSR1_CBFRSYNRA60 (0x4f0U) -#define SMMU_GNSR1_CBA2R60 (0x8f0U) -#define SMMU_GNSR1_CBAR61 (0xf4U) -#define SMMU_GNSR1_CBFRSYNRA61 (0x4f4U) -#define SMMU_GNSR1_CBA2R61 (0x8f4U) -#define SMMU_GNSR1_CBAR62 (0xf8U) -#define SMMU_GNSR1_CBFRSYNRA62 (0x4f8U) -#define SMMU_GNSR1_CBA2R62 (0x8f8U) -#define SMMU_GNSR1_CBAR63 (0xfcU) -#define SMMU_GNSR1_CBFRSYNRA63 (0x4fcU) -#define SMMU_GNSR1_CBA2R63 (0x8fcU) /******************************************************************************* * SMMU Global Secure Aux. Configuration Register @@ -581,269 +23,70 @@ #define SMMU_GSR0_PGSIZE_SHIFT 16U #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) -#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26) +#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) +#define SMMU_GSR0_PER (0x20200U) /******************************************************************************* * SMMU Global Aux. Control Register ******************************************************************************/ #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) -/******************************************************************************* - * SMMU configuration constants - ******************************************************************************/ -#define ID1_PAGESIZE (1U << 31U) -#define ID1_NUMPAGENDXB_SHIFT 28U -#define ID1_NUMPAGENDXB_MASK 7U -#define ID1_NUMS2CB_SHIFT 16U -#define ID1_NUMS2CB_MASK 0xffU -#define ID1_NUMCB_SHIFT 0U -#define ID1_NUMCB_MASK 0xffU -#define PGSHIFT 16U -#define CB_SIZE 0x800000U +/* SMMU IDs currently supported by the driver */ +enum { + TEGRA_SMMU0 = 0U, + TEGRA_SMMU1 = 1U, + TEGRA_SMMU2 = 2U +}; -typedef struct smmu_regs { - uint32_t reg; - uint32_t val; -} smmu_regs_t; +static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) +{ + uint32_t ret = 0U; -#define mc_make_sid_override_cfg(name) \ - { \ - .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \ - .val = 0x00000000U, \ +#if defined(TEGRA_SMMU0_BASE) + if (smmu_id == TEGRA_SMMU0) { + ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off); } +#endif -#define mc_make_sid_security_cfg(name) \ - { \ - .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \ - .val = 0x00000000U, \ +#if defined(TEGRA_SMMU1_BASE) + if (smmu_id == TEGRA_SMMU1) { + ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off); } +#endif -#define smmu_make_gnsr0_sec_cfg(base_addr, name) \ - { \ - .reg = base_addr + SMMU_GNSR0_ ## name, \ - .val = 0x00000000U, \ +#if defined(TEGRA_SMMU2_BASE) + if (smmu_id == TEGRA_SMMU2) { + ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off); } +#endif -/* - * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers - * is 0x400. So, add it to register address - */ -#define smmu_make_gnsr0_nsec_cfg(base_addr, name) \ - { \ - .reg = base_addr + 0x400U + SMMU_GNSR0_ ## name, \ - .val = 0x00000000U, \ - } - -#define smmu_make_gnsr0_smr_cfg(base_addr, n) \ - { \ - .reg = base_addr + SMMU_GNSR0_SMR ## n, \ - .val = 0x00000000U, \ - } - -#define smmu_make_gnsr0_s2cr_cfg(base_addr, n) \ - { \ - .reg = base_addr + SMMU_GNSR0_S2CR ## n, \ - .val = 0x00000000U, \ - } + return ret; +} -#define smmu_make_gnsr1_cbar_cfg(base_addr, n) \ - { \ - .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \ - .val = 0x00000000U, \ +static inline void tegra_smmu_write_32(uint32_t smmu_id, + uint32_t off, uint32_t val) +{ +#if defined(TEGRA_SMMU0_BASE) + if (smmu_id == TEGRA_SMMU0) { + mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val); } +#endif -#define smmu_make_gnsr1_cba2r_cfg(base_addr, n) \ - { \ - .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \ - .val = 0x00000000U, \ +#if defined(TEGRA_SMMU1_BASE) + if (smmu_id == TEGRA_SMMU1) { + mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val); } +#endif -#define smmu_make_cb_cfg(base_addr, name, n) \ - { \ - .reg = base_addr + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \ - + SMMU_CBn_ ## name, \ - .val = 0x00000000U, \ +#if defined(TEGRA_SMMU2_BASE) + if (smmu_id == TEGRA_SMMU2) { + mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val); } - -#define smmu_make_smrg_group(base_addr, n) \ - smmu_make_gnsr0_smr_cfg(base_addr, n), \ - smmu_make_gnsr0_s2cr_cfg(base_addr, n), \ - smmu_make_gnsr1_cbar_cfg(base_addr, n), \ - smmu_make_gnsr1_cba2r_cfg(base_addr, n) /* don't put "," here. */ - -#define smmu_make_cb_group(base_addr, n) \ - smmu_make_cb_cfg(base_addr, SCTLR, n), \ - smmu_make_cb_cfg(base_addr, TCR2, n), \ - smmu_make_cb_cfg(base_addr, TTBR0_LO, n), \ - smmu_make_cb_cfg(base_addr, TTBR0_HI, n), \ - smmu_make_cb_cfg(base_addr, TCR, n), \ - smmu_make_cb_cfg(base_addr, PRRR_MAIR0, n),\ - smmu_make_cb_cfg(base_addr, FSR, n), \ - smmu_make_cb_cfg(base_addr, FAR_LO, n), \ - smmu_make_cb_cfg(base_addr, FAR_HI, n), \ - smmu_make_cb_cfg(base_addr, FSYNR0, n) /* don't put "," here. */ - -#define smmu_make_cfg(base_addr) \ - smmu_make_gnsr0_nsec_cfg(base_addr, CR0), \ - smmu_make_gnsr0_sec_cfg(base_addr, IDR0), \ - smmu_make_gnsr0_sec_cfg(base_addr, IDR1), \ - smmu_make_gnsr0_sec_cfg(base_addr, IDR2), \ - smmu_make_gnsr0_nsec_cfg(base_addr, GFSR), \ - smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR0), \ - smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR1), \ - smmu_make_gnsr0_nsec_cfg(base_addr, TLBGSTATUS),\ - smmu_make_gnsr0_nsec_cfg(base_addr, PIDR2), \ - smmu_make_smrg_group(base_addr, 0), \ - smmu_make_smrg_group(base_addr, 1), \ - smmu_make_smrg_group(base_addr, 2), \ - smmu_make_smrg_group(base_addr, 3), \ - smmu_make_smrg_group(base_addr, 4), \ - smmu_make_smrg_group(base_addr, 5), \ - smmu_make_smrg_group(base_addr, 6), \ - smmu_make_smrg_group(base_addr, 7), \ - smmu_make_smrg_group(base_addr, 8), \ - smmu_make_smrg_group(base_addr, 9), \ - smmu_make_smrg_group(base_addr, 10), \ - smmu_make_smrg_group(base_addr, 11), \ - smmu_make_smrg_group(base_addr, 12), \ - smmu_make_smrg_group(base_addr, 13), \ - smmu_make_smrg_group(base_addr, 14), \ - smmu_make_smrg_group(base_addr, 15), \ - smmu_make_smrg_group(base_addr, 16), \ - smmu_make_smrg_group(base_addr, 17), \ - smmu_make_smrg_group(base_addr, 18), \ - smmu_make_smrg_group(base_addr, 19), \ - smmu_make_smrg_group(base_addr, 20), \ - smmu_make_smrg_group(base_addr, 21), \ - smmu_make_smrg_group(base_addr, 22), \ - smmu_make_smrg_group(base_addr, 23), \ - smmu_make_smrg_group(base_addr, 24), \ - smmu_make_smrg_group(base_addr, 25), \ - smmu_make_smrg_group(base_addr, 26), \ - smmu_make_smrg_group(base_addr, 27), \ - smmu_make_smrg_group(base_addr, 28), \ - smmu_make_smrg_group(base_addr, 29), \ - smmu_make_smrg_group(base_addr, 30), \ - smmu_make_smrg_group(base_addr, 31), \ - smmu_make_smrg_group(base_addr, 32), \ - smmu_make_smrg_group(base_addr, 33), \ - smmu_make_smrg_group(base_addr, 34), \ - smmu_make_smrg_group(base_addr, 35), \ - smmu_make_smrg_group(base_addr, 36), \ - smmu_make_smrg_group(base_addr, 37), \ - smmu_make_smrg_group(base_addr, 38), \ - smmu_make_smrg_group(base_addr, 39), \ - smmu_make_smrg_group(base_addr, 40), \ - smmu_make_smrg_group(base_addr, 41), \ - smmu_make_smrg_group(base_addr, 42), \ - smmu_make_smrg_group(base_addr, 43), \ - smmu_make_smrg_group(base_addr, 44), \ - smmu_make_smrg_group(base_addr, 45), \ - smmu_make_smrg_group(base_addr, 46), \ - smmu_make_smrg_group(base_addr, 47), \ - smmu_make_smrg_group(base_addr, 48), \ - smmu_make_smrg_group(base_addr, 49), \ - smmu_make_smrg_group(base_addr, 50), \ - smmu_make_smrg_group(base_addr, 51), \ - smmu_make_smrg_group(base_addr, 52), \ - smmu_make_smrg_group(base_addr, 53), \ - smmu_make_smrg_group(base_addr, 54), \ - smmu_make_smrg_group(base_addr, 55), \ - smmu_make_smrg_group(base_addr, 56), \ - smmu_make_smrg_group(base_addr, 57), \ - smmu_make_smrg_group(base_addr, 58), \ - smmu_make_smrg_group(base_addr, 59), \ - smmu_make_smrg_group(base_addr, 60), \ - smmu_make_smrg_group(base_addr, 61), \ - smmu_make_smrg_group(base_addr, 62), \ - smmu_make_smrg_group(base_addr, 63), \ - smmu_make_cb_group(base_addr, 0), \ - smmu_make_cb_group(base_addr, 1), \ - smmu_make_cb_group(base_addr, 2), \ - smmu_make_cb_group(base_addr, 3), \ - smmu_make_cb_group(base_addr, 4), \ - smmu_make_cb_group(base_addr, 5), \ - smmu_make_cb_group(base_addr, 6), \ - smmu_make_cb_group(base_addr, 7), \ - smmu_make_cb_group(base_addr, 8), \ - smmu_make_cb_group(base_addr, 9), \ - smmu_make_cb_group(base_addr, 10), \ - smmu_make_cb_group(base_addr, 11), \ - smmu_make_cb_group(base_addr, 12), \ - smmu_make_cb_group(base_addr, 13), \ - smmu_make_cb_group(base_addr, 14), \ - smmu_make_cb_group(base_addr, 15), \ - smmu_make_cb_group(base_addr, 16), \ - smmu_make_cb_group(base_addr, 17), \ - smmu_make_cb_group(base_addr, 18), \ - smmu_make_cb_group(base_addr, 19), \ - smmu_make_cb_group(base_addr, 20), \ - smmu_make_cb_group(base_addr, 21), \ - smmu_make_cb_group(base_addr, 22), \ - smmu_make_cb_group(base_addr, 23), \ - smmu_make_cb_group(base_addr, 24), \ - smmu_make_cb_group(base_addr, 25), \ - smmu_make_cb_group(base_addr, 26), \ - smmu_make_cb_group(base_addr, 27), \ - smmu_make_cb_group(base_addr, 28), \ - smmu_make_cb_group(base_addr, 29), \ - smmu_make_cb_group(base_addr, 30), \ - smmu_make_cb_group(base_addr, 31), \ - smmu_make_cb_group(base_addr, 32), \ - smmu_make_cb_group(base_addr, 33), \ - smmu_make_cb_group(base_addr, 34), \ - smmu_make_cb_group(base_addr, 35), \ - smmu_make_cb_group(base_addr, 36), \ - smmu_make_cb_group(base_addr, 37), \ - smmu_make_cb_group(base_addr, 38), \ - smmu_make_cb_group(base_addr, 39), \ - smmu_make_cb_group(base_addr, 40), \ - smmu_make_cb_group(base_addr, 41), \ - smmu_make_cb_group(base_addr, 42), \ - smmu_make_cb_group(base_addr, 43), \ - smmu_make_cb_group(base_addr, 44), \ - smmu_make_cb_group(base_addr, 45), \ - smmu_make_cb_group(base_addr, 46), \ - smmu_make_cb_group(base_addr, 47), \ - smmu_make_cb_group(base_addr, 48), \ - smmu_make_cb_group(base_addr, 49), \ - smmu_make_cb_group(base_addr, 50), \ - smmu_make_cb_group(base_addr, 51), \ - smmu_make_cb_group(base_addr, 52), \ - smmu_make_cb_group(base_addr, 53), \ - smmu_make_cb_group(base_addr, 54), \ - smmu_make_cb_group(base_addr, 55), \ - smmu_make_cb_group(base_addr, 56), \ - smmu_make_cb_group(base_addr, 57), \ - smmu_make_cb_group(base_addr, 58), \ - smmu_make_cb_group(base_addr, 59), \ - smmu_make_cb_group(base_addr, 60), \ - smmu_make_cb_group(base_addr, 61), \ - smmu_make_cb_group(base_addr, 62), \ - smmu_make_cb_group(base_addr, 63) /* don't put "," here. */ - -#define smmu_bypass_cfg \ - { \ - .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ - .val = 0x00000000U, \ - } - -#define _START_OF_TABLE_ \ - { \ - .reg = 0xCAFE05C7U, \ - .val = 0x00000000U, \ - } - -#define _END_OF_TABLE_ \ - { \ - .reg = 0xFFFFFFFFU, \ - .val = 0xFFFFFFFFU, \ - } - +#endif +} void tegra_smmu_init(void); -void tegra_smmu_save_context(uint64_t smmu_ctx_addr); -smmu_regs_t *plat_get_smmu_ctx(void); +void tegra_smmu_verify(void); uint32_t plat_get_num_smmu_devices(void); #endif /* SMMU_H */ diff --git a/plat/nvidia/tegra/include/drivers/spe.h b/plat/nvidia/tegra/include/drivers/spe.h index 0d6d69d10..e0f871408 100644 --- a/plat/nvidia/tegra/include/drivers/spe.h +++ b/plat/nvidia/tegra/include/drivers/spe.h @@ -11,11 +11,6 @@ #include <drivers/console.h> -typedef struct { - console_t console; - uintptr_t base; -} console_spe_t; - /* * Initialize a new spe console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -23,6 +18,6 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_spe_t *console); + console_t *console); #endif /* SPE_H */ diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S index 4f01e3306..2dc3b4152 100644 --- a/plat/nvidia/tegra/include/plat_macros.S +++ b/plat/nvidia/tegra/include/plat_macros.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,6 +28,7 @@ spacer: * --------------------------------------------- */ .macro plat_crash_print_regs +#ifdef TEGRA_GICC_BASE mov_imm x16, TEGRA_GICC_BASE /* gicc base address is now in x16 */ @@ -37,7 +39,7 @@ spacer: ldr w10, [x16, #GICC_CTLR] /* Store to the crash buf and print to cosole */ bl str_in_crash_buf_print - +#endif /* Print the GICD_ISPENDR regs */ mov_imm x16, TEGRA_GICD_BASE add x7, x16, #GICD_ISPENDR diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index eb55def4a..84b3297e0 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +13,19 @@ #include <tegra_def.h> +/******************************************************************************* + * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 + ******************************************************************************/ +#if !SEPARATE_CODE_AND_RODATA +#error "SEPARATE_CODE_AND_RODATA should be set to 1" +#endif + +/* + * Platform binary types for linking + */ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + /* * Platform binary types for linking */ @@ -33,7 +47,7 @@ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) /******************************************************************************* * Platform console related constants @@ -52,7 +66,6 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#define BL31_SIZE U(0x40000) #define BL31_BASE TZDRAM_BASE #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) @@ -72,4 +85,48 @@ #define MAX_IO_DEVICES U(0) #define MAX_IO_HANDLES U(0) +/******************************************************************************* + * Platforms macros to support SDEI + ******************************************************************************/ +#define TEGRA_SDEI_SGI_PRIVATE U(8) + +/******************************************************************************* + * Platform macros to support exception handling framework + ******************************************************************************/ +#define PLAT_PRI_BITS U(3) +#define PLAT_RAS_PRI U(0x10) +#define PLAT_SDEI_CRITICAL_PRI U(0x20) +#define PLAT_SDEI_NORMAL_PRI U(0x30) +#define PLAT_TEGRA_WDT_PRIO U(0x40) + +#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS,\ + PLAT_TEGRA_WDT_PRIO) + +/******************************************************************************* + * SDEI events + ******************************************************************************/ +/* SDEI dynamic private event numbers */ +#define TEGRA_SDEI_DP_EVENT_0 U(100) +#define TEGRA_SDEI_DP_EVENT_1 U(101) +#define TEGRA_SDEI_DP_EVENT_2 U(102) + +/* SDEI dynamic shared event numbers */ +#define TEGRA_SDEI_DS_EVENT_0 U(200) +#define TEGRA_SDEI_DS_EVENT_1 U(201) +#define TEGRA_SDEI_DS_EVENT_2 U(202) + +/* SDEI explicit events */ +#define TEGRA_SDEI_EP_EVENT_0 U(300) +#define TEGRA_SDEI_EP_EVENT_1 U(301) +#define TEGRA_SDEI_EP_EVENT_2 U(302) +#define TEGRA_SDEI_EP_EVENT_3 U(303) +#define TEGRA_SDEI_EP_EVENT_4 U(304) +#define TEGRA_SDEI_EP_EVENT_5 U(305) +#define TEGRA_SDEI_EP_EVENT_6 U(306) +#define TEGRA_SDEI_EP_EVENT_7 U(307) +#define TEGRA_SDEI_EP_EVENT_8 U(308) +#define TEGRA_SDEI_EP_EVENT_9 U(309) +#define TEGRA_SDEI_EP_EVENT_10 U(310) +#define TEGRA_SDEI_EP_EVENT_11 U(311) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index dfed2aa60..6b87655e3 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +11,11 @@ #include <lib/utils_def.h> /******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + +/******************************************************************************* * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` * call as the `state-id` field in the 'power state' parameter. ******************************************************************************/ @@ -103,6 +109,8 @@ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) +#define MC_VIDEO_PROTECT_REG_CTRL U(0x650) +#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) /******************************************************************************* * Tegra TZRAM constants @@ -110,4 +118,10 @@ #define TEGRA_TZRAM_BASE U(0x7C010000) #define TEGRA_TZRAM_SIZE U(0x10000) +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE ULL(0x80000000) +#define TEGRA_DRAM_END ULL(0x27FFFFFFF) + #endif /* TEGRA_DEF_H */ diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h index 9e2c02b4b..4514e1477 100644 --- a/plat/nvidia/tegra/include/t186/tegra186_private.h +++ b/plat/nvidia/tegra/include/t186/tegra186_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,6 @@ #ifndef TEGRA186_PRIVATE_H #define TEGRA186_PRIVATE_H -void tegra186_cpu_reset_handler(void); -uint64_t tegra186_get_cpu_reset_handler_base(void); -uint64_t tegra186_get_cpu_reset_handler_size(void); -uint64_t tegra186_get_smmu_ctx_offset(void); -void tegra186_set_system_suspend_entry(void); +uint64_t tegra186_get_mc_ctx_size(void); #endif /* TEGRA186_PRIVATE_H */ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index da050a895..a971cec93 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +11,11 @@ #include <lib/utils_def.h> /******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + +/******************************************************************************* * MCE apertures used by the ARI interface * * Aperture 0 - Cpu0 (ARM Cortex A-57) @@ -72,6 +78,12 @@ #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ /******************************************************************************* + * Clock identifier for the SE device + ******************************************************************************/ +#define TEGRA186_CLK_SE U(103) +#define TEGRA_CLK_SE TEGRA186_CLK_SE + +/******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) @@ -156,6 +168,8 @@ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) +#define MC_VIDEO_PROTECT_REG_CTRL U(0x650) +#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) /* * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the @@ -212,6 +226,14 @@ #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* + * Tegra HSP doorbell #0 constants + ******************************************************************************/ +#define TEGRA_HSP_DBELL_BASE U(0x03C90000) +#define HSP_DBELL_1_ENABLE U(0x104) +#define HSP_DBELL_3_TRIGGER U(0x300) +#define HSP_DBELL_3_ENABLE U(0x304) + +/******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x05000000) @@ -237,6 +259,7 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV0_HI U(0x654) #define SECURE_SCRATCH_RSV1_LO U(0x658) #define SECURE_SCRATCH_RSV1_HI U(0x65C) #define SECURE_SCRATCH_RSV6 U(0x680) @@ -246,12 +269,21 @@ #define SECURE_SCRATCH_RSV53_HI U(0x7FC) #define SECURE_SCRATCH_RSV55_LO U(0x808) #define SECURE_SCRATCH_RSV55_HI U(0x80C) +#define SECURE_SCRATCH_RSV63_LO U(0x848) +#define SECURE_SCRATCH_RSV63_HI U(0x84C) +#define SECURE_SCRATCH_RSV64_LO U(0x850) +#define SECURE_SCRATCH_RSV64_HI U(0x854) +#define SECURE_SCRATCH_RSV65_LO U(0x858) +#define SECURE_SCRATCH_RSV65_HI U(0x85c) +#define SECURE_SCRATCH_RSV66_LO U(0x860) +#define SECURE_SCRATCH_RSV66_HI U(0x864) +#define SECURE_SCRATCH_RSV68_LO U(0x870) #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6 -#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO -#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI +#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO +#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI #define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO #define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI #define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO @@ -279,4 +311,17 @@ #define TEGRA_TZRAM_BASE U(0x30000000) #define TEGRA_TZRAM_SIZE U(0x40000) +/******************************************************************************* + * Tegra CCPLEX-BPMP IPC constants + ******************************************************************************/ +#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000) +#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000) +#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ + +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE ULL(0x80000000) +#define TEGRA_DRAM_END ULL(0x27FFFFFFF) + #endif /* TEGRA_DEF_H */ diff --git a/plat/nvidia/tegra/include/t186/tegra_mc_def.h b/plat/nvidia/tegra/include/t186/tegra_mc_def.h index d051a150a..fa447725b 100644 --- a/plat/nvidia/tegra/include/t186/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_mc_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -282,4 +282,117 @@ #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24) #define MC_CLIENT_HOTRESET_STATUS1 0x974U +#ifndef __ASSEMBLER__ + +/******************************************************************************* + * Structure to hold the transaction override settings to use to override + * client inputs + ******************************************************************************/ +typedef struct mc_txn_override_cfg { + uint32_t offset; + uint8_t cgid_tag; +} mc_txn_override_cfg_t; + +#define mc_make_txn_override_cfg(off, val) \ + { \ + .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ + .cgid_tag = MC_TXN_OVERRIDE_ ## val \ + } + +/******************************************************************************* + * Structure to hold the Stream ID to use to override client inputs + ******************************************************************************/ +typedef struct mc_streamid_override_cfg { + uint32_t offset; + uint8_t stream_id; +} mc_streamid_override_cfg_t; + +/******************************************************************************* + * Structure to hold the Stream ID Security Configuration settings + ******************************************************************************/ +typedef struct mc_streamid_security_cfg { + char *name; + uint32_t offset; + uint32_t override_enable; + uint32_t override_client_inputs; + uint32_t override_client_ns_flag; +} mc_streamid_security_cfg_t; + +#define OVERRIDE_DISABLE 1U +#define OVERRIDE_ENABLE 0U +#define CLIENT_FLAG_SECURE 0U +#define CLIENT_FLAG_NON_SECURE 1U +#define CLIENT_INPUTS_OVERRIDE 1U +#define CLIENT_INPUTS_NO_OVERRIDE 0U + +/******************************************************************************* + * StreamID to indicate no SMMU translations (requests to be steered on the + * SMMU bypass path) + ******************************************************************************/ +#define MC_STREAM_ID_MAX 0x7FU + +#define mc_make_sec_cfg(off, ns, ovrrd, access) \ + { \ + .name = # off, \ + .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ + MC_STREAMID_OVERRIDE_CFG_ ## off), \ + .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ + .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ + .override_enable = OVERRIDE_ ## access \ + } + +#define mc_make_sid_override_cfg(name) \ + { \ + .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \ + .val = 0x00000000U, \ + } + +#define mc_make_sid_security_cfg(name) \ + { \ + .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \ + .val = 0x00000000U, \ + } + +#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ + ((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ + MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) + +#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \ + MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED + +#define mc_set_tsa_passthrough(client) \ + do { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ + (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ + (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ + } while (0) + +#define mc_set_tsa_w_passthrough(client) \ + do { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + (TSA_CONFIG_STATIC0_CSW_RESET_W & \ + (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ + (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ + } while (0) + +#define mc_set_tsa_r_passthrough(client) \ + { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \ + (TSA_CONFIG_STATIC0_CSR_RESET_R & \ + (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ + (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ + } while (0) + +#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \ + do { \ + tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ + MC_TXN_OVERRIDE_##normal_axi_id | \ + MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \ + MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \ + MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ + } while (0) + +#endif /* __ASSEMBLER__ */ + #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h index 8f1deb2a3..c5a51e951 100644 --- a/plat/nvidia/tegra/include/t194/tegra194_private.h +++ b/plat/nvidia/tegra/include/t194/tegra194_private.h @@ -10,7 +10,7 @@ void tegra194_cpu_reset_handler(void); uint64_t tegra194_get_cpu_reset_handler_base(void); uint64_t tegra194_get_cpu_reset_handler_size(void); -uint64_t tegra194_get_smmu_ctx_offset(void); +uint64_t tegra194_get_mc_ctx_offset(void); void tegra194_set_system_suspend_entry(void); #endif /* TEGRA194_PRIVATE_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra194_ras_private.h b/plat/nvidia/tegra/include/t194/tegra194_ras_private.h new file mode 100644 index 000000000..336461af3 --- /dev/null +++ b/plat/nvidia/tegra/include/t194/tegra194_ras_private.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TEGRA194_RAS_PRIVATE +#define TEGRA194_RAS_PRIVATE + +#include <stdint.h> + +/* Implementation defined RAS error and corresponding error message */ +struct ras_error { + const char *error_msg; + /* IERR(bits[15:8]) from ERR<n>STATUS */ + uint8_t error_code; +}; + +/* RAS error node-specific auxiliary data */ +struct ras_aux_data { + /* name for current RAS node. */ + const char *name; + /* point to null-terminated ras_error array to convert error code to msg. */ + const struct ras_error *error_records; + /* + * function to return an value which needs to be programmed into ERXCTLR_EL1 + * to enable all specified RAS errors for current node. + */ + uint64_t (*err_ctrl)(void); +}; + +/* IFU Uncorrectable RAS ERROR */ +#define IFU_UNCORR_RAS_ERROR_LIST(X) + +/* JSR_RET Uncorrectable RAS ERROR */ +#define JSR_RET_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(JSR_RET, 35, 0x13, "Floating Point Register File Parity Error") \ + X(JSR_RET, 34, 0x12, "Integer Register File Parity Error") \ + X(JSR_RET, 33, 0x11, "Garbage Bundle") \ + X(JSR_RET, 32, 0x10, "Bundle Completion Timeout") + +/* JSR_MTS Uncorrectable RAS ERROR */ +#define JSR_MTS_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(JSR_MTS, 40, 0x28, "CoreSight Access Error") \ + X(JSR_MTS, 39, 0x27, "Dual Execution Uncorrectable Error") \ + X(JSR_MTS, 37, 0x25, "CTU MMIO Region") \ + X(JSR_MTS, 36, 0x24, "MTS MMCRAB Region Access") \ + X(JSR_MTS, 35, 0x23, "MTS_CARVEOUT Access from ARM SW") \ + X(JSR_MTS, 34, 0x22, "NAFLL PLL Failure to Lock") \ + X(JSR_MTS, 32, 0x20, "Internal Uncorrectable MTS Error") + +/* LSD_STQ Uncorrectable RAS ERROR */ +#define LSD_STQ_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(LSD_STQ, 41, 0x39, "Coherent Cache Data Store Multi-Line ECC Error") \ + X(LSD_STQ, 40, 0x38, "Coherent Cache Data Store Uncorrectable ECC Error") \ + X(LSD_STQ, 38, 0x36, "Coherent Cache Data Load Uncorrectable ECC Error") \ + X(LSD_STQ, 33, 0x31, "Coherent Cache Tag Store Parity Error") \ + X(LSD_STQ, 32, 0x30, "Coherent Cache Tag Load Parity Error") + +/* LSD_DCC Uncorrectable RAS ERROR */ +#define LSD_DCC_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(LSD_DCC, 41, 0x49, "BTU Copy Mini-Cache PPN Multi-Hit Error") \ + X(LSD_DCC, 39, 0x47, "Coherent Cache Data Uncorrectable ECC Error") \ + X(LSD_DCC, 37, 0x45, "Version Cache Byte-Enable Parity Error") \ + X(LSD_DCC, 36, 0x44, "Version Cache Data Uncorrectable ECC Error") \ + X(LSD_DCC, 33, 0x41, "BTU Copy Coherent Cache PPN Parity Error") \ + X(LSD_DCC, 32, 0x40, "BTU Copy Coherent Cache VPN Parity Error") + +/* LSD_L1HPF Uncorrectable RAS ERROR */ +#define LSD_L1HPF_UNCORR_RAS_ERROR_LIST(X) + +/* L2 Uncorrectable RAS ERROR */ +#define L2_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(L2, 56, 0x68, "URT Timeout") \ + X(L2, 55, 0x67, "L2 Protocol Violation") \ + X(L2, 54, 0x66, "SCF to L2 Slave Error Read") \ + X(L2, 53, 0x65, "SCF to L2 Slave Error Write") \ + X(L2, 52, 0x64, "SCF to L2 Decode Error Read") \ + X(L2, 51, 0x63, "SCF to L2 Decode Error Write") \ + X(L2, 50, 0x62, "SCF to L2 Request Response Interface Parity Errors") \ + X(L2, 49, 0x61, "SCF to L2 Advance notice interface parity errors") \ + X(L2, 48, 0x60, "SCF to L2 Filldata Parity Errors") \ + X(L2, 47, 0x5F, "SCF to L2 UnCorrectable ECC Data Error on interface") \ + X(L2, 45, 0x5D, "Core 1 to L2 Parity Error") \ + X(L2, 44, 0x5C, "Core 0 to L2 Parity Error") \ + X(L2, 43, 0x5B, "L2 Multi-Hit") \ + X(L2, 42, 0x5A, "L2 URT Tag Parity Error") \ + X(L2, 41, 0x59, "L2 NTT Tag Parity Error") \ + X(L2, 40, 0x58, "L2 MLT Tag Parity Error") \ + X(L2, 39, 0x57, "L2 URD Data") \ + X(L2, 38, 0x56, "L2 NTP Data") \ + X(L2, 36, 0x54, "L2 MLC Uncorrectable Clean") \ + X(L2, 35, 0x53, "L2 URD Uncorrectable Dirty") \ + X(L2, 34, 0x52, "L2 MLC Uncorrectable Dirty") + +/* CLUSTER_CLOCKS Uncorrectable RAS ERROR */ +#define CLUSTER_CLOCKS_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(CLUSTER_CLOCKS, 32, 0xE4, "Frequency Monitor Error") + +/* MMU Uncorrectable RAS ERROR */ +#define MMU_UNCORR_RAS_ERROR_LIST(X) + +/* L3 Uncorrectable RAS ERROR */ +#define L3_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(L3, 43, 0x7B, "SNOC Interface Parity Error") \ + X(L3, 42, 0x7A, "MCF Interface Parity Error") \ + X(L3, 41, 0x79, "L3 Tag Parity Error") \ + X(L3, 40, 0x78, "L3 Dir Parity Error") \ + X(L3, 39, 0x77, "L3 Uncorrectable ECC Error") \ + X(L3, 37, 0x75, "Multi-Hit CAM Error") \ + X(L3, 36, 0x74, "Multi-Hit Tag Error") \ + X(L3, 35, 0x73, "Unrecognized Command Error") \ + X(L3, 34, 0x72, "L3 Protocol Error") + +/* CCPMU Uncorrectable RAS ERROR */ +#define CCPMU_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(CCPMU, 40, 0x87, "CoreSight Access Error") \ + X(CCPMU, 36, 0x84, "MCE Ucode Error") \ + X(CCPMU, 35, 0x83, "MCE IL1 Parity Error") \ + X(CCPMU, 34, 0x82, "MCE Timeout Error") \ + X(CCPMU, 33, 0x81, "CRAB Access Error") \ + X(CCPMU, 32, 0x80, "MCE Memory Access Error") + +/* SCF_IOB Uncorrectable RAS ERROR */ +#define SCF_IOB_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(SCF_IOB, 41, 0x99, "Request parity error") \ + X(SCF_IOB, 40, 0x98, "Putdata parity error") \ + X(SCF_IOB, 39, 0x97, "Uncorrectable ECC on Putdata") \ + X(SCF_IOB, 38, 0x96, "CBB Interface Error") \ + X(SCF_IOB, 37, 0x95, "MMCRAB Error") \ + X(SCF_IOB, 36, 0x94, "IHI Interface Error") \ + X(SCF_IOB, 35, 0x93, "CRI Error") \ + X(SCF_IOB, 34, 0x92, "TBX Interface Error") \ + X(SCF_IOB, 33, 0x91, "EVP Interface Error") + +/* SCF_SNOC Uncorrectable RAS ERROR */ +#define SCF_SNOC_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(SCF_SNOC, 42, 0xAA, "Misc Client Parity Error") \ + X(SCF_SNOC, 41, 0xA9, "Misc Filldata Parity Error") \ + X(SCF_SNOC, 40, 0xA8, "Uncorrectable ECC Misc Client") \ + X(SCF_SNOC, 39, 0xA7, "DVMU Interface Parity Error") \ + X(SCF_SNOC, 38, 0xA6, "DVMU Interface Timeout Error") \ + X(SCF_SNOC, 37, 0xA5, "CPE Request Error") \ + X(SCF_SNOC, 36, 0xA4, "CPE Response Error") \ + X(SCF_SNOC, 35, 0xA3, "CPE Timeout Error") \ + X(SCF_SNOC, 34, 0xA2, "Uncorrectable Carveout Error") + +/* SCF_CTU Uncorrectable RAS ERROR */ +#define SCF_CTU_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(SCF_CTU, 39, 0xB7, "Timeout error for TRC_DMA request") \ + X(SCF_CTU, 38, 0xB6, "Timeout error for CTU Snp") \ + X(SCF_CTU, 37, 0xB5, "Parity error in CTU TAG RAM") \ + X(SCF_CTU, 36, 0xB3, "Parity error in CTU DATA RAM") \ + X(SCF_CTU, 35, 0xB4, "Parity error for Cluster Rsp") \ + X(SCF_CTU, 34, 0xB2, "Parity error for TRL requests from 9 agents") \ + X(SCF_CTU, 33, 0xB1, "Parity error for MCF request") \ + X(SCF_CTU, 32, 0xB0, "TRC DMA fillsnoop parity error") + +/* CMU_CLOCKS Uncorrectable RAS ERROR */ +#define CMU_CLOCKS_UNCORR_RAS_ERROR_LIST(X) \ + /* Name, ERR_CTRL, IERR, ISA Desc */ \ + X(CMU_CLOCKS, 39, 0xC7, "Cluster 3 frequency monitor error") \ + X(CMU_CLOCKS, 38, 0xC6, "Cluster 2 frequency monitor error") \ + X(CMU_CLOCKS, 37, 0xC5, "Cluster 1 frequency monitor error") \ + X(CMU_CLOCKS, 36, 0xC3, "Cluster 0 frequency monitor error") \ + X(CMU_CLOCKS, 35, 0xC4, "Voltage error on ADC1 Monitored Logic") \ + X(CMU_CLOCKS, 34, 0xC2, "Voltage error on ADC0 Monitored Logic") \ + X(CMU_CLOCKS, 33, 0xC1, "Lookup Table 1 Parity Error") \ + X(CMU_CLOCKS, 32, 0xC0, "Lookup Table 0 Parity Error") + +/* + * Define one ras_error entry. + * + * This macro wille be used to to generate ras_error records for each node + * defined by <NODE_NAME>_UNCORR_RAS_ERROR_LIST macro. + */ +#define DEFINE_ONE_RAS_ERROR_MSG(unit, ras_bit, ierr, msg) \ + { \ + .error_msg = (msg), \ + .error_code = (ierr) \ + }, + +/* + * Set one implementation defined bit in ERR<n>CTLR + * + * This macro will be used to collect all defined ERR_CTRL bits for each node + * defined by <NODE_NAME>_UNCORR_RAS_ERROR_LIST macro. + */ +#define DEFINE_ENABLE_RAS_BIT(unit, ras_bit, ierr, msg) \ + do { \ + val |= (1ULL << ras_bit##U); \ + } while (0); + +/* Represent one RAS node with 0 or more error bits (ERR_CTLR) enabled */ +#define DEFINE_ONE_RAS_NODE(node) \ +static const struct ras_error node##_uncorr_ras_errors[] = { \ + node##_UNCORR_RAS_ERROR_LIST(DEFINE_ONE_RAS_ERROR_MSG) \ + { \ + NULL, \ + 0U \ + }, \ +}; \ +static inline uint64_t node##_err_ctrl(void) \ +{ \ + uint64_t val = 0ULL; \ + node##_UNCORR_RAS_ERROR_LIST(DEFINE_ENABLE_RAS_BIT) \ + return val; \ +} + +#define DEFINE_ONE_RAS_AUX_DATA(node) \ + { \ + .name = #node, \ + .error_records = node##_uncorr_ras_errors, \ + .err_ctrl = &node##_err_ctrl \ + }, + +#define PER_CORE_RAS_NODE_LIST(X) \ + X(IFU) \ + X(JSR_RET) \ + X(JSR_MTS) \ + X(LSD_STQ) \ + X(LSD_DCC) \ + X(LSD_L1HPF) + +#define PER_CORE_RAS_GROUP_NODES PER_CORE_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) + +#define PER_CLUSTER_RAS_NODE_LIST(X) \ + X(L2) \ + X(CLUSTER_CLOCKS) \ + X(MMU) + +#define PER_CLUSTER_RAS_GROUP_NODES PER_CLUSTER_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) + +#define SCF_L3_BANK_RAS_NODE_LIST(X) X(L3) + +/* we have 4 SCF_L3 nodes:3*256 + L3_Bank_ID(0-3) */ +#define SCF_L3_BANK_RAS_GROUP_NODES \ + SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ + SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ + SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) \ + SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) + +#define CCPLEX_RAS_NODE_LIST(X) \ + X(CCPMU) \ + X(SCF_IOB) \ + X(SCF_SNOC) \ + X(SCF_CTU) \ + X(CMU_CLOCKS) + +#define CCPLEX_RAS_GROUP_NODES CCPLEX_RAS_NODE_LIST(DEFINE_ONE_RAS_AUX_DATA) + +#endif /* TEGRA194_RAS_PRIVATE */ diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index df1d65630..abe193fcd 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -10,6 +10,17 @@ #include <lib/utils_def.h> /******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + +/******************************************************************************* + * Chip specific cluster and cpu numbers + ******************************************************************************/ +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) + +/******************************************************************************* * Chip specific page table and MMU setup constants ******************************************************************************/ #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) @@ -43,6 +54,12 @@ #define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ /******************************************************************************* + * Clock identifier for the SE device + ******************************************************************************/ +#define TEGRA194_CLK_SE U(124) +#define TEGRA_CLK_SE TEGRA194_CLK_SE + +/******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) @@ -93,6 +110,8 @@ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) +#define MC_VIDEO_PROTECT_REG_CTRL U(0x650) +#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) /* * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the @@ -197,6 +216,16 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV68_LO U(0x284) +#define SECURE_SCRATCH_RSV68_HI U(0x288) +#define SECURE_SCRATCH_RSV69_LO U(0x28C) +#define SECURE_SCRATCH_RSV69_HI U(0x290) +#define SECURE_SCRATCH_RSV70_LO U(0x294) +#define SECURE_SCRATCH_RSV70_HI U(0x298) +#define SECURE_SCRATCH_RSV71_LO U(0x29C) +#define SECURE_SCRATCH_RSV71_HI U(0x2A0) +#define SECURE_SCRATCH_RSV72_LO U(0x2A4) +#define SECURE_SCRATCH_RSV72_HI U(0x2A8) #define SECURE_SCRATCH_RSV75 U(0x2BC) #define SECURE_SCRATCH_RSV81_LO U(0x2EC) #define SECURE_SCRATCH_RSV81_HI U(0x2F0) @@ -215,8 +244,8 @@ #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) #define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 -#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO -#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI +#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO +#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI @@ -257,6 +286,12 @@ #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) /******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE ULL(0x80000000) +#define TEGRA_DRAM_END ULL(0xFFFFFFFFF) + +/******************************************************************************* * XUSB STREAMIDs ******************************************************************************/ #define TEGRA_SID_XUSB_HOST U(0x1b) @@ -266,4 +301,26 @@ #define TEGRA_SID_XUSB_VF2 U(0x5f) #define TEGRA_SID_XUSB_VF3 U(0x60) +/******************************************************************************* + * SCR addresses and expected settings + ******************************************************************************/ +#define SCRATCH_RSV68_SCR U(0x0C398110) +#define SCRATCH_RSV68_SCR_VAL U(0x38000101) +#define SCRATCH_RSV71_SCR U(0x0C39811C) +#define SCRATCH_RSV71_SCR_VAL U(0x38000101) +#define SCRATCH_RSV72_SCR U(0x0C398120) +#define SCRATCH_RSV72_SCR_VAL U(0x38000101) +#define SCRATCH_RSV75_SCR U(0x0C39812C) +#define SCRATCH_RSV75_SCR_VAL U(0x3A000005) +#define SCRATCH_RSV81_SCR U(0x0C398144) +#define SCRATCH_RSV81_SCR_VAL U(0x3A000105) +#define SCRATCH_RSV97_SCR U(0x0C398184) +#define SCRATCH_RSV97_SCR_VAL U(0x38000101) +#define SCRATCH_RSV99_SCR U(0x0C39818C) +#define SCRATCH_RSV99_SCR_VAL U(0x38000101) +#define SCRATCH_RSV109_SCR U(0x0C3981B4) +#define SCRATCH_RSV109_SCR_VAL U(0x38000101) +#define MISCREG_SCR_SCRTZWELCK U(0x00109000) +#define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100) + #endif /* TEGRA_DEF_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h deleted file mode 100644 index 34bdd7557..000000000 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ /dev/null @@ -1,685 +0,0 @@ -/* - * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TEGRA_MC_DEF_H -#define TEGRA_MC_DEF_H - -/******************************************************************************* - * Memory Controller Order_id registers - ******************************************************************************/ -#define MC_CLIENT_ORDER_ID_9 U(0x2a24) -#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U -#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12) -#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12) - -#define MC_CLIENT_ORDER_ID_27 U(0x2a6c) -#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U -#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) -#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4) - -#define MC_CLIENT_ORDER_ID_28 U(0x2a70) -#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U -#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) -#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) -#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) -#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12) - -#define mc_client_order_id(val, id, client) \ - ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ - MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) - -/******************************************************************************* - * Memory Controller's VC ID configuration registers - ******************************************************************************/ -#define VC_NISO 0U -#define VC_SISO 1U -#define VC_ISO 2U - -#define MC_HUB_PC_VC_ID_0 U(0x2a78) -#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U -#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8) -#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8) - -#define MC_HUB_PC_VC_ID_2 U(0x2a80) -#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U -#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28) -#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28) - -#define MC_HUB_PC_VC_ID_4 U(0x2a88) -#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U -#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) -#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) - -#define MC_HUB_PC_VC_ID_12 U(0x2aa8) -#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U -#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12) -#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12) - -#define mc_hub_vc_id(val, id, client) \ - ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ - MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) - -/******************************************************************************* - * Memory Controller's PCFIFO client configuration registers - ******************************************************************************/ -#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U - -#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U -#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29) - -#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U -#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21) - -#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU -#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27) - -#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U -#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30) - -#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U -#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0) -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0) -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30) -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30) - -#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U -#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31) -#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31) - -#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU -#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU -#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1) -#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1) -#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3) -#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3) - -/******************************************************************************* - * StreamID to indicate no SMMU translations (requests to be steered on the - * SMMU bypass path) - ******************************************************************************/ -#define MC_STREAM_ID_MAX 0x7FU - -/******************************************************************************* - * Stream ID Override Config registers - ******************************************************************************/ -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U -#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U -#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U -#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U -#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U -#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U -#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U -#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U -#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U -#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U -#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U -#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U -#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U -#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U -#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U -#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U -#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U -#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U -#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U -#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U -#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U -#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U -#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U -#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U -#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U -#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U -#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U -#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U -#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U -#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U -#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U -#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U -#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U -#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U -#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U -#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U -#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U -#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U -#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U -#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U -#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U -#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U -#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U -#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U -#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U -#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U -#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U -#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U -#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U -#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U -#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U -#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U -#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U -#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U -#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U -#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U -#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U -#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U -#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U -#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U -#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U -#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U -#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U -#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U -#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U -#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U -#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U -#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U -#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U -#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U -#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U -#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U -#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U -#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U -#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U -#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U -#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U -#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U -#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U -#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U -#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U -#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U -#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U -#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U -#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U -#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U -#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U -#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U -#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U -#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U -#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U -#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U -#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U -#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U -#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U -#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U -#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U -#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U -#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U -#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U -#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U -#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U -#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U -#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U -#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U -#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U - -/******************************************************************************* - * Macro to calculate Security cfg register addr from StreamID Override register - ******************************************************************************/ -#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t)) - -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4) - -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8) - -#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12) -#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12) - -/******************************************************************************* - * Memory Controller transaction override config registers - ******************************************************************************/ -#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U -#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U -#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U -#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U -#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U -#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU -#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U -#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U -#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U -#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U -#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U -#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU -#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U -#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U -#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U -#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U -#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU -#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U -#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U -#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U -#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U -#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U -#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U -#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU -#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U -#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U -#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU -#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU -#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U -#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U -#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU -#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U -#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U -#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U -#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU -#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U -#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U -#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U -#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U -#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U -#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U -#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U -#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U -#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U -#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU -#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U -#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U -#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U -#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU -#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U -#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U -#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U -#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U -#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U -#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U -#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U -#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U -#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU -#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U -#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U -#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U -#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U -#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U -#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U -#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U -#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U -#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU -#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U -#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU -#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U -#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U -#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U -#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U -#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U -#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU -#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U -#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU -#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU -#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU -#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU -#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U -#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU -#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U -#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U -#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U -#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U -#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U -#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U -#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU -#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U -#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U -#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U -#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U -#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U -#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U -#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U -#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U -#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU -#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U -#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U -#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U -#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U -#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U -#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU -#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU -#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U -#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU -#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU -#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U -#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U -#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U -#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U -#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U -#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U - -#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0) -#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4) -#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12) - -/******************************************************************************* - * Non-SO_DEV transactions override values for CGID_TAG bitfield for the - * MC_TXN_OVERRIDE_CONFIG_{module} registers - ******************************************************************************/ -#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U -#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U -#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U -#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U -#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL - -/******************************************************************************* - * Memory Controller Reset Control registers - ******************************************************************************/ -#define MC_CLIENT_HOTRESET_CTRL0 0x200U -#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U -#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0) -#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6) -#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7) -#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8) -#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9) -#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11) -#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15) -#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17) -#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18) -#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19) -#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20) -#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22) -#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29) -#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30) -#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31) -#define MC_CLIENT_HOTRESET_STATUS0 0x204U -#define MC_CLIENT_HOTRESET_CTRL1 0x970U -#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U -#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0) -#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2) -#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5) -#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6) -#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7) -#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8) -#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12) -#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13) -#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17) -#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18) -#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19) -#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20) -#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21) -#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22) -#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23) -#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26) -#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31) -#define MC_CLIENT_HOTRESET_STATUS1 0x974U -#define MC_CLIENT_HOTRESET_CTRL2 0x97cU -#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U -#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4) -#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9) -#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10) -#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11) -#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23) -#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25) -#define MC_CLIENT_HOTRESET_STATUS2 0x1898U - -#define MC_COALESCE_CTRL 0x2930U -#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) -#define MC_COALESCE_CONFIG_6_0 0x294cU -#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8) -#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14) - -/******************************************************************************* - * Tegra TSA Controller constants - ******************************************************************************/ -#define TEGRA_TSA_BASE U(0x02000000) - -#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U -#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U -#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U - -#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U -#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U -#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU -#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U -#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U -#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U -#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU -#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U -#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U -#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U -#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U -#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U -#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U -#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU -#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U -#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U -#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U -#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U -#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U -#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U -#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U -#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U -#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU -#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U -#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U -#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U -#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU -#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U -#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U -#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU -#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U -#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U -#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU -#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U -#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U -#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U -#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U -#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U -#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U -#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U -#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U -#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U -#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U -#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U -#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU -#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U -#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U -#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U -#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U -#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U -#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U -#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U -#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU -#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U -#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U -#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U -#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U -#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U -#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U -#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU -#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U -#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U -#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU -#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U -#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U -#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U -#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU -#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U -#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U -#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U -#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U -#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U -#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U -#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U -#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U -#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U -#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U -#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U -#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U -#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U -#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U -#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U -#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U -#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U -#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U -#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U -#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U -#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U -#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U -#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U -#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U -#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U -#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U -#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U -#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U -#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U -#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U -#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U -#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U - -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) -#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) -#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) - -#define REORDER_DEPTH_LIMIT 16 -#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK (ULL(0x7FF) << 21) -#define reorder_depth_limit(limit) (ULL(limit) << 21) - -#define tsa_read_32(client) \ - mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) - -#define mc_set_tsa_hub2(val, client) \ - { \ - mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ - ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \ - TSA_CONFIG_CSW_SO_DEV_HUB2)); \ - } - -#define mc_set_tsa_depth_limit(limit, client) \ - { \ - uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \ - mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ - ((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \ - reorder_depth_limit(limit))); \ - } - -#endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index bbcfdc5c1..81b25e036 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +11,11 @@ #include <lib/utils_def.h> /******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + +/******************************************************************************* * Power down state IDs ******************************************************************************/ #define PSTATE_ID_CORE_POWERDN U(7) @@ -43,6 +49,11 @@ #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400) /******************************************************************************* + * Counter-timer physical secure timer PPI + ******************************************************************************/ +#define TEGRA210_TIMER1_IRQ 32 + +/******************************************************************************* * iRAM memory constants ******************************************************************************/ #define TEGRA_IRAM_BASE U(0x40000000) @@ -143,6 +154,9 @@ #define SE_CLK_ENB_BIT (U(1) << 31) #define TEGRA_CLK_OUT_ENB_W U(0x364) #define ENTROPY_RESET_BIT (U(1) << 21) +#define TEGRA_CLK_RST_CTL_CLK_SRC_SE U(0x42C) +#define SE_CLK_SRC_MASK (U(7) << 29) +#define SE_CLK_SRC_CLK_M (U(6) << 29) #define TEGRA_RST_DEV_SET_V U(0x430) #define SE_RESET_BIT (U(1) << 31) #define HDA_RESET_BIT (U(1) << 29) @@ -231,6 +245,8 @@ #define MC_VIDEO_PROTECT_BASE_HI U(0x978) #define MC_VIDEO_PROTECT_BASE_LO U(0x648) #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) +#define MC_VIDEO_PROTECT_REG_CTRL U(0x650) +#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) /* SMMU configuration registers*/ #define MC_SMMU_PPCS_ASID_0 0x270U @@ -268,4 +284,10 @@ #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE ULL(0x80000000) +#define TEGRA_DRAM_END ULL(0x27FFFFFFF) + #endif /* TEGRA_DEF_H */ diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h index d83ce48b8..b8297fd93 100644 --- a/plat/nvidia/tegra/include/tegra_platform.h +++ b/plat/nvidia/tegra/include/tegra_platform.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,6 +30,13 @@ #define TEGRA_CHIPID_TEGRA13 U(0x13) #define TEGRA_CHIPID_TEGRA21 U(0x21) #define TEGRA_CHIPID_TEGRA18 U(0x18) +#define TEGRA_CHIPID_TEGRA19 U(0x19) + +/******************************************************************************* + * JEDEC Standard Manufacturer's Identification Code and Bank ID + ******************************************************************************/ +#define JEDEC_NVIDIA_MFID U(0x6B) +#define JEDEC_NVIDIA_BKID U(3) #ifndef __ASSEMBLER__ @@ -45,6 +53,7 @@ bool tegra_chipid_is_t132(void); bool tegra_chipid_is_t186(void); bool tegra_chipid_is_t210(void); bool tegra_chipid_is_t210_b01(void); +bool tegra_chipid_is_t194(void); /* * Tegra platform identifiers diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 761acdea5..cc2ad869c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +9,7 @@ #define TEGRA_PRIVATE_H #include <platform_def.h> +#include <stdbool.h> #include <arch.h> #include <arch_helpers.h> @@ -18,12 +20,6 @@ #include <tegra_gic.h> /******************************************************************************* - * Tegra DRAM memory base address - ******************************************************************************/ -#define TEGRA_DRAM_BASE ULL(0x80000000) -#define TEGRA_DRAM_END ULL(0x27FFFFFFF) - -/******************************************************************************* * Implementation defined ACTLR_EL1 bit definitions ******************************************************************************/ #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) @@ -51,6 +47,8 @@ typedef struct plat_params_from_bl2 { uint64_t sc7entry_fw_size; /* System Suspend Entry Firmware base address */ uint64_t sc7entry_fw_base; + /* Enable dual execution */ + uint8_t enable_ccplex_lock_step; } plat_params_from_bl2_t; /******************************************************************************* @@ -70,6 +68,11 @@ struct tegra_bl31_params { image_info_t *bl33_image_info; }; +/******************************************************************************* +* To suppress Coverity MISRA C-2012 Rule 2.2 violations +*******************************************************************************/ +#define UNUSED_FUNC_NOP() asm("nop") + /* Declarations for plat_psci_handlers.c */ int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state); @@ -82,6 +85,9 @@ struct tegra_bl31_params *plat_get_bl31_params(void); plat_params_from_bl2_t *plat_get_bl31_plat_params(void); void plat_early_platform_setup(void); void plat_late_platform_setup(void); +void plat_relocate_bl32_image(const image_info_t *bl32_img_info); +bool plat_supports_system_suspend(void); +void plat_runtime_setup(void); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); @@ -89,7 +95,7 @@ int32_t plat_lock_cpu_vectors(void); /* Declarations for tegra_fiq_glue.c */ void tegra_fiq_handler_setup(void); -int tegra_fiq_get_intr_context(void); +int32_t tegra_fiq_get_intr_context(void); void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); /* Declarations for tegra_security.c */ @@ -106,24 +112,12 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); +int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); int32_t tegra_soc_prepare_system_reset(void); __dead2 void tegra_soc_prepare_system_off(void); plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, const plat_local_state_t *states, uint32_t ncpu); -void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); -void tegra_cpu_standby(plat_local_state_t cpu_state); -int32_t tegra_pwr_domain_on(u_register_t mpidr); -void tegra_pwr_domain_off(const psci_power_state_t *target_state); -void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); -void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); -void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); -void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); -__dead2 void tegra_system_off(void); -__dead2 void tegra_system_reset(void); -int32_t tegra_validate_power_state(uint32_t power_state, - psci_power_state_t *req_state); -int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); /* Declarations for tegraXXX_pm.c */ int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); @@ -156,4 +150,9 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags); +#if RAS_EXTENSION +void tegra194_ras_enable(void); +void tegra194_ras_corrected_err_clear(uint64_t *cookie); +#endif + #endif /* TEGRA_PRIVATE_H */ |