diff options
Diffstat (limited to 'plat/nvidia/tegra/include/tegra_private.h')
| -rw-r--r-- | plat/nvidia/tegra/include/tegra_private.h | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 761acdea5..cc2ad869c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +9,7 @@ #define TEGRA_PRIVATE_H #include <platform_def.h> +#include <stdbool.h> #include <arch.h> #include <arch_helpers.h> @@ -18,12 +20,6 @@ #include <tegra_gic.h> /******************************************************************************* - * Tegra DRAM memory base address - ******************************************************************************/ -#define TEGRA_DRAM_BASE ULL(0x80000000) -#define TEGRA_DRAM_END ULL(0x27FFFFFFF) - -/******************************************************************************* * Implementation defined ACTLR_EL1 bit definitions ******************************************************************************/ #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) @@ -51,6 +47,8 @@ typedef struct plat_params_from_bl2 { uint64_t sc7entry_fw_size; /* System Suspend Entry Firmware base address */ uint64_t sc7entry_fw_base; + /* Enable dual execution */ + uint8_t enable_ccplex_lock_step; } plat_params_from_bl2_t; /******************************************************************************* @@ -70,6 +68,11 @@ struct tegra_bl31_params { image_info_t *bl33_image_info; }; +/******************************************************************************* +* To suppress Coverity MISRA C-2012 Rule 2.2 violations +*******************************************************************************/ +#define UNUSED_FUNC_NOP() asm("nop") + /* Declarations for plat_psci_handlers.c */ int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state); @@ -82,6 +85,9 @@ struct tegra_bl31_params *plat_get_bl31_params(void); plat_params_from_bl2_t *plat_get_bl31_plat_params(void); void plat_early_platform_setup(void); void plat_late_platform_setup(void); +void plat_relocate_bl32_image(const image_info_t *bl32_img_info); +bool plat_supports_system_suspend(void); +void plat_runtime_setup(void); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); @@ -89,7 +95,7 @@ int32_t plat_lock_cpu_vectors(void); /* Declarations for tegra_fiq_glue.c */ void tegra_fiq_handler_setup(void); -int tegra_fiq_get_intr_context(void); +int32_t tegra_fiq_get_intr_context(void); void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); /* Declarations for tegra_security.c */ @@ -106,24 +112,12 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); +int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); int32_t tegra_soc_prepare_system_reset(void); __dead2 void tegra_soc_prepare_system_off(void); plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, const plat_local_state_t *states, uint32_t ncpu); -void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); -void tegra_cpu_standby(plat_local_state_t cpu_state); -int32_t tegra_pwr_domain_on(u_register_t mpidr); -void tegra_pwr_domain_off(const psci_power_state_t *target_state); -void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); -void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); -void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); -void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); -__dead2 void tegra_system_off(void); -__dead2 void tegra_system_reset(void); -int32_t tegra_validate_power_state(uint32_t power_state, - psci_power_state_t *req_state); -int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); /* Declarations for tegraXXX_pm.c */ int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); @@ -156,4 +150,9 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags); +#if RAS_EXTENSION +void tegra194_ras_enable(void); +void tegra194_ras_corrected_err_clear(uint64_t *cookie); +#endif + #endif /* TEGRA_PRIVATE_H */ |