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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-25 14:57:57 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:20:59 +0000 |
| commit | 98551591f5371de2c2f0dee6be2e12b75653f04d (patch) | |
| tree | 8d894f2bf5d5e3ec7d29ca270169c2c37457e814 /docs | |
| parent | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 (diff) | |
| download | platform_external_arm-trusted-firmware-98551591f5371de2c2f0dee6be2e12b75653f04d.tar.gz platform_external_arm-trusted-firmware-98551591f5371de2c2f0dee6be2e12b75653f04d.tar.bz2 platform_external_arm-trusted-firmware-98551591f5371de2c2f0dee6be2e12b75653f04d.zip | |
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index dbb18569b..73ed38230 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -142,6 +142,9 @@ For Cortex-A75, the following errata build flags are defined : - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU. +- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + DSU Errata Workarounds ---------------------- |