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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-20 12:11:41 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 15:53:57 +0000 |
| commit | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 (patch) | |
| tree | f2144f3d54b1dfd7625bdcf08438573f569d2101 /docs | |
| parent | e6cab15dc710e2270d869c3fa76ed8d0d4943b66 (diff) | |
| download | platform_external_arm-trusted-firmware-5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8.tar.gz platform_external_arm-trusted-firmware-5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8.tar.bz2 platform_external_arm-trusted-firmware-5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8.zip | |
Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index d417521e4..dbb18569b 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -137,6 +137,11 @@ For Cortex-A73, the following errata build flags are defined : - ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. +For Cortex-A75, the following errata build flags are defined : + +- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + DSU Errata Workarounds ---------------------- |