From 98551591f5371de2c2f0dee6be2e12b75653f04d Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Mon, 25 Feb 2019 14:57:57 +0000 Subject: Add workaround for errata 790748 for Cortex-A75 Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt --- docs/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs') diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index dbb18569b..73ed38230 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -142,6 +142,9 @@ For Cortex-A75, the following errata build flags are defined : - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU. +- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + DSU Errata Workarounds ---------------------- -- cgit v1.2.3