diff options
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/arm/neon')
1996 files changed, 40690 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp new file mode 100644 index 000000000..746429dad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c new file mode 100644 index 000000000..f91f800a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c @@ -0,0 +1,48 @@ +/* Check that NEON polynomial vector types are suitably incompatible with + integer vector types of the same layout. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void s64_8 (int8x8_t a) {} +void u64_8 (uint8x8_t a) {} +void p64_8 (poly8x8_t a) {} +void s64_16 (int16x4_t a) {} +void u64_16 (uint16x4_t a) {} +void p64_16 (poly16x4_t a) {} + +void s128_8 (int8x16_t a) {} +void u128_8 (uint8x16_t a) {} +void p128_8 (poly8x16_t a) {} +void s128_16 (int16x8_t a) {} +void u128_16 (uint16x8_t a) {} +void p128_16 (poly16x8_t a) {} + +void foo () +{ + poly8x8_t v64_8; + poly16x4_t v64_16; + poly8x16_t v128_8; + poly16x8_t v128_16; + + s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */ + /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */ + u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */ + p64_8 (v64_8); + + s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */ + u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */ + p64_16 (v64_16); + + s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */ + u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */ + p128_8 (v128_8); + + s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */ + u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */ + p128_16 (v128_16); +} +/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c new file mode 100644 index 000000000..71cbb055f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c @@ -0,0 +1,84 @@ +/* Test the vector comparison intrinsics when comparing to immediate zero. + */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +#define GEN_TEST(T, D, C, R) \ + R test_##C##_##T (T a) { return C (a, D (0)); } + +#define GEN_DOUBLE_TESTS(S, T, C) \ + GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \ + GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) + +#define GEN_QUAD_TESTS(S, T, C) \ + GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \ + GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) + +#define GEN_COND_TESTS(C) \ + GEN_DOUBLE_TESTS (8, int8x8_t, C) \ + GEN_DOUBLE_TESTS (16, int16x4_t, C) \ + GEN_DOUBLE_TESTS (32, int32x2_t, C) \ + GEN_QUAD_TESTS (8, int8x16_t, C) \ + GEN_QUAD_TESTS (16, int16x8_t, C) \ + GEN_QUAD_TESTS (32, int32x4_t, C) + +GEN_COND_TESTS(vcgt) +GEN_COND_TESTS(vcge) +GEN_COND_TESTS(vclt) +GEN_COND_TESTS(vcle) +GEN_COND_TESTS(vceq) + +/* Scan for expected outputs. */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ + +/* And ensure we don't have unexpected output too. */ +/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */ + +/* Tidy up. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c new file mode 100644 index 000000000..8a8032d01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c new file mode 100644 index 000000000..45b577631 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c new file mode 100644 index 000000000..4e564ee10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c new file mode 100644 index 000000000..f036e0438 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c new file mode 100644 index 000000000..f9fbb869d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c new file mode 100644 index 000000000..853ab7fcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c new file mode 100644 index 000000000..1be084ede --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c new file mode 100644 index 000000000..acc6c0176 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c new file mode 100644 index 000000000..bfac186e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c new file mode 100644 index 000000000..10dcdfe12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c new file mode 100644 index 000000000..9c6178135 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c new file mode 100644 index 000000000..ac8488498 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c new file mode 100644 index 000000000..a1207e2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c new file mode 100644 index 000000000..758572982 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c new file mode 100644 index 000000000..c6048c2e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c new file mode 100644 index 000000000..41e03fe6d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c new file mode 100644 index 000000000..f0cdae6d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c new file mode 100644 index 000000000..278496f28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c new file mode 100644 index 000000000..622cd3843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c new file mode 100644 index 000000000..9d6c8b849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c new file mode 100644 index 000000000..d9f1accae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c new file mode 100644 index 000000000..695e9e17f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c new file mode 100644 index 000000000..1abf88844 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c new file mode 100644 index 000000000..ee517d83b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c new file mode 100644 index 000000000..ec46e7632 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c new file mode 100644 index 000000000..3abdefcd8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c new file mode 100644 index 000000000..5d13fac3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c @@ -0,0 +1,21 @@ +/* Test the `vRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c new file mode 100644 index 000000000..71ed3401f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c @@ -0,0 +1,21 @@ +/* Test the `vRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c new file mode 100644 index 000000000..c6e20c0dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c @@ -0,0 +1,21 @@ +/* Test the `vRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c new file mode 100644 index 000000000..b4cc42739 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c @@ -0,0 +1,21 @@ +/* Test the `vRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c new file mode 100644 index 000000000..42c77250c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c new file mode 100644 index 000000000..dfc5da7f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c new file mode 100644 index 000000000..030b5eed3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c new file mode 100644 index 000000000..2e091b39b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c new file mode 100644 index 000000000..f844a5bfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c new file mode 100644 index 000000000..a651bf484 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c new file mode 100644 index 000000000..2e78282d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c new file mode 100644 index 000000000..376fcf1d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c new file mode 100644 index 000000000..ae1555dcf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c new file mode 100644 index 000000000..18ec347c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c new file mode 100644 index 000000000..370ae502f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c new file mode 100644 index 000000000..5c5149ed0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c new file mode 100644 index 000000000..3045dddee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c new file mode 100644 index 000000000..2c3c12665 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c new file mode 100644 index 000000000..182c56b86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c new file mode 100644 index 000000000..1e41c26be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c new file mode 100644 index 000000000..c34b54e22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c new file mode 100644 index 000000000..c07863ec1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c new file mode 100644 index 000000000..910d7de54 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c new file mode 100644 index 000000000..25b5a6b5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c new file mode 100644 index 000000000..966e6c78e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c new file mode 100644 index 000000000..6227223e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c new file mode 100644 index 000000000..d219e9482 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c new file mode 100644 index 000000000..9f59e8c3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c new file mode 100644 index 000000000..d7904ea56 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c new file mode 100644 index 000000000..33d390157 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c new file mode 100644 index 000000000..cb7c469a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c new file mode 100644 index 000000000..3ac2e316e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c new file mode 100644 index 000000000..d0b6a9272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c new file mode 100644 index 000000000..af402f4f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c new file mode 100644 index 000000000..b8c0fbf1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c new file mode 100644 index 000000000..7bec98340 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c new file mode 100644 index 000000000..167a27c4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c new file mode 100644 index 000000000..14a6251fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c new file mode 100644 index 000000000..31d6f0ca3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c new file mode 100644 index 000000000..43fa61aac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c new file mode 100644 index 000000000..1b28f926a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c new file mode 100644 index 000000000..fc810c2cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c new file mode 100644 index 000000000..d951b266b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c new file mode 100644 index 000000000..f7f74c3c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c new file mode 100644 index 000000000..713c7bb1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c new file mode 100644 index 000000000..4b19bd846 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c new file mode 100644 index 000000000..8ba5a2075 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c new file mode 100644 index 000000000..26fa452c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c new file mode 100644 index 000000000..ed990790f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c new file mode 100644 index 000000000..b5e7b28ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c new file mode 100644 index 000000000..5275c97b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c new file mode 100644 index 000000000..3951ff0c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c new file mode 100644 index 000000000..4fe8aa303 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c new file mode 100644 index 000000000..0e2b06fdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c new file mode 100644 index 000000000..679805ad6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c new file mode 100644 index 000000000..87e5f2232 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c new file mode 100644 index 000000000..91ee45dfa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c new file mode 100644 index 000000000..f4adb3272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c new file mode 100644 index 000000000..14f8aa0d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c @@ -0,0 +1,22 @@ +/* Test the `vabals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c new file mode 100644 index 000000000..980b27e6d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c @@ -0,0 +1,22 @@ +/* Test the `vabals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c new file mode 100644 index 000000000..85dcb40b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c @@ -0,0 +1,22 @@ +/* Test the `vabals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c new file mode 100644 index 000000000..9cf105ee3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c @@ -0,0 +1,22 @@ +/* Test the `vabalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c new file mode 100644 index 000000000..dc9925f58 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c @@ -0,0 +1,22 @@ +/* Test the `vabalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c new file mode 100644 index 000000000..464e2cdad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c @@ -0,0 +1,22 @@ +/* Test the `vabalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c new file mode 100644 index 000000000..21f5adbdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c @@ -0,0 +1,22 @@ +/* Test the `vabas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c new file mode 100644 index 000000000..f9a41481e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c @@ -0,0 +1,22 @@ +/* Test the `vabas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c new file mode 100644 index 000000000..609680a05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c @@ -0,0 +1,22 @@ +/* Test the `vabas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c new file mode 100644 index 000000000..0896900fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c @@ -0,0 +1,22 @@ +/* Test the `vabau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c new file mode 100644 index 000000000..4f4f25abd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c @@ -0,0 +1,22 @@ +/* Test the `vabau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c new file mode 100644 index 000000000..91dfc1a83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c @@ -0,0 +1,22 @@ +/* Test the `vabau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c new file mode 100644 index 000000000..50c1acc63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c new file mode 100644 index 000000000..7ef3f2edd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c new file mode 100644 index 000000000..673b01f2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c new file mode 100644 index 000000000..5d24d228f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c new file mode 100644 index 000000000..222384e1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c new file mode 100644 index 000000000..ef5716b69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c new file mode 100644 index 000000000..065a5f3be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c new file mode 100644 index 000000000..8fc0be271 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c @@ -0,0 +1,21 @@ +/* Test the `vabdf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c new file mode 100644 index 000000000..e9df745b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c @@ -0,0 +1,21 @@ +/* Test the `vabdls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c new file mode 100644 index 000000000..b4ad32735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c @@ -0,0 +1,21 @@ +/* Test the `vabdls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c new file mode 100644 index 000000000..75ca12502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c @@ -0,0 +1,21 @@ +/* Test the `vabdls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c new file mode 100644 index 000000000..692962ede --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c new file mode 100644 index 000000000..f5a7ef691 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c new file mode 100644 index 000000000..221729ae6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c new file mode 100644 index 000000000..2d76a286d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c @@ -0,0 +1,21 @@ +/* Test the `vabds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c new file mode 100644 index 000000000..9ca6e5d8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c @@ -0,0 +1,21 @@ +/* Test the `vabds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c new file mode 100644 index 000000000..561687047 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c @@ -0,0 +1,21 @@ +/* Test the `vabds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c new file mode 100644 index 000000000..e23873494 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c new file mode 100644 index 000000000..61871dda4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c new file mode 100644 index 000000000..bff9f9cf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c new file mode 100644 index 000000000..36e145d08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c @@ -0,0 +1,20 @@ +/* Test the `vabsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vabsq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c new file mode 100644 index 000000000..befade576 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c new file mode 100644 index 000000000..8d1270012 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c new file mode 100644 index 000000000..a69d7a89e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c new file mode 100644 index 000000000..e60dd896d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c @@ -0,0 +1,20 @@ +/* Test the `vabsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vabs_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c new file mode 100644 index 000000000..9cc1ab561 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c @@ -0,0 +1,20 @@ +/* Test the `vabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c new file mode 100644 index 000000000..5f3c6353e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c @@ -0,0 +1,20 @@ +/* Test the `vabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c new file mode 100644 index 000000000..05ae5241a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c @@ -0,0 +1,20 @@ +/* Test the `vabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c new file mode 100644 index 000000000..fb856385d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c new file mode 100644 index 000000000..839af2433 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c new file mode 100644 index 000000000..f93a83221 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c new file mode 100644 index 000000000..fdc99171a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c new file mode 100644 index 000000000..49fe47812 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c new file mode 100644 index 000000000..2f6ac31a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c new file mode 100644 index 000000000..3c279b4ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c new file mode 100644 index 000000000..c525a85d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c new file mode 100644 index 000000000..975dfa37c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c new file mode 100644 index 000000000..15364b77c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c @@ -0,0 +1,21 @@ +/* Test the `vaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c new file mode 100644 index 000000000..d39d14a27 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c new file mode 100644 index 000000000..52d622164 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c new file mode 100644 index 000000000..cb593a2ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c new file mode 100644 index 000000000..59d311fa0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c new file mode 100644 index 000000000..570b8855b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c new file mode 100644 index 000000000..2156254e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c new file mode 100644 index 000000000..0ee3e4908 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c @@ -0,0 +1,21 @@ +/* Test the `vaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c new file mode 100644 index 000000000..3cd0978cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c @@ -0,0 +1,21 @@ +/* Test the `vaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c new file mode 100644 index 000000000..50e5197ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c @@ -0,0 +1,21 @@ +/* Test the `vaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c new file mode 100644 index 000000000..671fc9250 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c new file mode 100644 index 000000000..5a69ba320 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c new file mode 100644 index 000000000..723b45e80 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c new file mode 100644 index 000000000..4f2250e8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c @@ -0,0 +1,21 @@ +/* Test the `vadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c new file mode 100644 index 000000000..bc030289d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c @@ -0,0 +1,21 @@ +/* Test the `vadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c new file mode 100644 index 000000000..fb17e0ea3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c @@ -0,0 +1,20 @@ +/* Test the `vadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c new file mode 100644 index 000000000..e928b1250 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c @@ -0,0 +1,21 @@ +/* Test the `vadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c new file mode 100644 index 000000000..9564df38e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c new file mode 100644 index 000000000..2bc009e3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c new file mode 100644 index 000000000..18fc500b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c @@ -0,0 +1,20 @@ +/* Test the `vaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c new file mode 100644 index 000000000..625931b3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c new file mode 100644 index 000000000..b99025334 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c @@ -0,0 +1,21 @@ +/* Test the `vaddws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c new file mode 100644 index 000000000..447b8919b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c @@ -0,0 +1,21 @@ +/* Test the `vaddws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c new file mode 100644 index 000000000..f604c1ebf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c @@ -0,0 +1,21 @@ +/* Test the `vaddws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c new file mode 100644 index 000000000..f374bef96 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c new file mode 100644 index 000000000..211f79897 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c new file mode 100644 index 000000000..ae9601608 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c new file mode 100644 index 000000000..87c030442 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c @@ -0,0 +1,21 @@ +/* Test the `vandQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c new file mode 100644 index 000000000..3ae1a5218 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c @@ -0,0 +1,21 @@ +/* Test the `vandQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c new file mode 100644 index 000000000..cca486875 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c @@ -0,0 +1,21 @@ +/* Test the `vandQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c new file mode 100644 index 000000000..4d0ce17cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c @@ -0,0 +1,21 @@ +/* Test the `vandQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c new file mode 100644 index 000000000..ff7d646a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c @@ -0,0 +1,21 @@ +/* Test the `vandQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c new file mode 100644 index 000000000..a99a525b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c @@ -0,0 +1,21 @@ +/* Test the `vandQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c new file mode 100644 index 000000000..2484dd04c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c @@ -0,0 +1,21 @@ +/* Test the `vandQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c new file mode 100644 index 000000000..c20979fcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c @@ -0,0 +1,21 @@ +/* Test the `vandQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c new file mode 100644 index 000000000..dbb2c622f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c @@ -0,0 +1,21 @@ +/* Test the `vands16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c new file mode 100644 index 000000000..61c0c4113 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c @@ -0,0 +1,21 @@ +/* Test the `vands32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c new file mode 100644 index 000000000..13e18fb0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c @@ -0,0 +1,20 @@ +/* Test the `vands64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c new file mode 100644 index 000000000..526a50072 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c @@ -0,0 +1,21 @@ +/* Test the `vands8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c new file mode 100644 index 000000000..5c998856f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c @@ -0,0 +1,21 @@ +/* Test the `vandu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c new file mode 100644 index 000000000..8a936e673 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c @@ -0,0 +1,21 @@ +/* Test the `vandu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c new file mode 100644 index 000000000..d9ddf847a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c @@ -0,0 +1,20 @@ +/* Test the `vandu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c new file mode 100644 index 000000000..728c5a6d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c @@ -0,0 +1,21 @@ +/* Test the `vandu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c new file mode 100644 index 000000000..e15a260ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c new file mode 100644 index 000000000..f376bf077 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c new file mode 100644 index 000000000..87049f129 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c new file mode 100644 index 000000000..4f64e8817 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c new file mode 100644 index 000000000..f92f9b384 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c new file mode 100644 index 000000000..06d10da23 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c new file mode 100644 index 000000000..7cd63c035 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c new file mode 100644 index 000000000..3f44418d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c new file mode 100644 index 000000000..943e30534 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c @@ -0,0 +1,21 @@ +/* Test the `vbics16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c new file mode 100644 index 000000000..30df639e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c @@ -0,0 +1,21 @@ +/* Test the `vbics32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c new file mode 100644 index 000000000..379db45f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c @@ -0,0 +1,20 @@ +/* Test the `vbics64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c new file mode 100644 index 000000000..3b4bc8a8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c @@ -0,0 +1,21 @@ +/* Test the `vbics8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c new file mode 100644 index 000000000..e9952bc52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c @@ -0,0 +1,21 @@ +/* Test the `vbicu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c new file mode 100644 index 000000000..9334f403f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c @@ -0,0 +1,21 @@ +/* Test the `vbicu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c new file mode 100644 index 000000000..c276d65eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c @@ -0,0 +1,20 @@ +/* Test the `vbicu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c new file mode 100644 index 000000000..5e42c5237 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c @@ -0,0 +1,21 @@ +/* Test the `vbicu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c new file mode 100644 index 000000000..33bc0257e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQf32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c new file mode 100644 index 000000000..06db6555d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQp16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + poly16x8_t arg1_poly16x8_t; + poly16x8_t arg2_poly16x8_t; + + out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c new file mode 100644 index 000000000..519ee370d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vbslQp64 (void) +{ + poly64x2_t out_poly64x2_t; + uint64x2_t arg0_uint64x2_t; + poly64x2_t arg1_poly64x2_t; + poly64x2_t arg2_poly64x2_t; + + out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c new file mode 100644 index 000000000..52d498b8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQp8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + poly8x16_t arg1_poly8x16_t; + poly8x16_t arg2_poly8x16_t; + + out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c new file mode 100644 index 000000000..f8f090f52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c new file mode 100644 index 000000000..194ecdb35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c new file mode 100644 index 000000000..cba963da0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + int64x2_t arg2_int64x2_t; + + out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c new file mode 100644 index 000000000..fe8a64c5d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c new file mode 100644 index 000000000..121ce1edc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c new file mode 100644 index 000000000..dc213f1a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c new file mode 100644 index 000000000..6635e652f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + uint64x2_t arg2_uint64x2_t; + + out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c new file mode 100644 index 000000000..0fc6eb820 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c new file mode 100644 index 000000000..ea8750da5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c @@ -0,0 +1,22 @@ +/* Test the `vbslf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslf32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c new file mode 100644 index 000000000..632fea22f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c @@ -0,0 +1,22 @@ +/* Test the `vbslp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslp16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + poly16x4_t arg1_poly16x4_t; + poly16x4_t arg2_poly16x4_t; + + out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c new file mode 100644 index 000000000..51929274d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c @@ -0,0 +1,22 @@ +/* Test the `vbslp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vbslp64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64x1_t arg0_uint64x1_t; + poly64x1_t arg1_poly64x1_t; + poly64x1_t arg2_poly64x1_t; + + out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c new file mode 100644 index 000000000..a867a3b12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c @@ -0,0 +1,22 @@ +/* Test the `vbslp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslp8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + poly8x8_t arg1_poly8x8_t; + poly8x8_t arg2_poly8x8_t; + + out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c new file mode 100644 index 000000000..849b8ff85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c @@ -0,0 +1,22 @@ +/* Test the `vbsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c new file mode 100644 index 000000000..734560180 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c @@ -0,0 +1,22 @@ +/* Test the `vbsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c new file mode 100644 index 000000000..79516cd89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c @@ -0,0 +1,22 @@ +/* Test the `vbsls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + int64x1_t arg2_int64x1_t; + + out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c new file mode 100644 index 000000000..7cfd379b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c @@ -0,0 +1,22 @@ +/* Test the `vbsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c new file mode 100644 index 000000000..aef15fa6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c @@ -0,0 +1,22 @@ +/* Test the `vbslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c new file mode 100644 index 000000000..e04e349ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c @@ -0,0 +1,22 @@ +/* Test the `vbslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c new file mode 100644 index 000000000..a4a53af2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c @@ -0,0 +1,22 @@ +/* Test the `vbslu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + uint64x1_t arg2_uint64x1_t; + + out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c new file mode 100644 index 000000000..154ea961d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c @@ -0,0 +1,22 @@ +/* Test the `vbslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c new file mode 100644 index 000000000..8b5995525 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcageQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcageQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c new file mode 100644 index 000000000..0d45e320e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c @@ -0,0 +1,21 @@ +/* Test the `vcagef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c new file mode 100644 index 000000000..cef77b38c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcagtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c new file mode 100644 index 000000000..89b875927 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c @@ -0,0 +1,21 @@ +/* Test the `vcagtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c new file mode 100644 index 000000000..8cfef154d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c new file mode 100644 index 000000000..1101fde68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c @@ -0,0 +1,21 @@ +/* Test the `vcalef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcalef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c new file mode 100644 index 000000000..1d2cf7445 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c new file mode 100644 index 000000000..6a8a8171e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c new file mode 100644 index 000000000..14ad3e7dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c new file mode 100644 index 000000000..80a8f6233 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c new file mode 100644 index 000000000..843bfe0ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c new file mode 100644 index 000000000..f25faa5ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c new file mode 100644 index 000000000..77bda24d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c new file mode 100644 index 000000000..c6293f285 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c new file mode 100644 index 000000000..7090033be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c new file mode 100644 index 000000000..3ff24d546 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c new file mode 100644 index 000000000..b150b32c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c @@ -0,0 +1,21 @@ +/* Test the `vceqf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c new file mode 100644 index 000000000..2e4e608d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c @@ -0,0 +1,21 @@ +/* Test the `vceqp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c new file mode 100644 index 000000000..3cf450228 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c @@ -0,0 +1,21 @@ +/* Test the `vceqs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c new file mode 100644 index 000000000..989484130 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c @@ -0,0 +1,21 @@ +/* Test the `vceqs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c new file mode 100644 index 000000000..825214ae4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c @@ -0,0 +1,21 @@ +/* Test the `vceqs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c new file mode 100644 index 000000000..b7dd5450d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c @@ -0,0 +1,21 @@ +/* Test the `vcequ16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c new file mode 100644 index 000000000..7864cfdf8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c @@ -0,0 +1,21 @@ +/* Test the `vcequ32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c new file mode 100644 index 000000000..8b8b26fba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c @@ -0,0 +1,21 @@ +/* Test the `vcequ8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c new file mode 100644 index 000000000..b0eb53cfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c new file mode 100644 index 000000000..2ef989ac1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c new file mode 100644 index 000000000..2bef01abb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c new file mode 100644 index 000000000..15083d35e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c new file mode 100644 index 000000000..59c609b65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c new file mode 100644 index 000000000..fa4d67cf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c new file mode 100644 index 000000000..39dee295c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c new file mode 100644 index 000000000..797f43f6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c @@ -0,0 +1,21 @@ +/* Test the `vcgef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c new file mode 100644 index 000000000..52984c796 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c @@ -0,0 +1,21 @@ +/* Test the `vcges16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c new file mode 100644 index 000000000..935bde799 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c @@ -0,0 +1,21 @@ +/* Test the `vcges32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c new file mode 100644 index 000000000..15abad3fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c @@ -0,0 +1,21 @@ +/* Test the `vcges8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c new file mode 100644 index 000000000..ec96ebc74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c new file mode 100644 index 000000000..12c67bf7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c new file mode 100644 index 000000000..5457b91a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c new file mode 100644 index 000000000..9f6e6dc2d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c new file mode 100644 index 000000000..b733e6ffa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c new file mode 100644 index 000000000..eae07ad12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c new file mode 100644 index 000000000..2f82a9539 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c new file mode 100644 index 000000000..080a7af7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c new file mode 100644 index 000000000..0dfb361b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c new file mode 100644 index 000000000..0643e22e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c new file mode 100644 index 000000000..833bf1f55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c new file mode 100644 index 000000000..141df1061 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c @@ -0,0 +1,21 @@ +/* Test the `vcgts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c new file mode 100644 index 000000000..6350041d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c @@ -0,0 +1,21 @@ +/* Test the `vcgts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c new file mode 100644 index 000000000..1ad43968a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c @@ -0,0 +1,21 @@ +/* Test the `vcgts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c new file mode 100644 index 000000000..e3b2c80c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c new file mode 100644 index 000000000..60e6a9f1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c new file mode 100644 index 000000000..858647548 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c new file mode 100644 index 000000000..770da7b04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c new file mode 100644 index 000000000..f4f69e2b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c new file mode 100644 index 000000000..49d6cc0f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c new file mode 100644 index 000000000..32447e67a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c new file mode 100644 index 000000000..3c8ae5217 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c new file mode 100644 index 000000000..e2556e38e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c new file mode 100644 index 000000000..48e3ee239 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c new file mode 100644 index 000000000..88fa76483 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c @@ -0,0 +1,21 @@ +/* Test the `vclef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c new file mode 100644 index 000000000..885c5d510 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c @@ -0,0 +1,21 @@ +/* Test the `vcles16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c new file mode 100644 index 000000000..5bbd0d2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c @@ -0,0 +1,21 @@ +/* Test the `vcles32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c new file mode 100644 index 000000000..e247608db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c @@ -0,0 +1,21 @@ +/* Test the `vcles8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c new file mode 100644 index 000000000..6fcacbadd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c @@ -0,0 +1,21 @@ +/* Test the `vcleu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c new file mode 100644 index 000000000..568f56f99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c @@ -0,0 +1,21 @@ +/* Test the `vcleu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c new file mode 100644 index 000000000..81884bf72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c @@ -0,0 +1,21 @@ +/* Test the `vcleu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c new file mode 100644 index 000000000..22009dce0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c new file mode 100644 index 000000000..a4e2d70c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c new file mode 100644 index 000000000..91394e198 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c new file mode 100644 index 000000000..c98508412 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c @@ -0,0 +1,20 @@ +/* Test the `vclss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vcls_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c new file mode 100644 index 000000000..4f3e16f88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c @@ -0,0 +1,20 @@ +/* Test the `vclss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vcls_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c new file mode 100644 index 000000000..3c363745f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c @@ -0,0 +1,20 @@ +/* Test the `vclss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcls_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c new file mode 100644 index 000000000..1616849a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c new file mode 100644 index 000000000..794d2c4b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c new file mode 100644 index 000000000..871519b14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c new file mode 100644 index 000000000..41d32111f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c new file mode 100644 index 000000000..209bc3d0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c new file mode 100644 index 000000000..797c62a81 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c new file mode 100644 index 000000000..5a067fedf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c new file mode 100644 index 000000000..82ef84fb6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c @@ -0,0 +1,21 @@ +/* Test the `vcltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c new file mode 100644 index 000000000..b6aaeabb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c @@ -0,0 +1,21 @@ +/* Test the `vclts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c new file mode 100644 index 000000000..cb66ca98e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c @@ -0,0 +1,21 @@ +/* Test the `vclts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c new file mode 100644 index 000000000..60bbf636c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c @@ -0,0 +1,21 @@ +/* Test the `vclts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c new file mode 100644 index 000000000..e5d2918cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c @@ -0,0 +1,21 @@ +/* Test the `vcltu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c new file mode 100644 index 000000000..936e6b867 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c @@ -0,0 +1,21 @@ +/* Test the `vcltu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c new file mode 100644 index 000000000..ab73e1f18 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c @@ -0,0 +1,21 @@ +/* Test the `vcltu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c new file mode 100644 index 000000000..24df7b676 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclzq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c new file mode 100644 index 000000000..1e01ee9e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclzq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c new file mode 100644 index 000000000..80e40fd86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclzq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c new file mode 100644 index 000000000..2b023fa24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c new file mode 100644 index 000000000..529cbcf58 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c new file mode 100644 index 000000000..2be4915ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c new file mode 100644 index 000000000..b024559f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c @@ -0,0 +1,20 @@ +/* Test the `vclzs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vclz_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c new file mode 100644 index 000000000..b01e429c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c @@ -0,0 +1,20 @@ +/* Test the `vclzs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vclz_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c new file mode 100644 index 000000000..b23be0c1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c @@ -0,0 +1,20 @@ +/* Test the `vclzs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vclz_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c new file mode 100644 index 000000000..4f2516326 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c @@ -0,0 +1,20 @@ +/* Test the `vclzu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c new file mode 100644 index 000000000..4dd898345 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c @@ -0,0 +1,20 @@ +/* Test the `vclzu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c new file mode 100644 index 000000000..4bfe49878 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c @@ -0,0 +1,20 @@ +/* Test the `vclzu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c new file mode 100644 index 000000000..15a4f7154 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c new file mode 100644 index 000000000..fb6511903 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vcntq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c new file mode 100644 index 000000000..dea80786b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c new file mode 100644 index 000000000..39e0d1100 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c @@ -0,0 +1,20 @@ +/* Test the `vcntp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c new file mode 100644 index 000000000..89ae7b7b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c @@ -0,0 +1,20 @@ +/* Test the `vcnts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcnts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcnt_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c new file mode 100644 index 000000000..9a5f2f045 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c @@ -0,0 +1,20 @@ +/* Test the `vcntu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c new file mode 100644 index 000000000..a177288dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c @@ -0,0 +1,20 @@ +/* Test the `vcombinef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c new file mode 100644 index 000000000..79b4440b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c new file mode 100644 index 000000000..d5e156bdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vcombinep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c new file mode 100644 index 000000000..0fa1af6df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c new file mode 100644 index 000000000..9799f99b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c @@ -0,0 +1,20 @@ +/* Test the `vcombines16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c new file mode 100644 index 000000000..d68676c3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c @@ -0,0 +1,20 @@ +/* Test the `vcombines32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c new file mode 100644 index 000000000..389941540 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c @@ -0,0 +1,20 @@ +/* Test the `vcombines64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c new file mode 100644 index 000000000..b3c8d3a7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c @@ -0,0 +1,20 @@ +/* Test the `vcombines8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c new file mode 100644 index 000000000..f35528b6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c new file mode 100644 index 000000000..9c10e8597 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c new file mode 100644 index 000000000..fac517b48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c new file mode 100644 index 000000000..808a9f299 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c new file mode 100644 index 000000000..68fe67e50 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c @@ -0,0 +1,19 @@ +/* Test the `vcreatef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatef32 (void) +{ + float32x2_t out_float32x2_t; + uint64_t arg0_uint64_t; + + out_float32x2_t = vcreate_f32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c new file mode 100644 index 000000000..b02247259 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatep16 (void) +{ + poly16x4_t out_poly16x4_t; + uint64_t arg0_uint64_t; + + out_poly16x4_t = vcreate_p16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c new file mode 100644 index 000000000..7aedb73fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vcreatep64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64_t arg0_uint64_t; + + out_poly64x1_t = vcreate_p64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c new file mode 100644 index 000000000..7a3f607dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatep8 (void) +{ + poly8x8_t out_poly8x8_t; + uint64_t arg0_uint64_t; + + out_poly8x8_t = vcreate_p8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c new file mode 100644 index 000000000..2adfeb31e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c @@ -0,0 +1,19 @@ +/* Test the `vcreates16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates16 (void) +{ + int16x4_t out_int16x4_t; + uint64_t arg0_uint64_t; + + out_int16x4_t = vcreate_s16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c new file mode 100644 index 000000000..4212dcba5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c @@ -0,0 +1,19 @@ +/* Test the `vcreates32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates32 (void) +{ + int32x2_t out_int32x2_t; + uint64_t arg0_uint64_t; + + out_int32x2_t = vcreate_s32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c new file mode 100644 index 000000000..77e4a51b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c @@ -0,0 +1,19 @@ +/* Test the `vcreates64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates64 (void) +{ + int64x1_t out_int64x1_t; + uint64_t arg0_uint64_t; + + out_int64x1_t = vcreate_s64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c new file mode 100644 index 000000000..0c0d546aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c @@ -0,0 +1,19 @@ +/* Test the `vcreates8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates8 (void) +{ + int8x8_t out_int8x8_t; + uint64_t arg0_uint64_t; + + out_int8x8_t = vcreate_s8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c new file mode 100644 index 000000000..d8004802b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint64_t arg0_uint64_t; + + out_uint16x4_t = vcreate_u16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c new file mode 100644 index 000000000..42d72adc3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint64_t arg0_uint64_t; + + out_uint32x2_t = vcreate_u32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c new file mode 100644 index 000000000..5b0b37865 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vcreate_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c new file mode 100644 index 000000000..ea4114617 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint64_t arg0_uint64_t; + + out_uint8x8_t = vcreate_u8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c new file mode 100644 index 000000000..85916e770 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c new file mode 100644 index 000000000..ab20ff0ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c new file mode 100644 index 000000000..76ce86a0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_ns32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c new file mode 100644 index 000000000..16de37fe1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c new file mode 100644 index 000000000..1160edeab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c new file mode 100644 index 000000000..285e1dd89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c new file mode 100644 index 000000000..562137430 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c new file mode 100644 index 000000000..f2ea8f541 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c new file mode 100644 index 000000000..403fe621c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c new file mode 100644 index 000000000..dc344a3ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c new file mode 100644 index 000000000..b50b20e01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_ns32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c new file mode 100644 index 000000000..b003f0097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c new file mode 100644 index 000000000..6675596d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vcvtf16_f32 (void) +{ + float16x4_t out_float16x4_t; + float32x4_t arg0_float32x4_t; + + out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f16.f32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c new file mode 100644 index 000000000..dd0ce1702 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_f16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vcvtf32_f16 (void) +{ + float32x4_t out_float32x4_t; + float16x4_t arg0_float16x4_t; + + out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.f16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c new file mode 100644 index 000000000..e0ca9b062 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c new file mode 100644 index 000000000..b3b44bedf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c new file mode 100644 index 000000000..b626fbf74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvts32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvts32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c new file mode 100644 index 000000000..8c86d47af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c new file mode 100644 index 000000000..8593d871a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + + out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c new file mode 100644 index 000000000..b48966b76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c new file mode 100644 index 000000000..6211413c7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x1_t arg0_poly64x1_t; + + out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c new file mode 100644 index 000000000..ebe7a0da5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c new file mode 100644 index 000000000..dae7cb568 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + + out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c new file mode 100644 index 000000000..4ef5cb789 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + + out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c new file mode 100644 index 000000000..9c41050e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + + out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c new file mode 100644 index 000000000..428dfc404 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + + out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c new file mode 100644 index 000000000..840e6e2b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c new file mode 100644 index 000000000..76f3c756f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c new file mode 100644 index 000000000..8a6487135 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c new file mode 100644 index 000000000..c4886e62d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c new file mode 100644 index 000000000..5f7305aca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vdupq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c new file mode 100644 index 000000000..bd73329cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c new file mode 100644 index 000000000..68a1d746b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdupQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64_t arg0_poly64_t; + + out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c new file mode 100644 index 000000000..7c90d560d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c new file mode 100644 index 000000000..de837d919 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vdupq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c new file mode 100644 index 000000000..00f175cec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vdupq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c new file mode 100644 index 000000000..ab749a7bb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c new file mode 100644 index 000000000..3794d6eb1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vdupq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c new file mode 100644 index 000000000..fed6ea227 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c new file mode 100644 index 000000000..5b96fbcdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c new file mode 100644 index 000000000..0ddb72dec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c new file mode 100644 index 000000000..a490472fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c new file mode 100644 index 000000000..495f189bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c new file mode 100644 index 000000000..f951fac35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c new file mode 100644 index 000000000..ab263f170 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdup_lanep64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c new file mode 100644 index 000000000..dad99e4fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c new file mode 100644 index 000000000..046d440ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c new file mode 100644 index 000000000..f249a626a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c new file mode 100644 index 000000000..628140fd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c new file mode 100644 index 000000000..9ca250152 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c new file mode 100644 index 000000000..1b3dd02a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c new file mode 100644 index 000000000..520757873 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c new file mode 100644 index 000000000..a9de614c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c new file mode 100644 index 000000000..5687c0b47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c new file mode 100644 index 000000000..ba99fdce5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vdup_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c new file mode 100644 index 000000000..55bca29b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c new file mode 100644 index 000000000..3b6b7ec31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdup_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64_t arg0_poly64_t; + + out_poly64x1_t = vdup_n_p64 (arg0_poly64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c new file mode 100644 index 000000000..80d29e860 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c new file mode 100644 index 000000000..4d1ea6a6e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vdup_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c new file mode 100644 index 000000000..9fb1fc289 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vdup_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c new file mode 100644 index 000000000..033f1b474 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vdup_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c new file mode 100644 index 000000000..eba462c79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vdup_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c new file mode 100644 index 000000000..24015e592 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c new file mode 100644 index 000000000..78374d42a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c new file mode 100644 index 000000000..6888125c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c new file mode 100644 index 000000000..ee35ff37b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c new file mode 100644 index 000000000..f31d9bfab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c new file mode 100644 index 000000000..f3f01c65e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c new file mode 100644 index 000000000..a0428bee7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c @@ -0,0 +1,21 @@ +/* Test the `veorQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c new file mode 100644 index 000000000..7b24ea477 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c @@ -0,0 +1,21 @@ +/* Test the `veorQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c new file mode 100644 index 000000000..fd023171a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c @@ -0,0 +1,21 @@ +/* Test the `veorQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c new file mode 100644 index 000000000..17da85c6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c @@ -0,0 +1,21 @@ +/* Test the `veorQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c new file mode 100644 index 000000000..d2865e9fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c @@ -0,0 +1,21 @@ +/* Test the `veorQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c new file mode 100644 index 000000000..76370677d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c @@ -0,0 +1,21 @@ +/* Test the `veorQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c new file mode 100644 index 000000000..156b07b34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c @@ -0,0 +1,21 @@ +/* Test the `veorQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c new file mode 100644 index 000000000..b3ff98343 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c @@ -0,0 +1,21 @@ +/* Test the `veorQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c new file mode 100644 index 000000000..8af437edf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c @@ -0,0 +1,21 @@ +/* Test the `veors16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c new file mode 100644 index 000000000..105780393 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c @@ -0,0 +1,21 @@ +/* Test the `veors32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c new file mode 100644 index 000000000..2781be1b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c @@ -0,0 +1,20 @@ +/* Test the `veors64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c new file mode 100644 index 000000000..cda05c7e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c @@ -0,0 +1,21 @@ +/* Test the `veors8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c new file mode 100644 index 000000000..d89d87302 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c @@ -0,0 +1,21 @@ +/* Test the `veoru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c new file mode 100644 index 000000000..7804a8c16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c @@ -0,0 +1,21 @@ +/* Test the `veoru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c new file mode 100644 index 000000000..19d081489 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c @@ -0,0 +1,20 @@ +/* Test the `veoru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c new file mode 100644 index 000000000..aad32de44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c @@ -0,0 +1,21 @@ +/* Test the `veoru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c new file mode 100644 index 000000000..92597f9bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c @@ -0,0 +1,21 @@ +/* Test the `vextQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c new file mode 100644 index 000000000..546da6990 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c @@ -0,0 +1,21 @@ +/* Test the `vextQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c new file mode 100644 index 000000000..bc5e08aa7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c @@ -0,0 +1,21 @@ +/* Test the `vextQp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vextQp64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c new file mode 100644 index 000000000..f9273c2d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c @@ -0,0 +1,21 @@ +/* Test the `vextQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c new file mode 100644 index 000000000..d95ff2976 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c @@ -0,0 +1,21 @@ +/* Test the `vextQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c new file mode 100644 index 000000000..b6824ff6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c @@ -0,0 +1,21 @@ +/* Test the `vextQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c new file mode 100644 index 000000000..226aa207f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c @@ -0,0 +1,21 @@ +/* Test the `vextQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c new file mode 100644 index 000000000..274279a2d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c @@ -0,0 +1,21 @@ +/* Test the `vextQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c new file mode 100644 index 000000000..36fcb5273 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c @@ -0,0 +1,21 @@ +/* Test the `vextQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c new file mode 100644 index 000000000..082592a0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c @@ -0,0 +1,21 @@ +/* Test the `vextQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c new file mode 100644 index 000000000..ac496db0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c @@ -0,0 +1,21 @@ +/* Test the `vextQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c new file mode 100644 index 000000000..e77b9a2e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c @@ -0,0 +1,21 @@ +/* Test the `vextQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c new file mode 100644 index 000000000..5f7ef947c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c @@ -0,0 +1,21 @@ +/* Test the `vextf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c new file mode 100644 index 000000000..f1e176efb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c @@ -0,0 +1,21 @@ +/* Test the `vextp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c new file mode 100644 index 000000000..aa1e91f59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c @@ -0,0 +1,21 @@ +/* Test the `vextp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vextp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c new file mode 100644 index 000000000..feb2fdd07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c @@ -0,0 +1,21 @@ +/* Test the `vextp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c new file mode 100644 index 000000000..1d3eb7980 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c @@ -0,0 +1,21 @@ +/* Test the `vexts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c new file mode 100644 index 000000000..e83a0de6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c @@ -0,0 +1,21 @@ +/* Test the `vexts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c new file mode 100644 index 000000000..e594beca5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c @@ -0,0 +1,21 @@ +/* Test the `vexts64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c new file mode 100644 index 000000000..0575bd349 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c @@ -0,0 +1,21 @@ +/* Test the `vexts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c new file mode 100644 index 000000000..b94afdf61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c @@ -0,0 +1,21 @@ +/* Test the `vextu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c new file mode 100644 index 000000000..39bdf31ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c @@ -0,0 +1,21 @@ +/* Test the `vextu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c new file mode 100644 index 000000000..17afbd751 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c @@ -0,0 +1,21 @@ +/* Test the `vextu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c new file mode 100644 index 000000000..5176a7201 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c @@ -0,0 +1,21 @@ +/* Test the `vextu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c new file mode 100644 index 000000000..d400163a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmaQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmaQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c new file mode 100644 index 000000000..988328dd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c new file mode 100644 index 000000000..247a8edfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c new file mode 100644 index 000000000..7f9e8570d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c new file mode 100644 index 000000000..5c772c04c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c @@ -0,0 +1,28 @@ +/* Check that NEON vector shifts support immediate values == size. /* + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t test_vshll_n_u8 (uint8x8_t a) +{ + return vshll_n_u8(a, 8); +} + +uint32x4_t test_vshll_n_u16 (uint16x4_t a) +{ + return vshll_n_u16(a, 16); +} + +uint64x2_t test_vshll_n_u32 (uint32x2_t a) +{ + return vshll_n_u32(a, 32); +} + +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c new file mode 100644 index 000000000..54e04c50a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanef32 (void) +{ + float32_t out_float32_t; + float32x4_t arg0_float32x4_t; + + out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c new file mode 100644 index 000000000..cfb5447bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c new file mode 100644 index 000000000..7325dd744 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c new file mode 100644 index 000000000..f992d17a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes16 (void) +{ + int16_t out_int16_t; + int16x8_t arg0_int16x8_t; + + out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c new file mode 100644 index 000000000..36cb88ff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes32 (void) +{ + int32_t out_int32_t; + int32x4_t arg0_int32x4_t; + + out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c new file mode 100644 index 000000000..e3d3c178e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes64 (void) +{ + register int64_t out_int64_t asm ("r0"); + int64x2_t arg0_int64x2_t; + + out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c new file mode 100644 index 000000000..7ce2cc651 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes8 (void) +{ + int8_t out_int8_t; + int8x16_t arg0_int8x16_t; + + out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c new file mode 100644 index 000000000..d44f05f2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c new file mode 100644 index 000000000..3004f503c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c new file mode 100644 index 000000000..3426e4694 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu64 (void) +{ + register uint64_t out_uint64_t asm ("r0"); + uint64x2_t arg0_uint64x2_t; + + out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c new file mode 100644 index 000000000..57528f2f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c new file mode 100644 index 000000000..60f935e97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highf32 (void) +{ + float32x2_t out_float32x2_t; + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_high_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c new file mode 100644 index 000000000..660b83e34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c new file mode 100644 index 000000000..f2b1b7a9e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vget_highp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x2_t arg0_poly64x2_t; + + out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c new file mode 100644 index 000000000..e9519606e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c new file mode 100644 index 000000000..ca4e7706e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs16 (void) +{ + int16x4_t out_int16x4_t; + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_high_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c new file mode 100644 index 000000000..77ead1ac8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs32 (void) +{ + int32x2_t out_int32x2_t; + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_high_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c new file mode 100644 index 000000000..cb6a48480 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_high_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c new file mode 100644 index 000000000..ec249f823 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs8 (void) +{ + int8x8_t out_int8x8_t; + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_high_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c new file mode 100644 index 000000000..263a920aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c new file mode 100644 index 000000000..4797a132e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c new file mode 100644 index 000000000..899309f1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c new file mode 100644 index 000000000..a0c689736 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c new file mode 100644 index 000000000..908adeb70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanef32 (void) +{ + float32_t out_float32_t; + float32x2_t arg0_float32x2_t; + + out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c new file mode 100644 index 000000000..0dcf90b57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c new file mode 100644 index 000000000..22b06bdf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c new file mode 100644 index 000000000..4a86bf465 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes16 (void) +{ + int16_t out_int16_t; + int16x4_t arg0_int16x4_t; + + out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c new file mode 100644 index 000000000..8559da7ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes32 (void) +{ + int32_t out_int32_t; + int32x2_t arg0_int32x2_t; + + out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c new file mode 100644 index 000000000..5dc99424f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes64 (void) +{ + int64_t out_int64_t; + int64x1_t arg0_int64x1_t; + + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c new file mode 100644 index 000000000..be6110408 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes8 (void) +{ + int8_t out_int8_t; + int8x8_t arg0_int8x8_t; + + out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c new file mode 100644 index 000000000..66f645e32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c new file mode 100644 index 000000000..b19de8d28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c new file mode 100644 index 000000000..496a057fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu64 (void) +{ + uint64_t out_uint64_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c new file mode 100644 index 000000000..1affae83a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c new file mode 100644 index 000000000..81982d438 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowf32 (void) +{ + register float32x2_t out_float32x2_t asm ("d18"); + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_low_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c new file mode 100644 index 000000000..395461196 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowp16 (void) +{ + register poly16x4_t out_poly16x4_t asm ("d18"); + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c new file mode 100644 index 000000000..94cd3a8ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vget_lowp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x2_t arg0_poly64x2_t; + + out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c new file mode 100644 index 000000000..e4bf2f1d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowp8 (void) +{ + register poly8x8_t out_poly8x8_t asm ("d18"); + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c new file mode 100644 index 000000000..d2a07c63e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows16 (void) +{ + register int16x4_t out_int16x4_t asm ("d18"); + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_low_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c new file mode 100644 index 000000000..4278e2bcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows32 (void) +{ + register int32x2_t out_int32x2_t asm ("d18"); + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_low_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c new file mode 100644 index 000000000..53d26e7e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_low_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c new file mode 100644 index 000000000..a4ad63371 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows8 (void) +{ + register int8x8_t out_int8x8_t asm ("d18"); + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_low_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c new file mode 100644 index 000000000..c9e0a51a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu16 (void) +{ + register uint16x4_t out_uint16x4_t asm ("d18"); + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c new file mode 100644 index 000000000..841a619cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu32 (void) +{ + register uint32x2_t out_uint32x2_t asm ("d18"); + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c new file mode 100644 index 000000000..ab2b42c2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c new file mode 100644 index 000000000..fd2537bbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu8 (void) +{ + register uint8x8_t out_uint8x8_t asm ("d18"); + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c new file mode 100644 index 000000000..2bd30cd1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c new file mode 100644 index 000000000..04bbf03bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c new file mode 100644 index 000000000..86c3db518 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c new file mode 100644 index 000000000..75aae10e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c new file mode 100644 index 000000000..c7ec45a2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c new file mode 100644 index 000000000..8668d141b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c new file mode 100644 index 000000000..61344cff5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c @@ -0,0 +1,21 @@ +/* Test the `vhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c new file mode 100644 index 000000000..03d090292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c @@ -0,0 +1,21 @@ +/* Test the `vhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c new file mode 100644 index 000000000..90e79daa7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c @@ -0,0 +1,21 @@ +/* Test the `vhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c new file mode 100644 index 000000000..971778b78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c new file mode 100644 index 000000000..70865fad0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c new file mode 100644 index 000000000..b541b87d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c new file mode 100644 index 000000000..5647c6297 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c new file mode 100644 index 000000000..44e780e01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c new file mode 100644 index 000000000..8162a1014 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c new file mode 100644 index 000000000..1a84876ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c new file mode 100644 index 000000000..ae52afd29 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c new file mode 100644 index 000000000..ef43a4f3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c new file mode 100644 index 000000000..786c8d389 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c new file mode 100644 index 000000000..4c7e9c8b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c new file mode 100644 index 000000000..c8c1ada08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c new file mode 100644 index 000000000..bf83c7ce0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c new file mode 100644 index 000000000..f224eaf07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c new file mode 100644 index 000000000..fe145a9b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c new file mode 100644 index 000000000..fa9cf20f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c new file mode 100644 index 000000000..4e8303825 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c new file mode 100644 index 000000000..2d504c163 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp64 (void) +{ + poly64x2_t out_poly64x2_t; + + out_poly64x2_t = vld1q_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c new file mode 100644 index 000000000..70fb89885 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c new file mode 100644 index 000000000..1fedcf94d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c new file mode 100644 index 000000000..2abd4e447 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c new file mode 100644 index 000000000..4fceee82e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c new file mode 100644 index 000000000..e431a5cf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c new file mode 100644 index 000000000..6da756774 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c new file mode 100644 index 000000000..8e400bd25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c new file mode 100644 index 000000000..ef0a3828c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c new file mode 100644 index 000000000..b1e540d70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c new file mode 100644 index 000000000..8c7689edb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c new file mode 100644 index 000000000..163c2a7a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c new file mode 100644 index 000000000..d19267a4f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c new file mode 100644 index 000000000..7f7a22eba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c new file mode 100644 index 000000000..0d56492c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c new file mode 100644 index 000000000..3c5869fcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c new file mode 100644 index 000000000..154583b67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c new file mode 100644 index 000000000..a6aa3f804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c new file mode 100644 index 000000000..1653dd31c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c new file mode 100644 index 000000000..034e24d52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c new file mode 100644 index 000000000..ff92e91fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c new file mode 100644 index 000000000..be338f187 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c new file mode 100644 index 000000000..d792148d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c new file mode 100644 index 000000000..84bceb557 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c new file mode 100644 index 000000000..99ef87673 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Qp64 (void) +{ + poly64x2_t out_poly64x2_t; + + out_poly64x2_t = vld1q_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c new file mode 100644 index 000000000..e756b1bc7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c new file mode 100644 index 000000000..aaa29e982 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c new file mode 100644 index 000000000..14bc4221e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c new file mode 100644 index 000000000..093aee61a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c new file mode 100644 index 000000000..d4fffd0a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c new file mode 100644 index 000000000..267f7d15b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c new file mode 100644 index 000000000..53ccab0c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c new file mode 100644 index 000000000..56b0dbd3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c new file mode 100644 index 000000000..d68fc89ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c new file mode 100644 index 000000000..6f8435b36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupf32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c new file mode 100644 index 000000000..1287b471b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupp16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c new file mode 100644 index 000000000..f2b05c5d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1_dupp64 (void) +{ + poly64x1_t out_poly64x1_t; + + out_poly64x1_t = vld1_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c new file mode 100644 index 000000000..8fde64553 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupp8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c new file mode 100644 index 000000000..084f89e06 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c new file mode 100644 index 000000000..ba6697a4c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c new file mode 100644 index 000000000..410ee6fcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c new file mode 100644 index 000000000..18b21b527 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c new file mode 100644 index 000000000..1d893cd3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c new file mode 100644 index 000000000..f64084640 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c new file mode 100644 index 000000000..17be90a0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c new file mode 100644 index 000000000..5811f25fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c new file mode 100644 index 000000000..6165897ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c new file mode 100644 index 000000000..feecf1baa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c new file mode 100644 index 000000000..cf09f6cd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1_lanep64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c new file mode 100644 index 000000000..0d1729936 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c new file mode 100644 index 000000000..26272410e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c new file mode 100644 index 000000000..39575d456 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c new file mode 100644 index 000000000..1216405bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c new file mode 100644 index 000000000..7c763fd90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c new file mode 100644 index 000000000..9d2c45ed9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c new file mode 100644 index 000000000..3a7f3eec9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c new file mode 100644 index 000000000..b9e5d2042 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c new file mode 100644 index 000000000..7e4835afe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c new file mode 100644 index 000000000..2d90ac559 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c @@ -0,0 +1,19 @@ +/* Test the `vld1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1f32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c new file mode 100644 index 000000000..62aa89e8a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c @@ -0,0 +1,19 @@ +/* Test the `vld1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1p16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c new file mode 100644 index 000000000..9f182d441 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c @@ -0,0 +1,19 @@ +/* Test the `vld1p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1p64 (void) +{ + poly64x1_t out_poly64x1_t; + + out_poly64x1_t = vld1_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c new file mode 100644 index 000000000..60e47c2d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c @@ -0,0 +1,19 @@ +/* Test the `vld1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1p8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c new file mode 100644 index 000000000..1d4cf525f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c @@ -0,0 +1,19 @@ +/* Test the `vld1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c new file mode 100644 index 000000000..7af67c383 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c @@ -0,0 +1,19 @@ +/* Test the `vld1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c new file mode 100644 index 000000000..dadb9de22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c @@ -0,0 +1,19 @@ +/* Test the `vld1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c new file mode 100644 index 000000000..c27ebcd06 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c @@ -0,0 +1,19 @@ +/* Test the `vld1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c new file mode 100644 index 000000000..f973d6ec5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c @@ -0,0 +1,19 @@ +/* Test the `vld1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c new file mode 100644 index 000000000..4b455b292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c @@ -0,0 +1,19 @@ +/* Test the `vld1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c new file mode 100644 index 000000000..1504215d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c @@ -0,0 +1,19 @@ +/* Test the `vld1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c new file mode 100644 index 000000000..600d03518 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c @@ -0,0 +1,19 @@ +/* Test the `vld1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c new file mode 100644 index 000000000..9afbbecf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanef32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4x2_t arg1_float32x4x2_t; + + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c new file mode 100644 index 000000000..e1b85aad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanep16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8x2_t arg1_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c new file mode 100644 index 000000000..467c02b64 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8x2_t arg1_int16x8x2_t; + + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c new file mode 100644 index 000000000..5f9c4a8b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4x2_t arg1_int32x4x2_t; + + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c new file mode 100644 index 000000000..851572917 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8x2_t arg1_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c new file mode 100644 index 000000000..65ec23a6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4x2_t arg1_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c new file mode 100644 index 000000000..afde42c20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + + out_float32x4x2_t = vld2q_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c new file mode 100644 index 000000000..f74004628 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c new file mode 100644 index 000000000..9e4ff25f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + + out_poly8x16x2_t = vld2q_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c new file mode 100644 index 000000000..97c8a2c5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + + out_int16x8x2_t = vld2q_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c new file mode 100644 index 000000000..cd03e17d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + + out_int32x4x2_t = vld2q_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c new file mode 100644 index 000000000..b33a5a8f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + + out_int8x16x2_t = vld2q_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c new file mode 100644 index 000000000..76169af56 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c new file mode 100644 index 000000000..347e164bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c new file mode 100644 index 000000000..3b738a7ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + + out_uint8x16x2_t = vld2q_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c new file mode 100644 index 000000000..54fbd3da9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c new file mode 100644 index 000000000..b5ec4e227 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c new file mode 100644 index 000000000..0531a732d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld2_dupp64 (void) +{ + poly64x1x2_t out_poly64x1x2_t; + + out_poly64x1x2_t = vld2_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c new file mode 100644 index 000000000..2ad81b53a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c new file mode 100644 index 000000000..43b245d3d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c new file mode 100644 index 000000000..51e4fc8e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c new file mode 100644 index 000000000..644db84ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c new file mode 100644 index 000000000..015923392 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c new file mode 100644 index 000000000..85bbc4681 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c new file mode 100644 index 000000000..3549fde1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c new file mode 100644 index 000000000..a830f8310 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c new file mode 100644 index 000000000..c3763c8f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c new file mode 100644 index 000000000..f60279efd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanef32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2x2_t arg1_float32x2x2_t; + + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c new file mode 100644 index 000000000..0d7f415b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanep16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4x2_t arg1_poly16x4x2_t; + + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c new file mode 100644 index 000000000..8174e7bee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanep8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8x2_t arg1_poly8x8x2_t; + + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c new file mode 100644 index 000000000..5a1eb54bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4x2_t arg1_int16x4x2_t; + + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c new file mode 100644 index 000000000..a663c52ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2x2_t arg1_int32x2x2_t; + + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c new file mode 100644 index 000000000..073ba5417 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8x2_t arg1_int8x8x2_t; + + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c new file mode 100644 index 000000000..7250b562e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4x2_t arg1_uint16x4x2_t; + + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c new file mode 100644 index 000000000..9a46c65d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2x2_t arg1_uint32x2x2_t; + + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c new file mode 100644 index 000000000..ba2007109 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8x2_t arg1_uint8x8x2_t; + + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c new file mode 100644 index 000000000..c790de941 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c @@ -0,0 +1,19 @@ +/* Test the `vld2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2f32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c new file mode 100644 index 000000000..4c4338cfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c @@ -0,0 +1,19 @@ +/* Test the `vld2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2p16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c new file mode 100644 index 000000000..0a39b37f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c @@ -0,0 +1,19 @@ +/* Test the `vld2p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld2p64 (void) +{ + poly64x1x2_t out_poly64x1x2_t; + + out_poly64x1x2_t = vld2_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c new file mode 100644 index 000000000..d319c22e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c @@ -0,0 +1,19 @@ +/* Test the `vld2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2p8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c new file mode 100644 index 000000000..f725d79de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c @@ -0,0 +1,19 @@ +/* Test the `vld2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c new file mode 100644 index 000000000..3f417eeee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c @@ -0,0 +1,19 @@ +/* Test the `vld2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c new file mode 100644 index 000000000..b9900893f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c @@ -0,0 +1,19 @@ +/* Test the `vld2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c new file mode 100644 index 000000000..1df9eee6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c @@ -0,0 +1,19 @@ +/* Test the `vld2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c new file mode 100644 index 000000000..7440e0c08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c @@ -0,0 +1,19 @@ +/* Test the `vld2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c new file mode 100644 index 000000000..940fd7497 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c @@ -0,0 +1,19 @@ +/* Test the `vld2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c new file mode 100644 index 000000000..35c046a0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c @@ -0,0 +1,19 @@ +/* Test the `vld2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c new file mode 100644 index 000000000..2231e26c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c @@ -0,0 +1,19 @@ +/* Test the `vld2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c new file mode 100644 index 000000000..6bdc1e14a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanef32 (void) +{ + float32x4x3_t out_float32x4x3_t; + float32x4x3_t arg1_float32x4x3_t; + + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c new file mode 100644 index 000000000..12b3be0ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanep16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + poly16x8x3_t arg1_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c new file mode 100644 index 000000000..8ed21e3d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes16 (void) +{ + int16x8x3_t out_int16x8x3_t; + int16x8x3_t arg1_int16x8x3_t; + + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c new file mode 100644 index 000000000..af0118da0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes32 (void) +{ + int32x4x3_t out_int32x4x3_t; + int32x4x3_t arg1_int32x4x3_t; + + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c new file mode 100644 index 000000000..7880b98e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + uint16x8x3_t arg1_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c new file mode 100644 index 000000000..0b1bce5c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + uint32x4x3_t arg1_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c new file mode 100644 index 000000000..6f16d9d87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qf32 (void) +{ + float32x4x3_t out_float32x4x3_t; + + out_float32x4x3_t = vld3q_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c new file mode 100644 index 000000000..ff4ef8653 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qp16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c new file mode 100644 index 000000000..a23749378 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qp8 (void) +{ + poly8x16x3_t out_poly8x16x3_t; + + out_poly8x16x3_t = vld3q_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c new file mode 100644 index 000000000..cfa01367f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs16 (void) +{ + int16x8x3_t out_int16x8x3_t; + + out_int16x8x3_t = vld3q_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c new file mode 100644 index 000000000..e1721ef3d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs32 (void) +{ + int32x4x3_t out_int32x4x3_t; + + out_int32x4x3_t = vld3q_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c new file mode 100644 index 000000000..9f762ca6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs8 (void) +{ + int8x16x3_t out_int8x16x3_t; + + out_int8x16x3_t = vld3q_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c new file mode 100644 index 000000000..a2308729f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c new file mode 100644 index 000000000..21f20f880 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c new file mode 100644 index 000000000..7cbcc4690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu8 (void) +{ + uint8x16x3_t out_uint8x16x3_t; + + out_uint8x16x3_t = vld3q_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c new file mode 100644 index 000000000..542336971 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupf32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c new file mode 100644 index 000000000..6c08c8343 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupp16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c new file mode 100644 index 000000000..23bf88aa6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld3_dupp64 (void) +{ + poly64x1x3_t out_poly64x1x3_t; + + out_poly64x1x3_t = vld3_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c new file mode 100644 index 000000000..fd4a6603f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupp8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c new file mode 100644 index 000000000..4c11e7ef8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c new file mode 100644 index 000000000..b500c24a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c new file mode 100644 index 000000000..cf11f5c1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c new file mode 100644 index 000000000..4f0c8300d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c new file mode 100644 index 000000000..57e3597bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c new file mode 100644 index 000000000..e4abde4f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c new file mode 100644 index 000000000..a91712623 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c new file mode 100644 index 000000000..842618785 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c new file mode 100644 index 000000000..ccbe45f00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanef32 (void) +{ + float32x2x3_t out_float32x2x3_t; + float32x2x3_t arg1_float32x2x3_t; + + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c new file mode 100644 index 000000000..94b4ce421 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanep16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + poly16x4x3_t arg1_poly16x4x3_t; + + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c new file mode 100644 index 000000000..12b0786bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanep8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + poly8x8x3_t arg1_poly8x8x3_t; + + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c new file mode 100644 index 000000000..5ab744fc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes16 (void) +{ + int16x4x3_t out_int16x4x3_t; + int16x4x3_t arg1_int16x4x3_t; + + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c new file mode 100644 index 000000000..168f3f363 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes32 (void) +{ + int32x2x3_t out_int32x2x3_t; + int32x2x3_t arg1_int32x2x3_t; + + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c new file mode 100644 index 000000000..9d0d1a4b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes8 (void) +{ + int8x8x3_t out_int8x8x3_t; + int8x8x3_t arg1_int8x8x3_t; + + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c new file mode 100644 index 000000000..baf97a98a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + uint16x4x3_t arg1_uint16x4x3_t; + + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c new file mode 100644 index 000000000..05d7107f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + uint32x2x3_t arg1_uint32x2x3_t; + + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c new file mode 100644 index 000000000..af7556350 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + uint8x8x3_t arg1_uint8x8x3_t; + + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c new file mode 100644 index 000000000..120f834d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c @@ -0,0 +1,19 @@ +/* Test the `vld3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3f32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c new file mode 100644 index 000000000..2c47f5e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c @@ -0,0 +1,19 @@ +/* Test the `vld3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3p16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c new file mode 100644 index 000000000..cc7992892 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c @@ -0,0 +1,19 @@ +/* Test the `vld3p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld3p64 (void) +{ + poly64x1x3_t out_poly64x1x3_t; + + out_poly64x1x3_t = vld3_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c new file mode 100644 index 000000000..77c2462e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c @@ -0,0 +1,19 @@ +/* Test the `vld3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3p8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c new file mode 100644 index 000000000..355ede8c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c @@ -0,0 +1,19 @@ +/* Test the `vld3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c new file mode 100644 index 000000000..8d18a8843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c @@ -0,0 +1,19 @@ +/* Test the `vld3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c new file mode 100644 index 000000000..67bb3568f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c @@ -0,0 +1,19 @@ +/* Test the `vld3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c new file mode 100644 index 000000000..1be5d11bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c @@ -0,0 +1,19 @@ +/* Test the `vld3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c new file mode 100644 index 000000000..4db18f049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c @@ -0,0 +1,19 @@ +/* Test the `vld3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c new file mode 100644 index 000000000..82c10ff16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c @@ -0,0 +1,19 @@ +/* Test the `vld3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c new file mode 100644 index 000000000..bca1df48f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c @@ -0,0 +1,19 @@ +/* Test the `vld3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c new file mode 100644 index 000000000..c8ac20af1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c @@ -0,0 +1,19 @@ +/* Test the `vld3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c new file mode 100644 index 000000000..5c2499cdc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanef32 (void) +{ + float32x4x4_t out_float32x4x4_t; + float32x4x4_t arg1_float32x4x4_t; + + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c new file mode 100644 index 000000000..1d2d84e63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanep16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + poly16x8x4_t arg1_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c new file mode 100644 index 000000000..df23d281c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes16 (void) +{ + int16x8x4_t out_int16x8x4_t; + int16x8x4_t arg1_int16x8x4_t; + + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c new file mode 100644 index 000000000..db1daff7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes32 (void) +{ + int32x4x4_t out_int32x4x4_t; + int32x4x4_t arg1_int32x4x4_t; + + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c new file mode 100644 index 000000000..e2da0ea27 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + uint16x8x4_t arg1_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c new file mode 100644 index 000000000..d2960ecfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + uint32x4x4_t arg1_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c new file mode 100644 index 000000000..0a6e7e6be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qf32 (void) +{ + float32x4x4_t out_float32x4x4_t; + + out_float32x4x4_t = vld4q_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c new file mode 100644 index 000000000..5d902f531 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qp16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c new file mode 100644 index 000000000..e6d66b048 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qp8 (void) +{ + poly8x16x4_t out_poly8x16x4_t; + + out_poly8x16x4_t = vld4q_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c new file mode 100644 index 000000000..04394215d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs16 (void) +{ + int16x8x4_t out_int16x8x4_t; + + out_int16x8x4_t = vld4q_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c new file mode 100644 index 000000000..4101fa1bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs32 (void) +{ + int32x4x4_t out_int32x4x4_t; + + out_int32x4x4_t = vld4q_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c new file mode 100644 index 000000000..9e74f1e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs8 (void) +{ + int8x16x4_t out_int8x16x4_t; + + out_int8x16x4_t = vld4q_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c new file mode 100644 index 000000000..6b84331f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c new file mode 100644 index 000000000..55f7e93e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c new file mode 100644 index 000000000..9c766c127 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu8 (void) +{ + uint8x16x4_t out_uint8x16x4_t; + + out_uint8x16x4_t = vld4q_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c new file mode 100644 index 000000000..5315db2d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupf32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c new file mode 100644 index 000000000..7ed8224cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupp16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c new file mode 100644 index 000000000..bb15964af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld4_dupp64 (void) +{ + poly64x1x4_t out_poly64x1x4_t; + + out_poly64x1x4_t = vld4_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c new file mode 100644 index 000000000..ca1f8fa98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupp8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c new file mode 100644 index 000000000..43dab8f2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c new file mode 100644 index 000000000..183e3e9ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c new file mode 100644 index 000000000..f4c50493a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c new file mode 100644 index 000000000..3a4684a09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c new file mode 100644 index 000000000..a436cf092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c new file mode 100644 index 000000000..6836abd69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c new file mode 100644 index 000000000..244eb6188 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c new file mode 100644 index 000000000..33c787517 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c new file mode 100644 index 000000000..0fc0ab5fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanef32 (void) +{ + float32x2x4_t out_float32x2x4_t; + float32x2x4_t arg1_float32x2x4_t; + + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c new file mode 100644 index 000000000..b7407ade1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanep16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + poly16x4x4_t arg1_poly16x4x4_t; + + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c new file mode 100644 index 000000000..7e084106d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanep8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + poly8x8x4_t arg1_poly8x8x4_t; + + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c new file mode 100644 index 000000000..0dc653c5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes16 (void) +{ + int16x4x4_t out_int16x4x4_t; + int16x4x4_t arg1_int16x4x4_t; + + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c new file mode 100644 index 000000000..a3bdaf234 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes32 (void) +{ + int32x2x4_t out_int32x2x4_t; + int32x2x4_t arg1_int32x2x4_t; + + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c new file mode 100644 index 000000000..8555220fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes8 (void) +{ + int8x8x4_t out_int8x8x4_t; + int8x8x4_t arg1_int8x8x4_t; + + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c new file mode 100644 index 000000000..4a417f744 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + uint16x4x4_t arg1_uint16x4x4_t; + + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c new file mode 100644 index 000000000..c1e013a9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + uint32x2x4_t arg1_uint32x2x4_t; + + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c new file mode 100644 index 000000000..31dcf8ae6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + uint8x8x4_t arg1_uint8x8x4_t; + + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c new file mode 100644 index 000000000..aa755c0f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c @@ -0,0 +1,19 @@ +/* Test the `vld4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4f32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c new file mode 100644 index 000000000..e0300e8b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c @@ -0,0 +1,19 @@ +/* Test the `vld4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4p16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c new file mode 100644 index 000000000..b11fb9384 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c @@ -0,0 +1,19 @@ +/* Test the `vld4p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld4p64 (void) +{ + poly64x1x4_t out_poly64x1x4_t; + + out_poly64x1x4_t = vld4_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c new file mode 100644 index 000000000..7fbb29cf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c @@ -0,0 +1,19 @@ +/* Test the `vld4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4p8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c new file mode 100644 index 000000000..a5ef07b20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c @@ -0,0 +1,19 @@ +/* Test the `vld4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c new file mode 100644 index 000000000..08b929475 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c @@ -0,0 +1,19 @@ +/* Test the `vld4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c new file mode 100644 index 000000000..99ea54803 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c @@ -0,0 +1,19 @@ +/* Test the `vld4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c new file mode 100644 index 000000000..c9574671e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c @@ -0,0 +1,19 @@ +/* Test the `vld4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c new file mode 100644 index 000000000..4dea8af02 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c @@ -0,0 +1,19 @@ +/* Test the `vld4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c new file mode 100644 index 000000000..aee222589 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c @@ -0,0 +1,19 @@ +/* Test the `vld4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c new file mode 100644 index 000000000..2e8575406 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c @@ -0,0 +1,19 @@ +/* Test the `vld4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c new file mode 100644 index 000000000..ec1d9f9c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c @@ -0,0 +1,19 @@ +/* Test the `vld4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c new file mode 100644 index 000000000..83a2f44d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c new file mode 100644 index 000000000..c8edb7bd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c new file mode 100644 index 000000000..d40f05ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c new file mode 100644 index 000000000..55fdce62b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c new file mode 100644 index 000000000..587a7f1c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c new file mode 100644 index 000000000..dbbe70cc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c new file mode 100644 index 000000000..f785ac8d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c new file mode 100644 index 000000000..ab8cacc3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c new file mode 100644 index 000000000..047d77b49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c new file mode 100644 index 000000000..43ff8874b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c new file mode 100644 index 000000000..54cec995f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c new file mode 100644 index 000000000..8970ba591 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c new file mode 100644 index 000000000..e7094cdff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c new file mode 100644 index 000000000..4e68c3426 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c new file mode 100644 index 000000000..c1a93c6f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c @@ -0,0 +1,21 @@ +/* Test the `vminQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c new file mode 100644 index 000000000..889bd4175 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c @@ -0,0 +1,21 @@ +/* Test the `vminQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c new file mode 100644 index 000000000..dd92bcc49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c @@ -0,0 +1,21 @@ +/* Test the `vminQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c new file mode 100644 index 000000000..dc62e26d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c @@ -0,0 +1,21 @@ +/* Test the `vminQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c new file mode 100644 index 000000000..8b32ee617 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c @@ -0,0 +1,21 @@ +/* Test the `vminQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c new file mode 100644 index 000000000..bc2bb6a32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c @@ -0,0 +1,21 @@ +/* Test the `vminQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c new file mode 100644 index 000000000..4f7c5c63d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c @@ -0,0 +1,21 @@ +/* Test the `vminQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c new file mode 100644 index 000000000..4b69eb92f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c @@ -0,0 +1,21 @@ +/* Test the `vminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c new file mode 100644 index 000000000..33d080c73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c @@ -0,0 +1,21 @@ +/* Test the `vmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c new file mode 100644 index 000000000..ba9920272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c @@ -0,0 +1,21 @@ +/* Test the `vmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c new file mode 100644 index 000000000..956729db5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c @@ -0,0 +1,21 @@ +/* Test the `vmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c new file mode 100644 index 000000000..eba01626f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c @@ -0,0 +1,21 @@ +/* Test the `vminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c new file mode 100644 index 000000000..079c4ca71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c @@ -0,0 +1,21 @@ +/* Test the `vminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c new file mode 100644 index 000000000..0a2241821 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c @@ -0,0 +1,21 @@ +/* Test the `vminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c new file mode 100644 index 000000000..594c1ebdc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c new file mode 100644 index 000000000..151943896 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c new file mode 100644 index 000000000..7ba19cb74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c new file mode 100644 index 000000000..d8885876a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c new file mode 100644 index 000000000..e96e9a7ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c new file mode 100644 index 000000000..3e4057913 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c new file mode 100644 index 000000000..28e0d462d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c new file mode 100644 index 000000000..9b5ecf73b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c new file mode 100644 index 000000000..94481f947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c new file mode 100644 index 000000000..3b1926ab9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c new file mode 100644 index 000000000..336d56967 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c new file mode 100644 index 000000000..339db8763 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c new file mode 100644 index 000000000..579b2921d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c new file mode 100644 index 000000000..f0e5b60e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c new file mode 100644 index 000000000..246df1d8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c new file mode 100644 index 000000000..3108c90b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c new file mode 100644 index 000000000..b87b44872 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c new file mode 100644 index 000000000..8d68f1c79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c new file mode 100644 index 000000000..a426e1138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c new file mode 100644 index 000000000..998c06bdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c new file mode 100644 index 000000000..9274af803 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c new file mode 100644 index 000000000..17e96cb82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c new file mode 100644 index 000000000..3a707c7d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c new file mode 100644 index 000000000..04f2493f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c new file mode 100644 index 000000000..464c09450 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c new file mode 100644 index 000000000..b2eb2ed11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c new file mode 100644 index 000000000..6f11e99a5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c new file mode 100644 index 000000000..8b1ac6a97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c new file mode 100644 index 000000000..61f3c7ba9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c new file mode 100644 index 000000000..d7348de60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c new file mode 100644 index 000000000..93fc8bf55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c new file mode 100644 index 000000000..12103d125 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c new file mode 100644 index 000000000..968aef746 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c new file mode 100644 index 000000000..d4b3e46be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c new file mode 100644 index 000000000..9bec57879 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c new file mode 100644 index 000000000..4fadfe94f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c new file mode 100644 index 000000000..a62162000 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c @@ -0,0 +1,22 @@ +/* Test the `vmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c new file mode 100644 index 000000000..e64db5959 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c @@ -0,0 +1,22 @@ +/* Test the `vmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c new file mode 100644 index 000000000..22f4bdbed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c @@ -0,0 +1,22 @@ +/* Test the `vmlals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c new file mode 100644 index 000000000..874fd87b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c new file mode 100644 index 000000000..593c06b45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c new file mode 100644 index 000000000..efb4312cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c new file mode 100644 index 000000000..b37272b89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c @@ -0,0 +1,22 @@ +/* Test the `vmlas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c new file mode 100644 index 000000000..65c2e9af2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c @@ -0,0 +1,22 @@ +/* Test the `vmlas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c new file mode 100644 index 000000000..fcb1fd38d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c @@ -0,0 +1,22 @@ +/* Test the `vmlas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c new file mode 100644 index 000000000..c1dceab97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c @@ -0,0 +1,22 @@ +/* Test the `vmlau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c new file mode 100644 index 000000000..6acbea572 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c @@ -0,0 +1,22 @@ +/* Test the `vmlau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c new file mode 100644 index 000000000..9fc36666b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c @@ -0,0 +1,22 @@ +/* Test the `vmlau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c new file mode 100644 index 000000000..64ef449a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c new file mode 100644 index 000000000..3788e7f82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c new file mode 100644 index 000000000..952638079 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c new file mode 100644 index 000000000..a176265ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c new file mode 100644 index 000000000..094b9fd17 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c new file mode 100644 index 000000000..292a32874 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c new file mode 100644 index 000000000..02da0712a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c new file mode 100644 index 000000000..b09aaec97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c new file mode 100644 index 000000000..a42471171 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c new file mode 100644 index 000000000..b84ff6f6e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c new file mode 100644 index 000000000..af2ca68fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c new file mode 100644 index 000000000..4c83d9f31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c new file mode 100644 index 000000000..575ae0c39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c new file mode 100644 index 000000000..227ad9b21 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c new file mode 100644 index 000000000..9d785da73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c new file mode 100644 index 000000000..55a56a0de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c new file mode 100644 index 000000000..fc589718e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c new file mode 100644 index 000000000..f4b9c306c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c new file mode 100644 index 000000000..827178e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c new file mode 100644 index 000000000..5e226c1db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c new file mode 100644 index 000000000..dbc1e8bba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c new file mode 100644 index 000000000..7e6406ec0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c new file mode 100644 index 000000000..fca965b90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c new file mode 100644 index 000000000..712cfbb8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c new file mode 100644 index 000000000..6d977ec22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c new file mode 100644 index 000000000..772d3f97c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c new file mode 100644 index 000000000..4f1368d78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c new file mode 100644 index 000000000..2f44ee0ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c new file mode 100644 index 000000000..b36355acf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c new file mode 100644 index 000000000..dfab11895 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c new file mode 100644 index 000000000..aff34beac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c new file mode 100644 index 000000000..c9738747d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c new file mode 100644 index 000000000..22a045515 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c new file mode 100644 index 000000000..83370fdc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c new file mode 100644 index 000000000..232f7fe74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c new file mode 100644 index 000000000..b64226659 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c new file mode 100644 index 000000000..6ec259efe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c new file mode 100644 index 000000000..b7dd71427 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c new file mode 100644 index 000000000..ca6960bc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c new file mode 100644 index 000000000..47cbfb32a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c new file mode 100644 index 000000000..9765e5139 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c new file mode 100644 index 000000000..dcb55162b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c new file mode 100644 index 000000000..5655a1584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c @@ -0,0 +1,22 @@ +/* Test the `vmlss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c new file mode 100644 index 000000000..1a467dcd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c @@ -0,0 +1,22 @@ +/* Test the `vmlss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c new file mode 100644 index 000000000..db95bdc47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c @@ -0,0 +1,22 @@ +/* Test the `vmlss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c new file mode 100644 index 000000000..dfb918b6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c new file mode 100644 index 000000000..0afbc089f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c new file mode 100644 index 000000000..4da7a41d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c new file mode 100644 index 000000000..751910996 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vmovq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c new file mode 100644 index 000000000..48361e99e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c new file mode 100644 index 000000000..a3de68fde --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c new file mode 100644 index 000000000..1cec77735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vmovq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c new file mode 100644 index 000000000..59178b799 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vmovq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c new file mode 100644 index 000000000..35936cbd4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c new file mode 100644 index 000000000..e6883aed5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vmovq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c new file mode 100644 index 000000000..66b459a74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c new file mode 100644 index 000000000..958bb97f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c new file mode 100644 index 000000000..e373a1218 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c new file mode 100644 index 000000000..53120a8dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c new file mode 100644 index 000000000..589911947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vmov_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c new file mode 100644 index 000000000..02c906c10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c new file mode 100644 index 000000000..afd6b46f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c new file mode 100644 index 000000000..7691e1f4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vmov_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c new file mode 100644 index 000000000..b1454ca29 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vmov_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c new file mode 100644 index 000000000..7b0112828 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vmov_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c new file mode 100644 index 000000000..46a5dc8f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vmov_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c new file mode 100644 index 000000000..00ad860b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c new file mode 100644 index 000000000..c8424c204 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c new file mode 100644 index 000000000..b9613e06f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c new file mode 100644 index 000000000..38d80bcd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c new file mode 100644 index 000000000..31d5ef14a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c @@ -0,0 +1,20 @@ +/* Test the `vmovls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vmovl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c new file mode 100644 index 000000000..0d95e2eb9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c @@ -0,0 +1,20 @@ +/* Test the `vmovls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vmovl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c new file mode 100644 index 000000000..b27db8300 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c @@ -0,0 +1,20 @@ +/* Test the `vmovls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vmovl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c new file mode 100644 index 000000000..acca55af2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c new file mode 100644 index 000000000..f1eee8ee0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c new file mode 100644 index 000000000..2bf08e1e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c new file mode 100644 index 000000000..abd648bda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c @@ -0,0 +1,20 @@ +/* Test the `vmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c new file mode 100644 index 000000000..82c1c3714 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c @@ -0,0 +1,20 @@ +/* Test the `vmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c new file mode 100644 index 000000000..091bddc2a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c @@ -0,0 +1,20 @@ +/* Test the `vmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c new file mode 100644 index 000000000..85fca5f57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c new file mode 100644 index 000000000..6bdf0d453 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c new file mode 100644 index 000000000..41019fb7d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c new file mode 100644 index 000000000..cc4651be0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c new file mode 100644 index 000000000..e4620490d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c new file mode 100644 index 000000000..0e0e52734 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c new file mode 100644 index 000000000..d8897a599 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c new file mode 100644 index 000000000..f336710cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c new file mode 100644 index 000000000..e37e9ae40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32_t arg1_float32_t; + + out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c new file mode 100644 index 000000000..ff81b43ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c new file mode 100644 index 000000000..714bef43a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c new file mode 100644 index 000000000..ef05b9378 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16_t arg1_uint16_t; + + out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c new file mode 100644 index 000000000..2af6d757a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32_t arg1_uint32_t; + + out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c new file mode 100644 index 000000000..3e9ceb056 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c new file mode 100644 index 000000000..fe19f13da --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c new file mode 100644 index 000000000..5d4ac7b1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c new file mode 100644 index 000000000..3f8027270 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c new file mode 100644 index 000000000..8e49dbcf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c new file mode 100644 index 000000000..e73bc6dd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c new file mode 100644 index 000000000..d041a0d8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c new file mode 100644 index 000000000..75b3c67d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c new file mode 100644 index 000000000..967117975 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c new file mode 100644 index 000000000..b1a089274 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c new file mode 100644 index 000000000..dce5e9a94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c new file mode 100644 index 000000000..d73a2514d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c new file mode 100644 index 000000000..c77268bca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c new file mode 100644 index 000000000..8f7522402 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32_t arg1_float32_t; + + out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c new file mode 100644 index 000000000..cf24912d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c new file mode 100644 index 000000000..9c0a35e53 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c new file mode 100644 index 000000000..5d2c60b48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c new file mode 100644 index 000000000..9957837e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c new file mode 100644 index 000000000..7081b2f07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c new file mode 100644 index 000000000..4467bca7e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c new file mode 100644 index 000000000..db1655faa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c new file mode 100644 index 000000000..c723df2ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c new file mode 100644 index 000000000..adea5cc3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c new file mode 100644 index 000000000..9de27deb9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c new file mode 100644 index 000000000..0fe16d16f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c new file mode 100644 index 000000000..b3e9c1932 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c new file mode 100644 index 000000000..6cf18d24a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c new file mode 100644 index 000000000..72c288392 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c @@ -0,0 +1,21 @@ +/* Test the `vmullp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullp8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c new file mode 100644 index 000000000..cb7327886 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c @@ -0,0 +1,21 @@ +/* Test the `vmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c new file mode 100644 index 000000000..816f3abc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c @@ -0,0 +1,21 @@ +/* Test the `vmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c new file mode 100644 index 000000000..4c0d2b4aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c @@ -0,0 +1,21 @@ +/* Test the `vmulls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c new file mode 100644 index 000000000..8dad8be65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c @@ -0,0 +1,21 @@ +/* Test the `vmullu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c new file mode 100644 index 000000000..6010fa92c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c @@ -0,0 +1,21 @@ +/* Test the `vmullu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c new file mode 100644 index 000000000..05eb05ac3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c @@ -0,0 +1,21 @@ +/* Test the `vmullu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c new file mode 100644 index 000000000..3a9857271 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c @@ -0,0 +1,21 @@ +/* Test the `vmulp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c new file mode 100644 index 000000000..b2ac4c8c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c @@ -0,0 +1,21 @@ +/* Test the `vmuls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c new file mode 100644 index 000000000..7cac98d82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c @@ -0,0 +1,21 @@ +/* Test the `vmuls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c new file mode 100644 index 000000000..08fd311ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c @@ -0,0 +1,21 @@ +/* Test the `vmuls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c new file mode 100644 index 000000000..141d72fbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c new file mode 100644 index 000000000..5c36ffb9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c new file mode 100644 index 000000000..51d4a1708 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c @@ -0,0 +1,21 @@ +/* Test the `vmulu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c new file mode 100644 index 000000000..47d50b64f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c new file mode 100644 index 000000000..e60488447 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c new file mode 100644 index 000000000..ccad86944 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c new file mode 100644 index 000000000..164907c7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c new file mode 100644 index 000000000..ce18a4907 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c new file mode 100644 index 000000000..34795c776 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c new file mode 100644 index 000000000..d93aa36b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c new file mode 100644 index 000000000..46e3cf910 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c new file mode 100644 index 000000000..8464b2b95 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c @@ -0,0 +1,20 @@ +/* Test the `vmvns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vmvn_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c new file mode 100644 index 000000000..7a4dd9a79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c @@ -0,0 +1,20 @@ +/* Test the `vmvns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vmvn_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c new file mode 100644 index 000000000..c09872092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c @@ -0,0 +1,20 @@ +/* Test the `vmvns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vmvn_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c new file mode 100644 index 000000000..ab600a0a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c new file mode 100644 index 000000000..df2bd4b5a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c new file mode 100644 index 000000000..729ab71c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c new file mode 100644 index 000000000..c1e116913 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c @@ -0,0 +1,20 @@ +/* Test the `vnegQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vnegq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c new file mode 100644 index 000000000..c8b149789 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c new file mode 100644 index 000000000..e8b3e925c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c new file mode 100644 index 000000000..4e8e80d31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c new file mode 100644 index 000000000..82e95399f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c @@ -0,0 +1,20 @@ +/* Test the `vnegf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vneg_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c new file mode 100644 index 000000000..ff2315180 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c @@ -0,0 +1,20 @@ +/* Test the `vnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c new file mode 100644 index 000000000..82108678e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c @@ -0,0 +1,20 @@ +/* Test the `vnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c new file mode 100644 index 000000000..952e34010 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c @@ -0,0 +1,20 @@ +/* Test the `vnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c new file mode 100644 index 000000000..519da3ccc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c @@ -0,0 +1,21 @@ +/* Test the `vornQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c new file mode 100644 index 000000000..cec659911 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c @@ -0,0 +1,21 @@ +/* Test the `vornQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c new file mode 100644 index 000000000..05166ba4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c @@ -0,0 +1,21 @@ +/* Test the `vornQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c new file mode 100644 index 000000000..99982aefd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c @@ -0,0 +1,21 @@ +/* Test the `vornQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c new file mode 100644 index 000000000..761e72d7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c @@ -0,0 +1,21 @@ +/* Test the `vornQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c new file mode 100644 index 000000000..18a968539 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c @@ -0,0 +1,21 @@ +/* Test the `vornQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c new file mode 100644 index 000000000..84c9f895d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c @@ -0,0 +1,21 @@ +/* Test the `vornQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c new file mode 100644 index 000000000..ffe6766d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c @@ -0,0 +1,21 @@ +/* Test the `vornQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c new file mode 100644 index 000000000..b860142dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c @@ -0,0 +1,21 @@ +/* Test the `vorns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c new file mode 100644 index 000000000..826e0d288 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c @@ -0,0 +1,21 @@ +/* Test the `vorns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c new file mode 100644 index 000000000..d7b8e60d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c @@ -0,0 +1,20 @@ +/* Test the `vorns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c new file mode 100644 index 000000000..c71a6bb0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c @@ -0,0 +1,21 @@ +/* Test the `vorns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c new file mode 100644 index 000000000..d4983eebf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c @@ -0,0 +1,21 @@ +/* Test the `vornu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c new file mode 100644 index 000000000..aba68841a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c @@ -0,0 +1,21 @@ +/* Test the `vornu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c new file mode 100644 index 000000000..6fb3a9502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c @@ -0,0 +1,20 @@ +/* Test the `vornu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c new file mode 100644 index 000000000..6fdb7331c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c @@ -0,0 +1,21 @@ +/* Test the `vornu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c new file mode 100644 index 000000000..20ae7342e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c new file mode 100644 index 000000000..ba42dccd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c new file mode 100644 index 000000000..f46e7c16e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c new file mode 100644 index 000000000..d58607c84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c new file mode 100644 index 000000000..ce29c4ad7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c new file mode 100644 index 000000000..8b1a64845 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c new file mode 100644 index 000000000..55cf57ae5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c new file mode 100644 index 000000000..7be85fc43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c new file mode 100644 index 000000000..8e942cc1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c @@ -0,0 +1,21 @@ +/* Test the `vorrs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c new file mode 100644 index 000000000..f940a6530 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c @@ -0,0 +1,21 @@ +/* Test the `vorrs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c new file mode 100644 index 000000000..a1c7e5ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c @@ -0,0 +1,20 @@ +/* Test the `vorrs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c new file mode 100644 index 000000000..2d6b70cbe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c @@ -0,0 +1,21 @@ +/* Test the `vorrs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c new file mode 100644 index 000000000..5d50d7aad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c @@ -0,0 +1,21 @@ +/* Test the `vorru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c new file mode 100644 index 000000000..60c847649 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c @@ -0,0 +1,21 @@ +/* Test the `vorru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c new file mode 100644 index 000000000..1991b0215 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c @@ -0,0 +1,20 @@ +/* Test the `vorru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c new file mode 100644 index 000000000..e47d465e5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c @@ -0,0 +1,21 @@ +/* Test the `vorru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c new file mode 100644 index 000000000..35dcdbbad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x8_t arg1_int16x8_t; + + out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c new file mode 100644 index 000000000..a82551a28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x4_t arg1_int32x4_t; + + out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c new file mode 100644 index 000000000..182ea46c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x16_t arg1_int8x16_t; + + out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c new file mode 100644 index 000000000..c9f7833d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x8_t arg1_uint16x8_t; + + out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c new file mode 100644 index 000000000..80cf323ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x4_t arg1_uint32x4_t; + + out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c new file mode 100644 index 000000000..8e1dac223 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c new file mode 100644 index 000000000..88c3cb179 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c @@ -0,0 +1,21 @@ +/* Test the `vpadals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals16 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int16x4_t arg1_int16x4_t; + + out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c new file mode 100644 index 000000000..95897f5cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c @@ -0,0 +1,21 @@ +/* Test the `vpadals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals32 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int32x2_t arg1_int32x2_t; + + out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c new file mode 100644 index 000000000..3cc18459d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c @@ -0,0 +1,21 @@ +/* Test the `vpadals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals8 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int8x8_t arg1_int8x8_t; + + out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c new file mode 100644 index 000000000..280e4d611 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c new file mode 100644 index 000000000..1792b43d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c new file mode 100644 index 000000000..f3fb6b031 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c new file mode 100644 index 000000000..f08c8506a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c @@ -0,0 +1,21 @@ +/* Test the `vpaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c new file mode 100644 index 000000000..b3fc9aa13 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c new file mode 100644 index 000000000..00399e804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c new file mode 100644 index 000000000..09191ab3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c new file mode 100644 index 000000000..d65754b0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c new file mode 100644 index 000000000..b93bfd3f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c new file mode 100644 index 000000000..15f8a18a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c new file mode 100644 index 000000000..57d93b50d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c new file mode 100644 index 000000000..5abb48994 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c new file mode 100644 index 000000000..0107bfa1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c new file mode 100644 index 000000000..01c1fac9e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c new file mode 100644 index 000000000..6c47b0582 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c new file mode 100644 index 000000000..47fbc738a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c new file mode 100644 index 000000000..6d9ad1afd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c @@ -0,0 +1,21 @@ +/* Test the `vpadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c new file mode 100644 index 000000000..36d8aad1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c @@ -0,0 +1,21 @@ +/* Test the `vpadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c new file mode 100644 index 000000000..ea6bcae85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c @@ -0,0 +1,21 @@ +/* Test the `vpadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c new file mode 100644 index 000000000..1a19916e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c new file mode 100644 index 000000000..3bf215c71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c new file mode 100644 index 000000000..e1b6c5987 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c new file mode 100644 index 000000000..267fc3862 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c new file mode 100644 index 000000000..7476f2462 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c new file mode 100644 index 000000000..d2c3e81f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c new file mode 100644 index 000000000..c15c0b0a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c new file mode 100644 index 000000000..8fbad8694 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c new file mode 100644 index 000000000..2869fd339 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c new file mode 100644 index 000000000..75a29f27b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c new file mode 100644 index 000000000..59836f78f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c @@ -0,0 +1,21 @@ +/* Test the `vpminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c new file mode 100644 index 000000000..14af72840 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c @@ -0,0 +1,21 @@ +/* Test the `vpmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c new file mode 100644 index 000000000..c34afbdff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c @@ -0,0 +1,21 @@ +/* Test the `vpmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c new file mode 100644 index 000000000..b0212ff90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c @@ -0,0 +1,21 @@ +/* Test the `vpmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c new file mode 100644 index 000000000..a9fa87c7e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c @@ -0,0 +1,21 @@ +/* Test the `vpminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c new file mode 100644 index 000000000..2c2cb75ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c @@ -0,0 +1,21 @@ +/* Test the `vpminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c new file mode 100644 index 000000000..726fa72fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c @@ -0,0 +1,21 @@ +/* Test the `vpminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c new file mode 100644 index 000000000..75cbc0a2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c new file mode 100644 index 000000000..12978d383 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c new file mode 100644 index 000000000..55f9037f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c new file mode 100644 index 000000000..7323fe22a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c new file mode 100644 index 000000000..f6c3d1fdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c new file mode 100644 index 000000000..2801f4ffc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c new file mode 100644 index 000000000..3567a8ced --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c new file mode 100644 index 000000000..04d8fe750 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c new file mode 100644 index 000000000..1ab2c5ab6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c new file mode 100644 index 000000000..16a0de031 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c new file mode 100644 index 000000000..d27b4bce3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c new file mode 100644 index 000000000..e4dc0b90d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c new file mode 100644 index 000000000..ed3dc442a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c new file mode 100644 index 000000000..54bd77781 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c new file mode 100644 index 000000000..47dc81e8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c new file mode 100644 index 000000000..4bd258949 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c new file mode 100644 index 000000000..b150120eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c new file mode 100644 index 000000000..f38f38396 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c new file mode 100644 index 000000000..0c2da6d42 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c new file mode 100644 index 000000000..e2e515577 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c new file mode 100644 index 000000000..c0c456c34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c new file mode 100644 index 000000000..275150c86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c new file mode 100644 index 000000000..6e67b57d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c new file mode 100644 index 000000000..a81c9eaf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c new file mode 100644 index 000000000..2c2a7bfcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c new file mode 100644 index 000000000..65dd695fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c new file mode 100644 index 000000000..3757279e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c new file mode 100644 index 000000000..01565bba5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c new file mode 100644 index 000000000..ff5902f6c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c new file mode 100644 index 000000000..7a01d6b7a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c new file mode 100644 index 000000000..ddb866280 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c new file mode 100644 index 000000000..5147ac90f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c new file mode 100644 index 000000000..8d682946b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c new file mode 100644 index 000000000..7f7eacba8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c new file mode 100644 index 000000000..547ffd1b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c new file mode 100644 index 000000000..a8f7904a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c new file mode 100644 index 000000000..fde62bcbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c new file mode 100644 index 000000000..a31b5cb51 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c new file mode 100644 index 000000000..3ef17b938 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c new file mode 100644 index 000000000..e4ddbb666 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c new file mode 100644 index 000000000..9bcab766b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c @@ -0,0 +1,20 @@ +/* Test the `vqabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c new file mode 100644 index 000000000..20ecb7eea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c @@ -0,0 +1,20 @@ +/* Test the `vqabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c new file mode 100644 index 000000000..e4ee27ce6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c @@ -0,0 +1,20 @@ +/* Test the `vqabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c new file mode 100644 index 000000000..d5e1fc289 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c new file mode 100644 index 000000000..f408a3e04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c new file mode 100644 index 000000000..8f1a1a8b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c new file mode 100644 index 000000000..e94dc13d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c new file mode 100644 index 000000000..84f567748 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c new file mode 100644 index 000000000..5055627d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c new file mode 100644 index 000000000..cc3da0faa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c new file mode 100644 index 000000000..d64daf408 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c new file mode 100644 index 000000000..4a4df0be8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c @@ -0,0 +1,21 @@ +/* Test the `vqadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c new file mode 100644 index 000000000..b1a022fd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c @@ -0,0 +1,21 @@ +/* Test the `vqadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c new file mode 100644 index 000000000..48b4a6ebc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c @@ -0,0 +1,21 @@ +/* Test the `vqadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c new file mode 100644 index 000000000..3b408bc8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c @@ -0,0 +1,21 @@ +/* Test the `vqadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c new file mode 100644 index 000000000..b3d720483 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c new file mode 100644 index 000000000..dbe9038a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c new file mode 100644 index 000000000..08230f833 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c new file mode 100644 index 000000000..c465022f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c new file mode 100644 index 000000000..d2567c092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c new file mode 100644 index 000000000..7a9cfe8bc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c new file mode 100644 index 000000000..43a096265 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c new file mode 100644 index 000000000..2031a60db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c new file mode 100644 index 000000000..6391a7988 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c new file mode 100644 index 000000000..e7ff0d849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c new file mode 100644 index 000000000..aa32c490b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c new file mode 100644 index 000000000..c88b81a5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c new file mode 100644 index 000000000..3981f508b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c new file mode 100644 index 000000000..36c200be8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c new file mode 100644 index 000000000..06aeb8e14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c new file mode 100644 index 000000000..fac2fb654 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c new file mode 100644 index 000000000..70ee8a3f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c new file mode 100644 index 000000000..ea74a9172 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c new file mode 100644 index 000000000..10009f0d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c new file mode 100644 index 000000000..1884c9528 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c new file mode 100644 index 000000000..c9cacfc1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c new file mode 100644 index 000000000..ff6eb74e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c new file mode 100644 index 000000000..5b8e4c54e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c new file mode 100644 index 000000000..507bde891 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c new file mode 100644 index 000000000..e16030c2a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c new file mode 100644 index 000000000..be38f92ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c new file mode 100644 index 000000000..ef591cba6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c new file mode 100644 index 000000000..cb51f4be9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c new file mode 100644 index 000000000..f9476a2f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c new file mode 100644 index 000000000..2d5ee0064 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c new file mode 100644 index 000000000..1e980f1ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c new file mode 100644 index 000000000..947aa9635 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c new file mode 100644 index 000000000..72ba7c2ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c new file mode 100644 index 000000000..6a6b2e2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c new file mode 100644 index 000000000..8807b5909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c new file mode 100644 index 000000000..a921575e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c new file mode 100644 index 000000000..3c5285b11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c new file mode 100644 index 000000000..ce74646fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c new file mode 100644 index 000000000..74e1b8a08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c new file mode 100644 index 000000000..2e312505b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c new file mode 100644 index 000000000..845af1fa9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c new file mode 100644 index 000000000..6fa8d97a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c new file mode 100644 index 000000000..cb9b462b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c new file mode 100644 index 000000000..c5f523858 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c new file mode 100644 index 000000000..cc32b2138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c new file mode 100644 index 000000000..755847d0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c new file mode 100644 index 000000000..a05a1fc8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c new file mode 100644 index 000000000..30c43ef5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c new file mode 100644 index 000000000..d9f23ad83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c new file mode 100644 index 000000000..1383779fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c new file mode 100644 index 000000000..acafc1c28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c new file mode 100644 index 000000000..ec90a8866 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c new file mode 100644 index 000000000..e2a25e93d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c new file mode 100644 index 000000000..b01497d40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c new file mode 100644 index 000000000..613d3dc66 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c new file mode 100644 index 000000000..1d9bea8b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c new file mode 100644 index 000000000..1f0e739b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c new file mode 100644 index 000000000..80f3644a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c new file mode 100644 index 000000000..6c5bd1606 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c new file mode 100644 index 000000000..6819d8286 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c new file mode 100644 index 000000000..27c5c1d26 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c new file mode 100644 index 000000000..163e02def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c new file mode 100644 index 000000000..b6f46d096 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c new file mode 100644 index 000000000..15ecce049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c new file mode 100644 index 000000000..058095b36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c new file mode 100644 index 000000000..de81ba00e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c new file mode 100644 index 000000000..fac6fdb49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c new file mode 100644 index 000000000..0860a4463 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c new file mode 100644 index 000000000..4e49ad352 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c new file mode 100644 index 000000000..483aa8179 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c new file mode 100644 index 000000000..ad09efda2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c new file mode 100644 index 000000000..9abc96025 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c new file mode 100644 index 000000000..d02d6f7c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c new file mode 100644 index 000000000..cf288a078 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c @@ -0,0 +1,21 @@ +/* Test the `vqshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c new file mode 100644 index 000000000..39e38bfc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c @@ -0,0 +1,21 @@ +/* Test the `vqshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c new file mode 100644 index 000000000..6057b3589 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c @@ -0,0 +1,21 @@ +/* Test the `vqshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c new file mode 100644 index 000000000..4d3332fd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c @@ -0,0 +1,21 @@ +/* Test the `vqshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c new file mode 100644 index 000000000..cbae9aaec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c new file mode 100644 index 000000000..89ba48a23 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c new file mode 100644 index 000000000..df91fa9b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c new file mode 100644 index 000000000..f7ea9231b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c new file mode 100644 index 000000000..26feb6474 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c new file mode 100644 index 000000000..70a156d6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c new file mode 100644 index 000000000..bed332d60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c new file mode 100644 index 000000000..96e434752 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c new file mode 100644 index 000000000..2ec926ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c new file mode 100644 index 000000000..b9c156ad0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c new file mode 100644 index 000000000..5003573d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c new file mode 100644 index 000000000..649588e97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c new file mode 100644 index 000000000..4a0d5095b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c new file mode 100644 index 000000000..e9a10f6d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c new file mode 100644 index 000000000..32e9aef2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c new file mode 100644 index 000000000..6582d8fea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c new file mode 100644 index 000000000..39eef07f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c new file mode 100644 index 000000000..b479526ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c new file mode 100644 index 000000000..94d6b60e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c new file mode 100644 index 000000000..9d04d51a5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c new file mode 100644 index 000000000..37085e97c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c new file mode 100644 index 000000000..72943b2e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c new file mode 100644 index 000000000..be37e9115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c new file mode 100644 index 000000000..019b0a696 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c new file mode 100644 index 000000000..a08c1404d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c new file mode 100644 index 000000000..979f7c173 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c new file mode 100644 index 000000000..b0de08699 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c new file mode 100644 index 000000000..e03c2b236 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c new file mode 100644 index 000000000..a447931a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c new file mode 100644 index 000000000..89a87e5b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c new file mode 100644 index 000000000..fdc563c19 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c new file mode 100644 index 000000000..f8ba1ed00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c new file mode 100644 index 000000000..c16cb1a9b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c new file mode 100644 index 000000000..51b58df63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c new file mode 100644 index 000000000..799a3e38d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c new file mode 100644 index 000000000..673c8174b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c new file mode 100644 index 000000000..5a1eb44cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c new file mode 100644 index 000000000..d35cbd6e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c new file mode 100644 index 000000000..9f0949e0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c new file mode 100644 index 000000000..edd17ee47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c new file mode 100644 index 000000000..d59e810ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c new file mode 100644 index 000000000..d3452e96e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c @@ -0,0 +1,21 @@ +/* Test the `vrecpsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c new file mode 100644 index 000000000..c8d885b07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c @@ -0,0 +1,21 @@ +/* Test the `vrecpsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c new file mode 100644 index 000000000..91cac4df5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p128 (void) +{ + float32x4_t out_float32x4_t; + poly128_t arg0_poly128_t; + + out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c new file mode 100644 index 000000000..58049ac5b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p16 (void) +{ + float32x4_t out_float32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c new file mode 100644 index 000000000..96909f677 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p64 (void) +{ + float32x4_t out_float32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c new file mode 100644 index 000000000..fc5676001 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p8 (void) +{ + float32x4_t out_float32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c new file mode 100644 index 000000000..dc2227fe2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s16 (void) +{ + float32x4_t out_float32x4_t; + int16x8_t arg0_int16x8_t; + + out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c new file mode 100644 index 000000000..d0781f467 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c new file mode 100644 index 000000000..1528c711e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s64 (void) +{ + float32x4_t out_float32x4_t; + int64x2_t arg0_int64x2_t; + + out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c new file mode 100644 index 000000000..eb3a46bd4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s8 (void) +{ + float32x4_t out_float32x4_t; + int8x16_t arg0_int8x16_t; + + out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c new file mode 100644 index 000000000..5562dfff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u16 (void) +{ + float32x4_t out_float32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c new file mode 100644 index 000000000..8b43c6693 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c new file mode 100644 index 000000000..71e6a5f9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u64 (void) +{ + float32x4_t out_float32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c new file mode 100644 index 000000000..569316344 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u8 (void) +{ + float32x4_t out_float32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c new file mode 100644 index 000000000..aa7d2e7e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_f32 (void) +{ + poly128_t out_poly128_t; + float32x4_t arg0_float32x4_t; + + out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c new file mode 100644 index 000000000..94f2e9b4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p16 (void) +{ + poly128_t out_poly128_t; + poly16x8_t arg0_poly16x8_t; + + out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c new file mode 100644 index 000000000..d32007547 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p64 (void) +{ + poly128_t out_poly128_t; + poly64x2_t arg0_poly64x2_t; + + out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c new file mode 100644 index 000000000..112b0c6e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p8 (void) +{ + poly128_t out_poly128_t; + poly8x16_t arg0_poly8x16_t; + + out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c new file mode 100644 index 000000000..4fa06b238 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s16 (void) +{ + poly128_t out_poly128_t; + int16x8_t arg0_int16x8_t; + + out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c new file mode 100644 index 000000000..5f17cb813 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s32 (void) +{ + poly128_t out_poly128_t; + int32x4_t arg0_int32x4_t; + + out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c new file mode 100644 index 000000000..9b83912b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s64 (void) +{ + poly128_t out_poly128_t; + int64x2_t arg0_int64x2_t; + + out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c new file mode 100644 index 000000000..49e8b74b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s8 (void) +{ + poly128_t out_poly128_t; + int8x16_t arg0_int8x16_t; + + out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c new file mode 100644 index 000000000..d47429aeb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u16 (void) +{ + poly128_t out_poly128_t; + uint16x8_t arg0_uint16x8_t; + + out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c new file mode 100644 index 000000000..57abf79a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u32 (void) +{ + poly128_t out_poly128_t; + uint32x4_t arg0_uint32x4_t; + + out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c new file mode 100644 index 000000000..4d04daaaa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u64 (void) +{ + poly128_t out_poly128_t; + uint64x2_t arg0_uint64x2_t; + + out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c new file mode 100644 index 000000000..ba07bbc8a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u8 (void) +{ + poly128_t out_poly128_t; + uint8x16_t arg0_uint8x16_t; + + out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c new file mode 100644 index 000000000..b94f8f6ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_f32 (void) +{ + poly16x8_t out_poly16x8_t; + float32x4_t arg0_float32x4_t; + + out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c new file mode 100644 index 000000000..27d0d0afb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p128 (void) +{ + poly16x8_t out_poly16x8_t; + poly128_t arg0_poly128_t; + + out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c new file mode 100644 index 000000000..a0a3aaff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p64 (void) +{ + poly16x8_t out_poly16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c new file mode 100644 index 000000000..d284b595c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c new file mode 100644 index 000000000..fedcfa8de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s16 (void) +{ + poly16x8_t out_poly16x8_t; + int16x8_t arg0_int16x8_t; + + out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c new file mode 100644 index 000000000..8c56fee74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s32 (void) +{ + poly16x8_t out_poly16x8_t; + int32x4_t arg0_int32x4_t; + + out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c new file mode 100644 index 000000000..03c391a73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s64 (void) +{ + poly16x8_t out_poly16x8_t; + int64x2_t arg0_int64x2_t; + + out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c new file mode 100644 index 000000000..11b6c915d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s8 (void) +{ + poly16x8_t out_poly16x8_t; + int8x16_t arg0_int8x16_t; + + out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c new file mode 100644 index 000000000..80ba65f7c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c new file mode 100644 index 000000000..f1c9aeb75 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u32 (void) +{ + poly16x8_t out_poly16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c new file mode 100644 index 000000000..c2365d1bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u64 (void) +{ + poly16x8_t out_poly16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c new file mode 100644 index 000000000..8333c2f16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u8 (void) +{ + poly16x8_t out_poly16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c new file mode 100644 index 000000000..9f9b1a4ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_f32 (void) +{ + poly64x2_t out_poly64x2_t; + float32x4_t arg0_float32x4_t; + + out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c new file mode 100644 index 000000000..3f7129513 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p128 (void) +{ + poly64x2_t out_poly64x2_t; + poly128_t arg0_poly128_t; + + out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c new file mode 100644 index 000000000..897b7cd9d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p16 (void) +{ + poly64x2_t out_poly64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c new file mode 100644 index 000000000..772b268bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p8 (void) +{ + poly64x2_t out_poly64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c new file mode 100644 index 000000000..29f3f6c1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s16 (void) +{ + poly64x2_t out_poly64x2_t; + int16x8_t arg0_int16x8_t; + + out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c new file mode 100644 index 000000000..fae22f65e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s32 (void) +{ + poly64x2_t out_poly64x2_t; + int32x4_t arg0_int32x4_t; + + out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c new file mode 100644 index 000000000..8769bc8e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s64 (void) +{ + poly64x2_t out_poly64x2_t; + int64x2_t arg0_int64x2_t; + + out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c new file mode 100644 index 000000000..1163cc2b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s8 (void) +{ + poly64x2_t out_poly64x2_t; + int8x16_t arg0_int8x16_t; + + out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c new file mode 100644 index 000000000..f2b53260e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u16 (void) +{ + poly64x2_t out_poly64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c new file mode 100644 index 000000000..6b6179ba4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u32 (void) +{ + poly64x2_t out_poly64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c new file mode 100644 index 000000000..655ffd4fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u64 (void) +{ + poly64x2_t out_poly64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c new file mode 100644 index 000000000..40b40dd11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u8 (void) +{ + poly64x2_t out_poly64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c new file mode 100644 index 000000000..e27080efd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_f32 (void) +{ + poly8x16_t out_poly8x16_t; + float32x4_t arg0_float32x4_t; + + out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c new file mode 100644 index 000000000..b517a6fdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p128 (void) +{ + poly8x16_t out_poly8x16_t; + poly128_t arg0_poly128_t; + + out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c new file mode 100644 index 000000000..86dd6a4a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p16 (void) +{ + poly8x16_t out_poly8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c new file mode 100644 index 000000000..9e70b8a07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p64 (void) +{ + poly8x16_t out_poly8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c new file mode 100644 index 000000000..608e27293 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s16 (void) +{ + poly8x16_t out_poly8x16_t; + int16x8_t arg0_int16x8_t; + + out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c new file mode 100644 index 000000000..7900676d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s32 (void) +{ + poly8x16_t out_poly8x16_t; + int32x4_t arg0_int32x4_t; + + out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c new file mode 100644 index 000000000..27483dcf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s64 (void) +{ + poly8x16_t out_poly8x16_t; + int64x2_t arg0_int64x2_t; + + out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c new file mode 100644 index 000000000..d4be56f6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s8 (void) +{ + poly8x16_t out_poly8x16_t; + int8x16_t arg0_int8x16_t; + + out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c new file mode 100644 index 000000000..c00a55fe0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u16 (void) +{ + poly8x16_t out_poly8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c new file mode 100644 index 000000000..e5b580b44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u32 (void) +{ + poly8x16_t out_poly8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c new file mode 100644 index 000000000..5e80ed7d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u64 (void) +{ + poly8x16_t out_poly8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c new file mode 100644 index 000000000..321e8f8dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c new file mode 100644 index 000000000..08d6b6afc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_f32 (void) +{ + int16x8_t out_int16x8_t; + float32x4_t arg0_float32x4_t; + + out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c new file mode 100644 index 000000000..77bfe3882 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p128 (void) +{ + int16x8_t out_int16x8_t; + poly128_t arg0_poly128_t; + + out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c new file mode 100644 index 000000000..1505b725e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p16 (void) +{ + int16x8_t out_int16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c new file mode 100644 index 000000000..41890f32a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p64 (void) +{ + int16x8_t out_int16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c new file mode 100644 index 000000000..48c54f212 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p8 (void) +{ + int16x8_t out_int16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c new file mode 100644 index 000000000..15f54fa94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s32 (void) +{ + int16x8_t out_int16x8_t; + int32x4_t arg0_int32x4_t; + + out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c new file mode 100644 index 000000000..eb8e53516 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s64 (void) +{ + int16x8_t out_int16x8_t; + int64x2_t arg0_int64x2_t; + + out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c new file mode 100644 index 000000000..f353c9268 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c new file mode 100644 index 000000000..8ea96b7b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c new file mode 100644 index 000000000..ac571b126 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u32 (void) +{ + int16x8_t out_int16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c new file mode 100644 index 000000000..73959abd9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u64 (void) +{ + int16x8_t out_int16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c new file mode 100644 index 000000000..45e85b131 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u8 (void) +{ + int16x8_t out_int16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c new file mode 100644 index 000000000..795db0753 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c new file mode 100644 index 000000000..9a179ae3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p128 (void) +{ + int32x4_t out_int32x4_t; + poly128_t arg0_poly128_t; + + out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c new file mode 100644 index 000000000..473c12350 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p16 (void) +{ + int32x4_t out_int32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c new file mode 100644 index 000000000..cc7ad95ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p64 (void) +{ + int32x4_t out_int32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c new file mode 100644 index 000000000..819e1d122 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p8 (void) +{ + int32x4_t out_int32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c new file mode 100644 index 000000000..7d2b5a0b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c new file mode 100644 index 000000000..8116033e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s64 (void) +{ + int32x4_t out_int32x4_t; + int64x2_t arg0_int64x2_t; + + out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c new file mode 100644 index 000000000..6786ddbfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s8 (void) +{ + int32x4_t out_int32x4_t; + int8x16_t arg0_int8x16_t; + + out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c new file mode 100644 index 000000000..104e22d68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u16 (void) +{ + int32x4_t out_int32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c new file mode 100644 index 000000000..8385fd8a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c new file mode 100644 index 000000000..90b91a74a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u64 (void) +{ + int32x4_t out_int32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c new file mode 100644 index 000000000..60ad32a44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u8 (void) +{ + int32x4_t out_int32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c new file mode 100644 index 000000000..212005fab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_f32 (void) +{ + int64x2_t out_int64x2_t; + float32x4_t arg0_float32x4_t; + + out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c new file mode 100644 index 000000000..adc1b9bbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p128 (void) +{ + int64x2_t out_int64x2_t; + poly128_t arg0_poly128_t; + + out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c new file mode 100644 index 000000000..0003a1f72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p16 (void) +{ + int64x2_t out_int64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c new file mode 100644 index 000000000..89ab9ccb4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p64 (void) +{ + int64x2_t out_int64x2_t; + poly64x2_t arg0_poly64x2_t; + + out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c new file mode 100644 index 000000000..02d7174b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p8 (void) +{ + int64x2_t out_int64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c new file mode 100644 index 000000000..26350eeb8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s16 (void) +{ + int64x2_t out_int64x2_t; + int16x8_t arg0_int16x8_t; + + out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c new file mode 100644 index 000000000..471db5cc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c new file mode 100644 index 000000000..903be8ff6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s8 (void) +{ + int64x2_t out_int64x2_t; + int8x16_t arg0_int8x16_t; + + out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c new file mode 100644 index 000000000..cbb49098f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u16 (void) +{ + int64x2_t out_int64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c new file mode 100644 index 000000000..882cf77bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u32 (void) +{ + int64x2_t out_int64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c new file mode 100644 index 000000000..f9bc43ae4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c new file mode 100644 index 000000000..3af2f0138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u8 (void) +{ + int64x2_t out_int64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c new file mode 100644 index 000000000..6a31442cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_f32 (void) +{ + int8x16_t out_int8x16_t; + float32x4_t arg0_float32x4_t; + + out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c new file mode 100644 index 000000000..d94090068 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p128 (void) +{ + int8x16_t out_int8x16_t; + poly128_t arg0_poly128_t; + + out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c new file mode 100644 index 000000000..6491c795a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p16 (void) +{ + int8x16_t out_int8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c new file mode 100644 index 000000000..a9adec387 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p64 (void) +{ + int8x16_t out_int8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c new file mode 100644 index 000000000..914321d55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p8 (void) +{ + int8x16_t out_int8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c new file mode 100644 index 000000000..fee5e2723 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s16 (void) +{ + int8x16_t out_int8x16_t; + int16x8_t arg0_int16x8_t; + + out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c new file mode 100644 index 000000000..2bf941aa5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s32 (void) +{ + int8x16_t out_int8x16_t; + int32x4_t arg0_int32x4_t; + + out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c new file mode 100644 index 000000000..1e6557174 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s64 (void) +{ + int8x16_t out_int8x16_t; + int64x2_t arg0_int64x2_t; + + out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c new file mode 100644 index 000000000..84b86eaae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u16 (void) +{ + int8x16_t out_int8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c new file mode 100644 index 000000000..e5f85ccd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u32 (void) +{ + int8x16_t out_int8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c new file mode 100644 index 000000000..9f299b366 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u64 (void) +{ + int8x16_t out_int8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c new file mode 100644 index 000000000..f04a53733 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c new file mode 100644 index 000000000..cb4a2e502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_f32 (void) +{ + uint16x8_t out_uint16x8_t; + float32x4_t arg0_float32x4_t; + + out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c new file mode 100644 index 000000000..792609246 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p128 (void) +{ + uint16x8_t out_uint16x8_t; + poly128_t arg0_poly128_t; + + out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c new file mode 100644 index 000000000..5667d60c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p16 (void) +{ + uint16x8_t out_uint16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c new file mode 100644 index 000000000..7a9b538f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p64 (void) +{ + uint16x8_t out_uint16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c new file mode 100644 index 000000000..d45442d9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p8 (void) +{ + uint16x8_t out_uint16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c new file mode 100644 index 000000000..9b6615909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c new file mode 100644 index 000000000..9a6d0f44a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s32 (void) +{ + uint16x8_t out_uint16x8_t; + int32x4_t arg0_int32x4_t; + + out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c new file mode 100644 index 000000000..c5a5378e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s64 (void) +{ + uint16x8_t out_uint16x8_t; + int64x2_t arg0_int64x2_t; + + out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c new file mode 100644 index 000000000..4ca22dceb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s8 (void) +{ + uint16x8_t out_uint16x8_t; + int8x16_t arg0_int8x16_t; + + out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c new file mode 100644 index 000000000..516c94957 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u32 (void) +{ + uint16x8_t out_uint16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c new file mode 100644 index 000000000..816da82c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u64 (void) +{ + uint16x8_t out_uint16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c new file mode 100644 index 000000000..ac5e98fa8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c new file mode 100644 index 000000000..7453f24b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c new file mode 100644 index 000000000..ce716b0ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p128 (void) +{ + uint32x4_t out_uint32x4_t; + poly128_t arg0_poly128_t; + + out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c new file mode 100644 index 000000000..27989c53c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p16 (void) +{ + uint32x4_t out_uint32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c new file mode 100644 index 000000000..a8b709e02 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p64 (void) +{ + uint32x4_t out_uint32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c new file mode 100644 index 000000000..2b3e01843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p8 (void) +{ + uint32x4_t out_uint32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c new file mode 100644 index 000000000..3a6f20f0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s16 (void) +{ + uint32x4_t out_uint32x4_t; + int16x8_t arg0_int16x8_t; + + out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c new file mode 100644 index 000000000..3079729aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c new file mode 100644 index 000000000..927cd3a60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s64 (void) +{ + uint32x4_t out_uint32x4_t; + int64x2_t arg0_int64x2_t; + + out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c new file mode 100644 index 000000000..5b546ccac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s8 (void) +{ + uint32x4_t out_uint32x4_t; + int8x16_t arg0_int8x16_t; + + out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c new file mode 100644 index 000000000..055739e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c new file mode 100644 index 000000000..ddf51f8ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u64 (void) +{ + uint32x4_t out_uint32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c new file mode 100644 index 000000000..2f860c193 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u8 (void) +{ + uint32x4_t out_uint32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c new file mode 100644 index 000000000..5224dcf87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_f32 (void) +{ + uint64x2_t out_uint64x2_t; + float32x4_t arg0_float32x4_t; + + out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c new file mode 100644 index 000000000..789973e0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p128 (void) +{ + uint64x2_t out_uint64x2_t; + poly128_t arg0_poly128_t; + + out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c new file mode 100644 index 000000000..fc592b78d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p16 (void) +{ + uint64x2_t out_uint64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c new file mode 100644 index 000000000..38071503e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p64 (void) +{ + uint64x2_t out_uint64x2_t; + poly64x2_t arg0_poly64x2_t; + + out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c new file mode 100644 index 000000000..503c44393 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p8 (void) +{ + uint64x2_t out_uint64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c new file mode 100644 index 000000000..430694abc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s16 (void) +{ + uint64x2_t out_uint64x2_t; + int16x8_t arg0_int16x8_t; + + out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c new file mode 100644 index 000000000..acfc69e74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s32 (void) +{ + uint64x2_t out_uint64x2_t; + int32x4_t arg0_int32x4_t; + + out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c new file mode 100644 index 000000000..033c6516e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c new file mode 100644 index 000000000..b6c312fbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s8 (void) +{ + uint64x2_t out_uint64x2_t; + int8x16_t arg0_int8x16_t; + + out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c new file mode 100644 index 000000000..dbe9d5160 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u16 (void) +{ + uint64x2_t out_uint64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c new file mode 100644 index 000000000..58b3c67e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c new file mode 100644 index 000000000..c20fef185 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u8 (void) +{ + uint64x2_t out_uint64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c new file mode 100644 index 000000000..f7b470415 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_f32 (void) +{ + uint8x16_t out_uint8x16_t; + float32x4_t arg0_float32x4_t; + + out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c new file mode 100644 index 000000000..54a832cf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p128 (void) +{ + uint8x16_t out_uint8x16_t; + poly128_t arg0_poly128_t; + + out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c new file mode 100644 index 000000000..758f10bea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p16 (void) +{ + uint8x16_t out_uint8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c new file mode 100644 index 000000000..3336e6c24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p64 (void) +{ + uint8x16_t out_uint8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c new file mode 100644 index 000000000..29f2aa19e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c new file mode 100644 index 000000000..1d79abb9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s16 (void) +{ + uint8x16_t out_uint8x16_t; + int16x8_t arg0_int16x8_t; + + out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c new file mode 100644 index 000000000..9f7c4f2f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s32 (void) +{ + uint8x16_t out_uint8x16_t; + int32x4_t arg0_int32x4_t; + + out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c new file mode 100644 index 000000000..a01fb1d1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s64 (void) +{ + uint8x16_t out_uint8x16_t; + int64x2_t arg0_int64x2_t; + + out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c new file mode 100644 index 000000000..0d65f31d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c new file mode 100644 index 000000000..dd9306192 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u16 (void) +{ + uint8x16_t out_uint8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c new file mode 100644 index 000000000..30f4b4559 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u32 (void) +{ + uint8x16_t out_uint8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c new file mode 100644 index 000000000..3f04c7192 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u64 (void) +{ + uint8x16_t out_uint8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c new file mode 100644 index 000000000..92ede4949 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p16 (void) +{ + float32x2_t out_float32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c new file mode 100644 index 000000000..e9714658f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p64 (void) +{ + float32x2_t out_float32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c new file mode 100644 index 000000000..ee2e6a92e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p8 (void) +{ + float32x2_t out_float32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c new file mode 100644 index 000000000..39ec36947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s16 (void) +{ + float32x2_t out_float32x2_t; + int16x4_t arg0_int16x4_t; + + out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c new file mode 100644 index 000000000..008598f14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c new file mode 100644 index 000000000..6a5ede493 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s64 (void) +{ + float32x2_t out_float32x2_t; + int64x1_t arg0_int64x1_t; + + out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c new file mode 100644 index 000000000..cc645e5d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s8 (void) +{ + float32x2_t out_float32x2_t; + int8x8_t arg0_int8x8_t; + + out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c new file mode 100644 index 000000000..fbb96790f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u16 (void) +{ + float32x2_t out_float32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c new file mode 100644 index 000000000..f87c885c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c new file mode 100644 index 000000000..610f77ad4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u64 (void) +{ + float32x2_t out_float32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c new file mode 100644 index 000000000..bfd81b171 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u8 (void) +{ + float32x2_t out_float32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c new file mode 100644 index 000000000..91508a6d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_f32 (void) +{ + poly16x4_t out_poly16x4_t; + float32x2_t arg0_float32x2_t; + + out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c new file mode 100644 index 000000000..4cd6818db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_p64 (void) +{ + poly16x4_t out_poly16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c new file mode 100644 index 000000000..a2f7207ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_p8 (void) +{ + poly16x4_t out_poly16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c new file mode 100644 index 000000000..3f22296cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s16 (void) +{ + poly16x4_t out_poly16x4_t; + int16x4_t arg0_int16x4_t; + + out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c new file mode 100644 index 000000000..393246cca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s32 (void) +{ + poly16x4_t out_poly16x4_t; + int32x2_t arg0_int32x2_t; + + out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c new file mode 100644 index 000000000..f5c99711a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s64 (void) +{ + poly16x4_t out_poly16x4_t; + int64x1_t arg0_int64x1_t; + + out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c new file mode 100644 index 000000000..6cf01b280 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s8 (void) +{ + poly16x4_t out_poly16x4_t; + int8x8_t arg0_int8x8_t; + + out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c new file mode 100644 index 000000000..4cdeeac44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c new file mode 100644 index 000000000..5b1094097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u32 (void) +{ + poly16x4_t out_poly16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c new file mode 100644 index 000000000..b036ff475 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u64 (void) +{ + poly16x4_t out_poly16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c new file mode 100644 index 000000000..d165cafb4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u8 (void) +{ + poly16x4_t out_poly16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c new file mode 100644 index 000000000..d9ecd6f88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_f32 (void) +{ + poly64x1_t out_poly64x1_t; + float32x2_t arg0_float32x2_t; + + out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c new file mode 100644 index 000000000..db437279b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_p16 (void) +{ + poly64x1_t out_poly64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c new file mode 100644 index 000000000..1fb0131d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_p8 (void) +{ + poly64x1_t out_poly64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c new file mode 100644 index 000000000..528db2d57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s16 (void) +{ + poly64x1_t out_poly64x1_t; + int16x4_t arg0_int16x4_t; + + out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c new file mode 100644 index 000000000..c6887d7e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s32 (void) +{ + poly64x1_t out_poly64x1_t; + int32x2_t arg0_int32x2_t; + + out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c new file mode 100644 index 000000000..f2b041649 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s64 (void) +{ + poly64x1_t out_poly64x1_t; + int64x1_t arg0_int64x1_t; + + out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c new file mode 100644 index 000000000..1866d19fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s8 (void) +{ + poly64x1_t out_poly64x1_t; + int8x8_t arg0_int8x8_t; + + out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c new file mode 100644 index 000000000..7903ec26f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u16 (void) +{ + poly64x1_t out_poly64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c new file mode 100644 index 000000000..3d8e9e40f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u32 (void) +{ + poly64x1_t out_poly64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c new file mode 100644 index 000000000..caa0464aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c new file mode 100644 index 000000000..47e1dfa5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u8 (void) +{ + poly64x1_t out_poly64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c new file mode 100644 index 000000000..b73599085 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_f32 (void) +{ + poly8x8_t out_poly8x8_t; + float32x2_t arg0_float32x2_t; + + out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c new file mode 100644 index 000000000..28a04a3e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_p16 (void) +{ + poly8x8_t out_poly8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c new file mode 100644 index 000000000..f5eff21ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_p64 (void) +{ + poly8x8_t out_poly8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c new file mode 100644 index 000000000..2a559c8d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s16 (void) +{ + poly8x8_t out_poly8x8_t; + int16x4_t arg0_int16x4_t; + + out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c new file mode 100644 index 000000000..a3c627085 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s32 (void) +{ + poly8x8_t out_poly8x8_t; + int32x2_t arg0_int32x2_t; + + out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c new file mode 100644 index 000000000..1a5cbbbcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s64 (void) +{ + poly8x8_t out_poly8x8_t; + int64x1_t arg0_int64x1_t; + + out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c new file mode 100644 index 000000000..0f8af3e5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s8 (void) +{ + poly8x8_t out_poly8x8_t; + int8x8_t arg0_int8x8_t; + + out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c new file mode 100644 index 000000000..f3cdaab48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u16 (void) +{ + poly8x8_t out_poly8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c new file mode 100644 index 000000000..210e063c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u32 (void) +{ + poly8x8_t out_poly8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c new file mode 100644 index 000000000..bf83e5df9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u64 (void) +{ + poly8x8_t out_poly8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c new file mode 100644 index 000000000..17d8d8c87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c new file mode 100644 index 000000000..380947bcc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_f32 (void) +{ + int16x4_t out_int16x4_t; + float32x2_t arg0_float32x2_t; + + out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c new file mode 100644 index 000000000..3742001b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p16 (void) +{ + int16x4_t out_int16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c new file mode 100644 index 000000000..127865d16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p64 (void) +{ + int16x4_t out_int16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c new file mode 100644 index 000000000..5970dc86c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p8 (void) +{ + int16x4_t out_int16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c new file mode 100644 index 000000000..bee17e4c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s32 (void) +{ + int16x4_t out_int16x4_t; + int32x2_t arg0_int32x2_t; + + out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c new file mode 100644 index 000000000..4a8feda9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s64 (void) +{ + int16x4_t out_int16x4_t; + int64x1_t arg0_int64x1_t; + + out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c new file mode 100644 index 000000000..e079c6158 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c new file mode 100644 index 000000000..cf86bd4a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c new file mode 100644 index 000000000..853e7ab2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u32 (void) +{ + int16x4_t out_int16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c new file mode 100644 index 000000000..a72786ded --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u64 (void) +{ + int16x4_t out_int16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c new file mode 100644 index 000000000..9c8459e46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u8 (void) +{ + int16x4_t out_int16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c new file mode 100644 index 000000000..73fe251e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c new file mode 100644 index 000000000..36df97c5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p16 (void) +{ + int32x2_t out_int32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c new file mode 100644 index 000000000..f8be30b92 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p64 (void) +{ + int32x2_t out_int32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c new file mode 100644 index 000000000..54e9dee78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p8 (void) +{ + int32x2_t out_int32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c new file mode 100644 index 000000000..f5e3fb6fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c new file mode 100644 index 000000000..f1430843f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s64 (void) +{ + int32x2_t out_int32x2_t; + int64x1_t arg0_int64x1_t; + + out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c new file mode 100644 index 000000000..a336577d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s8 (void) +{ + int32x2_t out_int32x2_t; + int8x8_t arg0_int8x8_t; + + out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c new file mode 100644 index 000000000..2f078613e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u16 (void) +{ + int32x2_t out_int32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c new file mode 100644 index 000000000..4087e9c78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c new file mode 100644 index 000000000..826bb8efb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u64 (void) +{ + int32x2_t out_int32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c new file mode 100644 index 000000000..31589a8a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u8 (void) +{ + int32x2_t out_int32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c new file mode 100644 index 000000000..0096e368a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_f32 (void) +{ + int64x1_t out_int64x1_t; + float32x2_t arg0_float32x2_t; + + out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c new file mode 100644 index 000000000..bdbe4302f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p16 (void) +{ + int64x1_t out_int64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c new file mode 100644 index 000000000..5f7c17bd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p64 (void) +{ + int64x1_t out_int64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c new file mode 100644 index 000000000..76da59f39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p8 (void) +{ + int64x1_t out_int64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c new file mode 100644 index 000000000..0f978f390 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s16 (void) +{ + int64x1_t out_int64x1_t; + int16x4_t arg0_int16x4_t; + + out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c new file mode 100644 index 000000000..aefa689a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c new file mode 100644 index 000000000..a7e0adad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s8 (void) +{ + int64x1_t out_int64x1_t; + int8x8_t arg0_int8x8_t; + + out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c new file mode 100644 index 000000000..110818567 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u16 (void) +{ + int64x1_t out_int64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c new file mode 100644 index 000000000..978a6e480 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u32 (void) +{ + int64x1_t out_int64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c new file mode 100644 index 000000000..0546f26dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c new file mode 100644 index 000000000..601b5988d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u8 (void) +{ + int64x1_t out_int64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c new file mode 100644 index 000000000..05d921d7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_f32 (void) +{ + int8x8_t out_int8x8_t; + float32x2_t arg0_float32x2_t; + + out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c new file mode 100644 index 000000000..38e812a16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p16 (void) +{ + int8x8_t out_int8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c new file mode 100644 index 000000000..8345963ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p64 (void) +{ + int8x8_t out_int8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c new file mode 100644 index 000000000..402484411 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p8 (void) +{ + int8x8_t out_int8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c new file mode 100644 index 000000000..df368e370 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s16 (void) +{ + int8x8_t out_int8x8_t; + int16x4_t arg0_int16x4_t; + + out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c new file mode 100644 index 000000000..caefc38dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s32 (void) +{ + int8x8_t out_int8x8_t; + int32x2_t arg0_int32x2_t; + + out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c new file mode 100644 index 000000000..a8c7c333e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s64 (void) +{ + int8x8_t out_int8x8_t; + int64x1_t arg0_int64x1_t; + + out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c new file mode 100644 index 000000000..dbd1eec43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u16 (void) +{ + int8x8_t out_int8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c new file mode 100644 index 000000000..40e1475ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u32 (void) +{ + int8x8_t out_int8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c new file mode 100644 index 000000000..6d53d41e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u64 (void) +{ + int8x8_t out_int8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c new file mode 100644 index 000000000..8f31a4c76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c new file mode 100644 index 000000000..f960624d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_f32 (void) +{ + uint16x4_t out_uint16x4_t; + float32x2_t arg0_float32x2_t; + + out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c new file mode 100644 index 000000000..e787a969e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p16 (void) +{ + uint16x4_t out_uint16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c new file mode 100644 index 000000000..34f920bbd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p64 (void) +{ + uint16x4_t out_uint16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c new file mode 100644 index 000000000..c332e9450 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p8 (void) +{ + uint16x4_t out_uint16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c new file mode 100644 index 000000000..d72ec3452 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c new file mode 100644 index 000000000..b6d86c011 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x2_t arg0_int32x2_t; + + out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c new file mode 100644 index 000000000..87f494bec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s64 (void) +{ + uint16x4_t out_uint16x4_t; + int64x1_t arg0_int64x1_t; + + out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c new file mode 100644 index 000000000..11695c169 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s8 (void) +{ + uint16x4_t out_uint16x4_t; + int8x8_t arg0_int8x8_t; + + out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c new file mode 100644 index 000000000..9f0171a05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c new file mode 100644 index 000000000..0db76c692 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u64 (void) +{ + uint16x4_t out_uint16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c new file mode 100644 index 000000000..71b555ac5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c new file mode 100644 index 000000000..813b8b961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c new file mode 100644 index 000000000..3662cc3cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p16 (void) +{ + uint32x2_t out_uint32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c new file mode 100644 index 000000000..b5f24fbc4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p64 (void) +{ + uint32x2_t out_uint32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c new file mode 100644 index 000000000..73ddff115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p8 (void) +{ + uint32x2_t out_uint32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c new file mode 100644 index 000000000..02ec84c91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s16 (void) +{ + uint32x2_t out_uint32x2_t; + int16x4_t arg0_int16x4_t; + + out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c new file mode 100644 index 000000000..2a964c830 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c new file mode 100644 index 000000000..ad9493856 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x1_t arg0_int64x1_t; + + out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c new file mode 100644 index 000000000..8ff896e70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s8 (void) +{ + uint32x2_t out_uint32x2_t; + int8x8_t arg0_int8x8_t; + + out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c new file mode 100644 index 000000000..5c4883422 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c new file mode 100644 index 000000000..8fd55f24b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c new file mode 100644 index 000000000..ab192091d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u8 (void) +{ + uint32x2_t out_uint32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c new file mode 100644 index 000000000..7ded8687a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_f32 (void) +{ + uint64x1_t out_uint64x1_t; + float32x2_t arg0_float32x2_t; + + out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c new file mode 100644 index 000000000..c48213439 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p16 (void) +{ + uint64x1_t out_uint64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c new file mode 100644 index 000000000..741912a4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p64 (void) +{ + uint64x1_t out_uint64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c new file mode 100644 index 000000000..858af4624 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p8 (void) +{ + uint64x1_t out_uint64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c new file mode 100644 index 000000000..e07c4e83e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s16 (void) +{ + uint64x1_t out_uint64x1_t; + int16x4_t arg0_int16x4_t; + + out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c new file mode 100644 index 000000000..0fa51a1a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s32 (void) +{ + uint64x1_t out_uint64x1_t; + int32x2_t arg0_int32x2_t; + + out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c new file mode 100644 index 000000000..1f1f62e43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c new file mode 100644 index 000000000..299b45ce5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s8 (void) +{ + uint64x1_t out_uint64x1_t; + int8x8_t arg0_int8x8_t; + + out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c new file mode 100644 index 000000000..dd2c1550d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u16 (void) +{ + uint64x1_t out_uint64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c new file mode 100644 index 000000000..8dbe9e200 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c new file mode 100644 index 000000000..fe0724a8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u8 (void) +{ + uint64x1_t out_uint64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c new file mode 100644 index 000000000..e82cba753 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_f32 (void) +{ + uint8x8_t out_uint8x8_t; + float32x2_t arg0_float32x2_t; + + out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c new file mode 100644 index 000000000..08516125c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p16 (void) +{ + uint8x8_t out_uint8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c new file mode 100644 index 000000000..907b67c15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p64 (void) +{ + uint8x8_t out_uint8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c new file mode 100644 index 000000000..91d3d0eaa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c new file mode 100644 index 000000000..50a2cd187 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x4_t arg0_int16x4_t; + + out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c new file mode 100644 index 000000000..a5db01b62 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s32 (void) +{ + uint8x8_t out_uint8x8_t; + int32x2_t arg0_int32x2_t; + + out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c new file mode 100644 index 000000000..f906e018b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s64 (void) +{ + uint8x8_t out_uint8x8_t; + int64x1_t arg0_int64x1_t; + + out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c new file mode 100644 index 000000000..bd2ba481f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c new file mode 100644 index 000000000..eb38ca82f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c new file mode 100644 index 000000000..6fb11b26f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u32 (void) +{ + uint8x8_t out_uint8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c new file mode 100644 index 000000000..cf7ff27ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u64 (void) +{ + uint8x8_t out_uint8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c new file mode 100644 index 000000000..b815c199f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c new file mode 100644 index 000000000..7167fec30 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c new file mode 100644 index 000000000..d43613079 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c new file mode 100644 index 000000000..15086d584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c new file mode 100644 index 000000000..b2c7ca88e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev16_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c new file mode 100644 index 000000000..10ba66f7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c new file mode 100644 index 000000000..af213d91e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c new file mode 100644 index 000000000..926068f10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c new file mode 100644 index 000000000..bfd8ec2e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c new file mode 100644 index 000000000..74fc2470d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c new file mode 100644 index 000000000..cf0220a86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c new file mode 100644 index 000000000..ad5dba31c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c new file mode 100644 index 000000000..93f19405e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c new file mode 100644 index 000000000..b19ce01c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c new file mode 100644 index 000000000..08bf6f258 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev32_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c new file mode 100644 index 000000000..47b8a591d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev32_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c new file mode 100644 index 000000000..928c1d45c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c new file mode 100644 index 000000000..ac5c63690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c new file mode 100644 index 000000000..c9ab7008d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c new file mode 100644 index 000000000..2d5d2f86b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c new file mode 100644 index 000000000..019b6d419 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c new file mode 100644 index 000000000..5923b2d2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c new file mode 100644 index 000000000..93ffd5818 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c new file mode 100644 index 000000000..9353e7057 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c new file mode 100644 index 000000000..590d833fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c new file mode 100644 index 000000000..014da6812 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c new file mode 100644 index 000000000..4b7d8e495 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c new file mode 100644 index 000000000..3ea280e90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64f32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrev64_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c new file mode 100644 index 000000000..1b30d60e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c new file mode 100644 index 000000000..370f49854 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c new file mode 100644 index 000000000..ee4206ba7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev64_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c new file mode 100644 index 000000000..f7057ce49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrev64_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c new file mode 100644 index 000000000..c073b0b68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev64_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c new file mode 100644 index 000000000..4fdd2697c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c new file mode 100644 index 000000000..61d21b69d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c new file mode 100644 index 000000000..71a6af177 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c new file mode 100644 index 000000000..02ca46509 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrnda_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c new file mode 100644 index 000000000..b94165735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrnd_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c new file mode 100644 index 000000000..7f4e90bf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndmf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndmf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndm_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c new file mode 100644 index 000000000..df8e3e934 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndnf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndn_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c new file mode 100644 index 000000000..d3900cd78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndpf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndp_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c new file mode 100644 index 000000000..b7b5d73c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqaf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqa_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c new file mode 100644 index 000000000..08b4b45f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c new file mode 100644 index 000000000..6d16bfc93 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqmf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqmf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqm_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c new file mode 100644 index 000000000..b31ca95db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqnf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqn_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c new file mode 100644 index 000000000..5c4a86690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqpf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqp_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c new file mode 100644 index 000000000..05b92b0aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c new file mode 100644 index 000000000..5d51dec60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c new file mode 100644 index 000000000..6e1bf7532 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrtef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c new file mode 100644 index 000000000..1e4908e46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c new file mode 100644 index 000000000..ee38e04fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c @@ -0,0 +1,21 @@ +/* Test the `vrsqrtsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c new file mode 100644 index 000000000..36cb69def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c @@ -0,0 +1,21 @@ +/* Test the `vrsqrtsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c new file mode 100644 index 000000000..c6b18495e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c new file mode 100644 index 000000000..dda571aaf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c new file mode 100644 index 000000000..873c8cfe4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c new file mode 100644 index 000000000..f6ade301c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c new file mode 100644 index 000000000..c825da15e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c new file mode 100644 index 000000000..af8f2853c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c new file mode 100644 index 000000000..55dca359b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c new file mode 100644 index 000000000..f671e1e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c new file mode 100644 index 000000000..27a0f7225 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c new file mode 100644 index 000000000..b30b26748 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c new file mode 100644 index 000000000..d6e5817d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c new file mode 100644 index 000000000..340614cd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c new file mode 100644 index 000000000..d02118a25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c new file mode 100644 index 000000000..e63a197df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c new file mode 100644 index 000000000..6f4f4d379 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c new file mode 100644 index 000000000..77c22056b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c new file mode 100644 index 000000000..5c5454f98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c new file mode 100644 index 000000000..fd09e21d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c new file mode 100644 index 000000000..783cc82c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c new file mode 100644 index 000000000..0d5a89ec1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c new file mode 100644 index 000000000..3bff5d232 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c new file mode 100644 index 000000000..0e4853190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c new file mode 100644 index 000000000..31344a6e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c new file mode 100644 index 000000000..dd11cd54b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c new file mode 100644 index 000000000..2fdbc0d01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c new file mode 100644 index 000000000..078ffd41b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c new file mode 100644 index 000000000..a330ae3d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c new file mode 100644 index 000000000..cdf26269a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c new file mode 100644 index 000000000..70fe6ccf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c new file mode 100644 index 000000000..06e6b52d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c new file mode 100644 index 000000000..ed3d4a4a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c new file mode 100644 index 000000000..6413ef8d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c new file mode 100644 index 000000000..8dc0bd470 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c new file mode 100644 index 000000000..58a6dbb97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c new file mode 100644 index 000000000..584ef1270 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c new file mode 100644 index 000000000..77e6e0160 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c new file mode 100644 index 000000000..6138ad3dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c new file mode 100644 index 000000000..65bfdb1d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c new file mode 100644 index 000000000..59a91bdec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c new file mode 100644 index 000000000..66f4c3119 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c new file mode 100644 index 000000000..f7a49f4bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c new file mode 100644 index 000000000..634e66739 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c new file mode 100644 index 000000000..7d71f84f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c new file mode 100644 index 000000000..ae1f85ae9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c new file mode 100644 index 000000000..c4e11a18b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c new file mode 100644 index 000000000..12378ebfe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c new file mode 100644 index 000000000..cc2c7d5f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c new file mode 100644 index 000000000..6591e42c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c new file mode 100644 index 000000000..94d904506 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c new file mode 100644 index 000000000..eabc7928c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c new file mode 100644 index 000000000..f205caf00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c new file mode 100644 index 000000000..bf8240fde --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c new file mode 100644 index 000000000..2c8941f9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c @@ -0,0 +1,21 @@ +/* Test the `vshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c new file mode 100644 index 000000000..fb6be6ea0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c @@ -0,0 +1,21 @@ +/* Test the `vshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c new file mode 100644 index 000000000..b5a61033f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c @@ -0,0 +1,21 @@ +/* Test the `vshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c new file mode 100644 index 000000000..a807191ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c @@ -0,0 +1,21 @@ +/* Test the `vshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c new file mode 100644 index 000000000..14f2428d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c new file mode 100644 index 000000000..596327584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c new file mode 100644 index 000000000..f29dedc14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c new file mode 100644 index 000000000..1b900396b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c new file mode 100644 index 000000000..286edb14b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c new file mode 100644 index 000000000..d47d574e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c new file mode 100644 index 000000000..66b693e73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c new file mode 100644 index 000000000..f92da931d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c new file mode 100644 index 000000000..8f81e7896 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c new file mode 100644 index 000000000..e5fbf44f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c new file mode 100644 index 000000000..a8ff5f7d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c new file mode 100644 index 000000000..673d90e4f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c new file mode 100644 index 000000000..0a14a00df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c new file mode 100644 index 000000000..545478909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c new file mode 100644 index 000000000..3fd27fc98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c new file mode 100644 index 000000000..069978d47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c new file mode 100644 index 000000000..43c610b62 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c new file mode 100644 index 000000000..1b7bb5d33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c new file mode 100644 index 000000000..a78b9fcf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c new file mode 100644 index 000000000..cdb968693 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c new file mode 100644 index 000000000..832dc831a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c new file mode 100644 index 000000000..314ba2516 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c new file mode 100644 index 000000000..465592a65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c new file mode 100644 index 000000000..614451a68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c new file mode 100644 index 000000000..6fe4066ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c new file mode 100644 index 000000000..901b17c31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c new file mode 100644 index 000000000..601ee13c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c new file mode 100644 index 000000000..cbb47285e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsliQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c new file mode 100644 index 000000000..8e5a256e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c new file mode 100644 index 000000000..d3c67ac77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c new file mode 100644 index 000000000..12b69848f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c new file mode 100644 index 000000000..441996f8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c new file mode 100644 index 000000000..8f393b4c9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c new file mode 100644 index 000000000..0936eb759 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c new file mode 100644 index 000000000..23b1dddcf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c new file mode 100644 index 000000000..b14a16592 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c new file mode 100644 index 000000000..d6a86a6e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c new file mode 100644 index 000000000..30d206e79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c new file mode 100644 index 000000000..801add49b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsli_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c new file mode 100644 index 000000000..ffcacb25b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c new file mode 100644 index 000000000..1d58cc7ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c new file mode 100644 index 000000000..1920c9115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c new file mode 100644 index 000000000..4bef7bc91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c new file mode 100644 index 000000000..7b0260f4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c new file mode 100644 index 000000000..addda9c20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c new file mode 100644 index 000000000..0bdaef3a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c new file mode 100644 index 000000000..3733d7055 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c new file mode 100644 index 000000000..020e5959b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c new file mode 100644 index 000000000..d1f6100e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c new file mode 100644 index 000000000..9d44cca6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c new file mode 100644 index 000000000..bcda76849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c new file mode 100644 index 000000000..0dbf181c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c new file mode 100644 index 000000000..4b6553314 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c new file mode 100644 index 000000000..721459583 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c new file mode 100644 index 000000000..8a982d205 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c new file mode 100644 index 000000000..523e5a09b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c new file mode 100644 index 000000000..37c97c562 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c new file mode 100644 index 000000000..e79430804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c new file mode 100644 index 000000000..6381a13e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c new file mode 100644 index 000000000..6f46eef22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c new file mode 100644 index 000000000..42ad77321 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c new file mode 100644 index 000000000..baaab7e48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c new file mode 100644 index 000000000..dc63a5ad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c new file mode 100644 index 000000000..5555f75d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c new file mode 100644 index 000000000..39a96c080 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c new file mode 100644 index 000000000..d2e48165a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsriQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c new file mode 100644 index 000000000..d17d7e724 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c new file mode 100644 index 000000000..c7375409c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c new file mode 100644 index 000000000..1b17696aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c new file mode 100644 index 000000000..d959c341b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c new file mode 100644 index 000000000..b04c800cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c new file mode 100644 index 000000000..2d3f1d6b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c new file mode 100644 index 000000000..19c87fec7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c new file mode 100644 index 000000000..b747b2237 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c new file mode 100644 index 000000000..1e949e5e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c new file mode 100644 index 000000000..a1aac08f1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c new file mode 100644 index 000000000..0abffc2e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsri_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c new file mode 100644 index 000000000..bd102bf98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c new file mode 100644 index 000000000..bb0687220 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c new file mode 100644 index 000000000..8712857ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c new file mode 100644 index 000000000..f54fca4dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c new file mode 100644 index 000000000..405e03522 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c new file mode 100644 index 000000000..4c751e792 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c new file mode 100644 index 000000000..b82f63b59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c new file mode 100644 index 000000000..20381bfd2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c new file mode 100644 index 000000000..87293317c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c new file mode 100644 index 000000000..1f95128e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c new file mode 100644 index 000000000..90e7ccc1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c new file mode 100644 index 000000000..74a198baf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x2_t arg1_poly64x2_t; + + vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c new file mode 100644 index 000000000..6abb646c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c new file mode 100644 index 000000000..ec283e228 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c new file mode 100644 index 000000000..6e73d6e11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c new file mode 100644 index 000000000..46d369c99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c new file mode 100644 index 000000000..d7b3a1c12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c new file mode 100644 index 000000000..27958f6d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c new file mode 100644 index 000000000..b4aa760e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c new file mode 100644 index 000000000..5f4c927b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c @@ -0,0 +1,25 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ + +/* Detect ICE in the case of unaligned memory address. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +unsigned char dummy_store[1000]; + +void +foo (char* addr) +{ + uint8x16_t vdata = vld1q_u8 (addr); + vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0); +} + +uint64_t +bar (uint64x2_t vdata) +{ + vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0); + return vgetq_lane_u64 (vdata, 0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c new file mode 100644 index 000000000..54faaa3fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c new file mode 100644 index 000000000..9b09e72c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c new file mode 100644 index 000000000..a4b3d8a1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c new file mode 100644 index 000000000..9b4873371 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c new file mode 100644 index 000000000..7d1e020f1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1Qp64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x2_t arg1_poly64x2_t; + + vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c new file mode 100644 index 000000000..f3843399e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c new file mode 100644 index 000000000..e6c39cf35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c new file mode 100644 index 000000000..587dcf0ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c new file mode 100644 index 000000000..50511d1ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c new file mode 100644 index 000000000..2de9814b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c new file mode 100644 index 000000000..81d8cc5ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c new file mode 100644 index 000000000..408c6b29e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c new file mode 100644 index 000000000..1c17e5b0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c new file mode 100644 index 000000000..1605e2756 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c new file mode 100644 index 000000000..781703140 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c new file mode 100644 index 000000000..c6a19daf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c new file mode 100644 index 000000000..f8c70c359 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1_lanep64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1_t arg1_poly64x1_t; + + vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c new file mode 100644 index 000000000..1b5dd4f77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c new file mode 100644 index 000000000..4efdc5024 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c new file mode 100644 index 000000000..9c3c1354c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c new file mode 100644 index 000000000..64fed4a10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c new file mode 100644 index 000000000..59646f8a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c new file mode 100644 index 000000000..6ae716647 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c new file mode 100644 index 000000000..369abf7fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c new file mode 100644 index 000000000..7296fee8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c new file mode 100644 index 000000000..ba6076e1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c new file mode 100644 index 000000000..f3460f5e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c @@ -0,0 +1,20 @@ +/* Test the `vst1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1f32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_f32 (arg0_float32_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c new file mode 100644 index 000000000..7504c5cf8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c @@ -0,0 +1,20 @@ +/* Test the `vst1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c new file mode 100644 index 000000000..7329fba9d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c @@ -0,0 +1,20 @@ +/* Test the `vst1p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1_t arg1_poly64x1_t; + + vst1_p64 (arg0_poly64_t, arg1_poly64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c new file mode 100644 index 000000000..3059aac60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c @@ -0,0 +1,20 @@ +/* Test the `vst1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c new file mode 100644 index 000000000..fbddb2fd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c @@ -0,0 +1,20 @@ +/* Test the `vst1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_s16 (arg0_int16_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c new file mode 100644 index 000000000..f264db036 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c @@ -0,0 +1,20 @@ +/* Test the `vst1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_s32 (arg0_int32_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c new file mode 100644 index 000000000..64de48bb0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c @@ -0,0 +1,20 @@ +/* Test the `vst1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_s64 (arg0_int64_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c new file mode 100644 index 000000000..7916448d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c @@ -0,0 +1,20 @@ +/* Test the `vst1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_s8 (arg0_int8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c new file mode 100644 index 000000000..797aef16f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c @@ -0,0 +1,20 @@ +/* Test the `vst1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c new file mode 100644 index 000000000..563ea9dc3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c @@ -0,0 +1,20 @@ +/* Test the `vst1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c new file mode 100644 index 000000000..b95f5d587 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c @@ -0,0 +1,20 @@ +/* Test the `vst1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c new file mode 100644 index 000000000..75358e769 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c @@ -0,0 +1,20 @@ +/* Test the `vst1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c new file mode 100644 index 000000000..485735632 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c new file mode 100644 index 000000000..bed15034c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c new file mode 100644 index 000000000..57867352f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c new file mode 100644 index 000000000..cf0dc15dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c new file mode 100644 index 000000000..b751e6b97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c new file mode 100644 index 000000000..b5fbe0e28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c new file mode 100644 index 000000000..56f9adcda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c new file mode 100644 index 000000000..184199033 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c new file mode 100644 index 000000000..2d98ec910 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x2_t arg1_poly8x16x2_t; + + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c new file mode 100644 index 000000000..39395f6d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c new file mode 100644 index 000000000..1768d4786 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c new file mode 100644 index 000000000..423cb8c8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x2_t arg1_int8x16x2_t; + + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c new file mode 100644 index 000000000..a25958a72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c new file mode 100644 index 000000000..47722b352 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c new file mode 100644 index 000000000..b79478026 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x2_t arg1_uint8x16x2_t; + + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c new file mode 100644 index 000000000..e7752920e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c new file mode 100644 index 000000000..be9913b39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c new file mode 100644 index 000000000..0a95e268d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c new file mode 100644 index 000000000..728593ccb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c new file mode 100644 index 000000000..32d49b58c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c new file mode 100644 index 000000000..9e67eb323 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c new file mode 100644 index 000000000..d56f20961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c new file mode 100644 index 000000000..053704cea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c new file mode 100644 index 000000000..a35360088 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c new file mode 100644 index 000000000..b43c4135b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c @@ -0,0 +1,20 @@ +/* Test the `vst2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c new file mode 100644 index 000000000..1d112ff65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c @@ -0,0 +1,20 @@ +/* Test the `vst2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c new file mode 100644 index 000000000..3ccaa5464 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c @@ -0,0 +1,20 @@ +/* Test the `vst2p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst2p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x2_t arg1_poly64x1x2_t; + + vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c new file mode 100644 index 000000000..59c4d62e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c @@ -0,0 +1,20 @@ +/* Test the `vst2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c new file mode 100644 index 000000000..eb6cb59a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c @@ -0,0 +1,20 @@ +/* Test the `vst2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c new file mode 100644 index 000000000..a17b58dc4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c @@ -0,0 +1,20 @@ +/* Test the `vst2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c new file mode 100644 index 000000000..668ae50a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c @@ -0,0 +1,20 @@ +/* Test the `vst2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x2_t arg1_int64x1x2_t; + + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c new file mode 100644 index 000000000..343414e34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c @@ -0,0 +1,20 @@ +/* Test the `vst2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c new file mode 100644 index 000000000..903279d0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c @@ -0,0 +1,20 @@ +/* Test the `vst2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c new file mode 100644 index 000000000..1396ed119 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c @@ -0,0 +1,20 @@ +/* Test the `vst2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c new file mode 100644 index 000000000..006e31f25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c @@ -0,0 +1,20 @@ +/* Test the `vst2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x2_t arg1_uint64x1x2_t; + + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c new file mode 100644 index 000000000..55cd34779 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c @@ -0,0 +1,20 @@ +/* Test the `vst2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c new file mode 100644 index 000000000..8e4f0dca9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c new file mode 100644 index 000000000..f8fcb977f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c new file mode 100644 index 000000000..3fde1a3af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c new file mode 100644 index 000000000..1eb428922 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c new file mode 100644 index 000000000..ca98dded6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c new file mode 100644 index 000000000..a2a59d7a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c new file mode 100644 index 000000000..b4b480fb7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c new file mode 100644 index 000000000..aa34886f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c new file mode 100644 index 000000000..b13fcd7e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x3_t arg1_poly8x16x3_t; + + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c new file mode 100644 index 000000000..6cac405f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c new file mode 100644 index 000000000..3c8437094 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c new file mode 100644 index 000000000..fee56af42 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x3_t arg1_int8x16x3_t; + + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c new file mode 100644 index 000000000..af3910b7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c new file mode 100644 index 000000000..8828885af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c new file mode 100644 index 000000000..c273fe6dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x3_t arg1_uint8x16x3_t; + + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c new file mode 100644 index 000000000..de654e907 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c new file mode 100644 index 000000000..de733ff67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c new file mode 100644 index 000000000..a9a26447f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c new file mode 100644 index 000000000..a98b40714 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c new file mode 100644 index 000000000..5b2450c67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c new file mode 100644 index 000000000..8cd04f716 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c new file mode 100644 index 000000000..692058d91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c new file mode 100644 index 000000000..32a5193a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c new file mode 100644 index 000000000..952ffcbec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c new file mode 100644 index 000000000..e80b8e916 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c @@ -0,0 +1,20 @@ +/* Test the `vst3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c new file mode 100644 index 000000000..1d7831264 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c @@ -0,0 +1,20 @@ +/* Test the `vst3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c new file mode 100644 index 000000000..73ced9544 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c @@ -0,0 +1,20 @@ +/* Test the `vst3p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst3p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x3_t arg1_poly64x1x3_t; + + vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c new file mode 100644 index 000000000..ca8c5ec43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c @@ -0,0 +1,20 @@ +/* Test the `vst3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c new file mode 100644 index 000000000..5c1bcf9de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c @@ -0,0 +1,20 @@ +/* Test the `vst3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c new file mode 100644 index 000000000..3f5a3aad1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c @@ -0,0 +1,20 @@ +/* Test the `vst3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c new file mode 100644 index 000000000..8c6a851db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c @@ -0,0 +1,20 @@ +/* Test the `vst3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x3_t arg1_int64x1x3_t; + + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c new file mode 100644 index 000000000..8853fbaf5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c @@ -0,0 +1,20 @@ +/* Test the `vst3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c new file mode 100644 index 000000000..e17c6c8d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c @@ -0,0 +1,20 @@ +/* Test the `vst3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c new file mode 100644 index 000000000..3b7d8ce20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c @@ -0,0 +1,20 @@ +/* Test the `vst3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c new file mode 100644 index 000000000..08d9c7a08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c @@ -0,0 +1,20 @@ +/* Test the `vst3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x3_t arg1_uint64x1x3_t; + + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c new file mode 100644 index 000000000..78944cba0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c @@ -0,0 +1,20 @@ +/* Test the `vst3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c new file mode 100644 index 000000000..adbb4d569 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c new file mode 100644 index 000000000..587477c87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c new file mode 100644 index 000000000..3febdf7d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c new file mode 100644 index 000000000..71406af83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c new file mode 100644 index 000000000..1229c86a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c new file mode 100644 index 000000000..5e0683f30 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c new file mode 100644 index 000000000..2ecb6b173 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c new file mode 100644 index 000000000..a9b9b7ca9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c new file mode 100644 index 000000000..17142c1a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x4_t arg1_poly8x16x4_t; + + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c new file mode 100644 index 000000000..8511619fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c new file mode 100644 index 000000000..f65894eab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c new file mode 100644 index 000000000..a74d58b5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x4_t arg1_int8x16x4_t; + + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c new file mode 100644 index 000000000..b124c7cc9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c new file mode 100644 index 000000000..fa7d2130d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c new file mode 100644 index 000000000..d853b12bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x4_t arg1_uint8x16x4_t; + + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c new file mode 100644 index 000000000..acef9f0a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c new file mode 100644 index 000000000..64e4713ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c new file mode 100644 index 000000000..1ac58df28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c new file mode 100644 index 000000000..e7e1e2aea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c new file mode 100644 index 000000000..2c99611a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c new file mode 100644 index 000000000..7eebc1644 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c new file mode 100644 index 000000000..decc7caf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c new file mode 100644 index 000000000..4cfeddbbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c new file mode 100644 index 000000000..217ced27a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c new file mode 100644 index 000000000..931b8ed15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c @@ -0,0 +1,20 @@ +/* Test the `vst4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c new file mode 100644 index 000000000..ea58c44fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c @@ -0,0 +1,20 @@ +/* Test the `vst4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c new file mode 100644 index 000000000..b9f7b168d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c @@ -0,0 +1,20 @@ +/* Test the `vst4p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst4p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x4_t arg1_poly64x1x4_t; + + vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c new file mode 100644 index 000000000..95e5ccdf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c @@ -0,0 +1,20 @@ +/* Test the `vst4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c new file mode 100644 index 000000000..7811d74c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c @@ -0,0 +1,20 @@ +/* Test the `vst4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c new file mode 100644 index 000000000..f93ea4097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c @@ -0,0 +1,20 @@ +/* Test the `vst4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c new file mode 100644 index 000000000..796762a3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c @@ -0,0 +1,20 @@ +/* Test the `vst4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x4_t arg1_int64x1x4_t; + + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c new file mode 100644 index 000000000..877e2c407 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c @@ -0,0 +1,20 @@ +/* Test the `vst4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c new file mode 100644 index 000000000..5de43f591 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c @@ -0,0 +1,20 @@ +/* Test the `vst4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c new file mode 100644 index 000000000..1ae9e5e60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c @@ -0,0 +1,20 @@ +/* Test the `vst4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c new file mode 100644 index 000000000..2453d6bd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c @@ -0,0 +1,20 @@ +/* Test the `vst4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x4_t arg1_uint64x1x4_t; + + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c new file mode 100644 index 000000000..380acc647 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c @@ -0,0 +1,20 @@ +/* Test the `vst4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c new file mode 100644 index 000000000..88caa2898 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c new file mode 100644 index 000000000..d33790b9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c new file mode 100644 index 000000000..77b2a743f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c new file mode 100644 index 000000000..1b0c5a198 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c new file mode 100644 index 000000000..11b2f6a8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c new file mode 100644 index 000000000..e3f750406 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c new file mode 100644 index 000000000..5fe1d0b4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c new file mode 100644 index 000000000..19536b992 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c new file mode 100644 index 000000000..c9f5d95b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c new file mode 100644 index 000000000..442828abd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c @@ -0,0 +1,21 @@ +/* Test the `vsubf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c new file mode 100644 index 000000000..06e6189be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c new file mode 100644 index 000000000..42e8b5740 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c new file mode 100644 index 000000000..f314a40d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c new file mode 100644 index 000000000..5c3f82624 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c new file mode 100644 index 000000000..1bd62fc15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c new file mode 100644 index 000000000..35fa65afa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c new file mode 100644 index 000000000..1db042d94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c @@ -0,0 +1,21 @@ +/* Test the `vsubls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c new file mode 100644 index 000000000..e8acf9240 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c @@ -0,0 +1,21 @@ +/* Test the `vsubls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c new file mode 100644 index 000000000..7b457cadb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c @@ -0,0 +1,21 @@ +/* Test the `vsubls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c new file mode 100644 index 000000000..b9cc873ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c @@ -0,0 +1,21 @@ +/* Test the `vsublu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c new file mode 100644 index 000000000..afb456e65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c @@ -0,0 +1,21 @@ +/* Test the `vsublu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c new file mode 100644 index 000000000..890925437 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c @@ -0,0 +1,21 @@ +/* Test the `vsublu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c new file mode 100644 index 000000000..0638a7dfe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c new file mode 100644 index 000000000..0c9b6a360 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c new file mode 100644 index 000000000..57bcd33d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c @@ -0,0 +1,20 @@ +/* Test the `vsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c new file mode 100644 index 000000000..cb927d615 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c new file mode 100644 index 000000000..80985e247 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c new file mode 100644 index 000000000..47d595ba1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c new file mode 100644 index 000000000..3a8ae462e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c @@ -0,0 +1,20 @@ +/* Test the `vsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c new file mode 100644 index 000000000..b359e1655 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c new file mode 100644 index 000000000..90cbe20a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c @@ -0,0 +1,21 @@ +/* Test the `vsubws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c new file mode 100644 index 000000000..963e5933c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c @@ -0,0 +1,21 @@ +/* Test the `vsubws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c new file mode 100644 index 000000000..103b8fcb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c @@ -0,0 +1,21 @@ +/* Test the `vsubws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c new file mode 100644 index 000000000..98e5cdac3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c new file mode 100644 index 000000000..ccd2a7b09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c new file mode 100644 index 000000000..c89e73331 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c new file mode 100644 index 000000000..225159c3a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c new file mode 100644 index 000000000..a8ecd46e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c new file mode 100644 index 000000000..1d2ea7d0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c new file mode 100644 index 000000000..bb748f95b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x2_t arg0_poly8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c new file mode 100644 index 000000000..29dc16190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x2_t arg0_int8x8x2_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c new file mode 100644 index 000000000..493538461 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x2_t arg0_uint8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c new file mode 100644 index 000000000..4bc77fa1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x3_t arg0_poly8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c new file mode 100644 index 000000000..f088f3777 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x3_t arg0_int8x8x3_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c new file mode 100644 index 000000000..3f84d0062 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x3_t arg0_uint8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c new file mode 100644 index 000000000..2cdc37d04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x4_t arg0_poly8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c new file mode 100644 index 000000000..870c9bd4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x4_t arg0_int8x8x4_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c new file mode 100644 index 000000000..461fc9569 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x4_t arg0_uint8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c new file mode 100644 index 000000000..a081f169e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c new file mode 100644 index 000000000..400ef33ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c new file mode 100644 index 000000000..da4a65d43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c new file mode 100644 index 000000000..ffc07b470 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x2_t arg1_poly8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c new file mode 100644 index 000000000..96c9104a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x2_t arg1_int8x8x2_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c new file mode 100644 index 000000000..4b5606448 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x2_t arg1_uint8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c new file mode 100644 index 000000000..8f06ef92e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x3_t arg1_poly8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c new file mode 100644 index 000000000..996277476 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x3_t arg1_int8x8x3_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c new file mode 100644 index 000000000..b6785512a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x3_t arg1_uint8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c new file mode 100644 index 000000000..c021cf823 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x4_t arg1_poly8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c new file mode 100644 index 000000000..c06b1aaf9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x4_t arg1_int8x8x4_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c new file mode 100644 index 000000000..e43ca46f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x4_t arg1_uint8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c new file mode 100644 index 000000000..690fa19d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c new file mode 100644 index 000000000..58f156eab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c new file mode 100644 index 000000000..0819bfbf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c new file mode 100644 index 000000000..dc4f76e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c new file mode 100644 index 000000000..fe71416de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c new file mode 100644 index 000000000..5ddd827d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c new file mode 100644 index 000000000..1d66dae84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c new file mode 100644 index 000000000..2712dd513 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c new file mode 100644 index 000000000..58f6f64e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c new file mode 100644 index 000000000..c5a301b99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c new file mode 100644 index 000000000..b970a6a26 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c new file mode 100644 index 000000000..615bd5750 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c new file mode 100644 index 000000000..068720c86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c @@ -0,0 +1,21 @@ +/* Test the `vtrns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c new file mode 100644 index 000000000..f01047497 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c @@ -0,0 +1,21 @@ +/* Test the `vtrns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c new file mode 100644 index 000000000..bf900a107 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c @@ -0,0 +1,21 @@ +/* Test the `vtrns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c new file mode 100644 index 000000000..aa98b4026 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c new file mode 100644 index 000000000..74f5cace6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c new file mode 100644 index 000000000..f4766be76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c new file mode 100644 index 000000000..69e876328 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c new file mode 100644 index 000000000..a41fd7df9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c new file mode 100644 index 000000000..b5e46b442 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c new file mode 100644 index 000000000..f3bf7004a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c new file mode 100644 index 000000000..7024ebe1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c new file mode 100644 index 000000000..717ffd1ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c new file mode 100644 index 000000000..bc3729961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c new file mode 100644 index 000000000..6bd7cae15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c @@ -0,0 +1,21 @@ +/* Test the `vtstp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c new file mode 100644 index 000000000..1637af486 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c @@ -0,0 +1,21 @@ +/* Test the `vtsts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c new file mode 100644 index 000000000..e8037b977 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c @@ -0,0 +1,21 @@ +/* Test the `vtsts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c new file mode 100644 index 000000000..ec3379adb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c @@ -0,0 +1,21 @@ +/* Test the `vtsts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c new file mode 100644 index 000000000..629855f61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c @@ -0,0 +1,21 @@ +/* Test the `vtstu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c new file mode 100644 index 000000000..a8b774b7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c @@ -0,0 +1,21 @@ +/* Test the `vtstu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c new file mode 100644 index 000000000..51480d8ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c @@ -0,0 +1,21 @@ +/* Test the `vtstu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c new file mode 100644 index 000000000..2f429394e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c new file mode 100644 index 000000000..31760090a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c new file mode 100644 index 000000000..e5d7a2de5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c new file mode 100644 index 000000000..b0a427e4d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c new file mode 100644 index 000000000..b883174b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c new file mode 100644 index 000000000..84d2a8afb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c new file mode 100644 index 000000000..f583a5082 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c new file mode 100644 index 000000000..3c96ef362 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c new file mode 100644 index 000000000..f385a56ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c new file mode 100644 index 000000000..ca92c7e9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c new file mode 100644 index 000000000..cf2b796ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c new file mode 100644 index 000000000..da46ec058 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c new file mode 100644 index 000000000..4d0a90670 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c @@ -0,0 +1,21 @@ +/* Test the `vuzps16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c new file mode 100644 index 000000000..b337fad20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c @@ -0,0 +1,21 @@ +/* Test the `vuzps32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c new file mode 100644 index 000000000..73da12852 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c @@ -0,0 +1,21 @@ +/* Test the `vuzps8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c new file mode 100644 index 000000000..259a141e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c new file mode 100644 index 000000000..1d5fae6a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c new file mode 100644 index 000000000..e5e368039 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c new file mode 100644 index 000000000..fee46b793 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c new file mode 100644 index 000000000..1a0b0803e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c new file mode 100644 index 000000000..c0cca6074 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c new file mode 100644 index 000000000..2979d1a0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c new file mode 100644 index 000000000..4a96c4aa3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c new file mode 100644 index 000000000..718756774 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c new file mode 100644 index 000000000..b4641de3a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c new file mode 100644 index 000000000..c8fee60c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c new file mode 100644 index 000000000..eee6bc54f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c new file mode 100644 index 000000000..6c13a07ad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c @@ -0,0 +1,21 @@ +/* Test the `vzipf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c new file mode 100644 index 000000000..726500ed3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c @@ -0,0 +1,21 @@ +/* Test the `vzipp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c new file mode 100644 index 000000000..4a5dd76b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c @@ -0,0 +1,21 @@ +/* Test the `vzipp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c new file mode 100644 index 000000000..795bab6d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c @@ -0,0 +1,21 @@ +/* Test the `vzips16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c new file mode 100644 index 000000000..663985ebe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c @@ -0,0 +1,21 @@ +/* Test the `vzips32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c new file mode 100644 index 000000000..cca6933aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c @@ -0,0 +1,21 @@ +/* Test the `vzips8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c new file mode 100644 index 000000000..53822f93a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c @@ -0,0 +1,21 @@ +/* Test the `vzipu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c new file mode 100644 index 000000000..d9a280bf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c @@ -0,0 +1,21 @@ +/* Test the `vzipu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c new file mode 100644 index 000000000..056898939 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c @@ -0,0 +1,21 @@ +/* Test the `vzipu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ |