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authorRong Xu <xur@google.com>2014-07-21 23:47:22 (GMT)
committerRong Xu <xur@google.com>2014-07-29 22:31:03 (GMT)
commit38a8aecfb882072900434499696b5c32a2274515 (patch)
tree2aac97f0ae24b03cd98c1a06e989c031c173f889 /gcc-4.9/gcc/testsuite/gcc.target
parentc231900e5dcc14d8296bd9f62b45997a49d4d5e7 (diff)
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[4.9] Switch gcc-4.9 to use google/gcc-4_9 branch.
This source drop uses svn version r212828 of google/gcc-4.9 branch. We also cherry-picked r213062, r213063 and r213064 to fix windows build issues. All gcc-4.9 patches before July 3rd are ported to google/gcc-4.9. The following prior commits has not been merged to google branch yet. (They are included in this commit). e7af147f979e657fe2df00808e5b4319b0e088c6, baf87df3cb2683649ba7e9872362a7e721117c23, and c231900e5dcc14d8296bd9f62b45997a49d4d5e7. Change-Id: I4bea3ea470387ff751c2be4cb0d4a12059b9299b
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c59
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c39
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c19
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c36
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/alpha/pr61586.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/avr/pr60991.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61055.c88
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61443.c134
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr57233.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr57233.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-pr57233.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map3
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp36
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-1.c23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-2.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-3.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-4.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-5.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-6.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-7.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-8.c29
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-no-patching.c27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-patching.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-sibling-call.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr57233.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60868.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60901.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60902.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-1.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-2.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61423.c38
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61446.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-1.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pr57233.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unaligned-mov.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/vec-may_alias.c25
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pr57233.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-1.c27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-2.c44
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-3.c103
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c88
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c88
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-ttest.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack01.c91
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack02.c96
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack03.c88
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60735.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math1.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math2.c73
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c55
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c2
137 files changed, 2551 insertions, 186 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
index a95d06a..07e56ff 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
@@ -34,6 +34,13 @@ struct hfa_fx2_t
float b;
};
+struct hfa_fx3_t
+{
+ float a;
+ float b;
+ float c;
+};
+
struct hfa_dx2_t
{
double a;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c
new file mode 100644
index 0000000..ae1e3ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c
@@ -0,0 +1,59 @@
+/* Test AAPCS64 layout and __builtin_va_start.
+
+ Pass named HFA/HVA argument on stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-13.c"
+
+struct float_float_t
+{
+ float a;
+ float b;
+} float_float;
+
+union float_int_t
+{
+ float b8;
+ int b5;
+} float_int;
+
+#define HAS_DATA_INIT_FUNC
+void
+init_data ()
+{
+ float_float.a = 1.2f;
+ float_float.b = 2.2f;
+
+ float_int.b8 = 4983.80f;
+}
+
+#include "abitest.h"
+#else
+ ARG (float, 1.0f, S0, 0)
+ ARG (float, 2.0f, S1, 1)
+ ARG (float, 3.0f, S2, 2)
+ ARG (float, 4.0f, S3, 3)
+ ARG (float, 5.0f, S4, 4)
+ ARG (float, 6.0f, S5, 5)
+ ARG (float, 7.0f, S6, 6)
+ ARG (struct float_float_t, float_float, STACK, 7)
+ ARG (int, 9, W0, 8)
+ ARG (int, 10, W1, 9)
+ ARG (int, 11, W2, 10)
+ ARG (int, 12, W3, 11)
+ ARG (int, 13, W4, 12)
+ ARG (int, 14, W5, 13)
+ ARG (int, 15, W6, LAST_NAMED_ARG_ID)
+ DOTS
+ /* Note on the reason of using 'X7' instead of 'W7' here:
+ Using 'X7' makes sure the test works in the big-endian mode.
+ According to PCS rules B.4 and C.10, the size of float_int is rounded
+ to 8 bytes and prepared in the register X7 as if loaded via LDR from
+ the memory, with the content of the other 4 bytes unspecified. The
+ test framework will only compare the 4 relavent bytes. */
+ ANON (union float_int_t, float_int, X7, 15)
+ LAST_ANON (long long, 12683143434LL, STACK + 8, 16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c
new file mode 100644
index 0000000..91080d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c
@@ -0,0 +1,35 @@
+/* Test AAPCS64 layout and __builtin_va_start.
+
+ Pass named HFA/HVA argument on stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-14.c"
+#include "type-def.h"
+
+struct hfa_fx2_t hfa_fx2 = {1.2f, 2.2f};
+struct hfa_fx3_t hfa_fx3 = {3.2f, 4.2f, 5.2f};
+vf4_t float32x4 = {6.2f, 7.2f, 8.2f, 9.2f};
+vf4_t float32x4_2 = {10.2f, 11.2f, 12.2f, 13.2f};
+
+#include "abitest.h"
+#else
+ ARG (float, 1.0f, S0, 0)
+ ARG (float, 2.0f, S1, 1)
+ ARG (float, 3.0f, S2, 2)
+ ARG (float, 4.0f, S3, 3)
+ ARG (float, 5.0f, S4, 4)
+ ARG (float, 6.0f, S5, 5)
+ ARG (float, 7.0f, S6, 6)
+ ARG (struct hfa_fx3_t, hfa_fx3, STACK, 7)
+ /* Previous argument size has been rounded up to the nearest multiple of
+ 8 bytes. */
+ ARG (struct hfa_fx2_t, hfa_fx2, STACK + 16, 8)
+ /* NSAA is rounded up to the nearest natural alignment of float32x4. */
+ ARG (vf4_t, float32x4, STACK + 32, 9)
+ ARG (vf4_t, float32x4_2, STACK + 48, LAST_NAMED_ARG_ID)
+ DOTS
+ LAST_ANON (double, 123456789.987, STACK + 64, 11)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c
new file mode 100644
index 0000000..d8fdb32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c
@@ -0,0 +1,39 @@
+/* Test AAPCS64 layout and __builtin_va_start.
+
+ Pass named __128int argument on stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-15.c"
+#include "type-def.h"
+
+union int128_t qword;
+
+#define HAS_DATA_INIT_FUNC
+void
+init_data ()
+{
+ /* Init signed quad-word integer. */
+ qword.l64 = 0xfdb9753102468aceLL;
+ qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+ ARG (int, 1, W0, 0)
+ ARG (int, 2, W1, 1)
+ ARG (int, 3, W2, 2)
+ ARG (int, 4, W3, 3)
+ ARG (int, 5, W4, 4)
+ ARG (int, 6, W5, 5)
+ ARG (int, 7, W6, 6)
+ ARG (__int128, qword.i, STACK, LAST_NAMED_ARG_ID)
+ DOTS
+#ifndef __AAPCS64_BIG_ENDIAN__
+ LAST_ANON (int, 8, STACK + 16, 8)
+#else
+ LAST_ANON (int, 8, STACK + 20, 8)
+#endif
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c
new file mode 100644
index 0000000..45ece53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+typedef unsigned int wchar_t;
+typedef long unsigned int size_t;
+
+size_t
+wcstombs(char *s , const wchar_t *pwcs , size_t n)
+{
+ int count = 0;
+
+ if (n != 0) {
+ do {
+ if ((*s++ = (char) *pwcs++) == 0)
+ break;
+ count++;
+ } while (--n != 0);
+ }
+ return count;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index aa041cc..782f6d1 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -387,7 +387,7 @@ test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
int32x1_t
-test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
{
return vqdmlalh_lane_s16 (a, b, c, 3);
}
@@ -403,7 +403,7 @@ test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
{
return vqdmlals_lane_s32 (a, b, c, 1);
}
@@ -419,7 +419,7 @@ test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
int32x1_t
-test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
{
return vqdmlslh_lane_s16 (a, b, c, 3);
}
@@ -435,7 +435,7 @@ test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
{
return vqdmlsls_lane_s32 (a, b, c, 1);
}
@@ -451,7 +451,7 @@ test_vqdmulhh_s16 (int16x1_t a, int16x1_t b)
/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
int16x1_t
-test_vqdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+test_vqdmulhh_lane_s16 (int16x1_t a, int16x4_t b)
{
return vqdmulhh_lane_s16 (a, b, 3);
}
@@ -467,9 +467,9 @@ test_vqdmulhs_s32 (int32x1_t a, int32x1_t b)
/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
int32x1_t
-test_vqdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+test_vqdmulhs_lane_s32 (int32x1_t a, int32x2_t b)
{
- return vqdmulhs_lane_s32 (a, b, 3);
+ return vqdmulhs_lane_s32 (a, b, 1);
}
/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
@@ -483,7 +483,7 @@ test_vqdmullh_s16 (int16x1_t a, int16x1_t b)
/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
int32x1_t
-test_vqdmullh_lane_s16 (int16x1_t a, int16x8_t b)
+test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b)
{
return vqdmullh_lane_s16 (a, b, 3);
}
@@ -499,7 +499,7 @@ test_vqdmulls_s32 (int32x1_t a, int32x1_t b)
/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmulls_lane_s32 (int32x1_t a, int32x4_t b)
+test_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b)
{
return vqdmulls_lane_s32 (a, b, 1);
}
@@ -515,9 +515,9 @@ test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b)
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
int16x1_t
-test_vqrdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+test_vqrdmulhh_lane_s16 (int16x1_t a, int16x4_t b)
{
- return vqrdmulhh_lane_s16 (a, b, 6);
+ return vqrdmulhh_lane_s16 (a, b, 3);
}
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
@@ -531,9 +531,9 @@ test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b)
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
int32x1_t
-test_vqrdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+test_vqrdmulhs_lane_s32 (int32x1_t a, int32x2_t b)
{
- return vqrdmulhs_lane_s32 (a, b, 2);
+ return vqrdmulhs_lane_s32 (a, b, 1);
}
/* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
index affb8a8..52b0496 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
-#include "../../../config/aarch64/arm_neon.h"
+#include "arm_neon.h"
/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
@@ -305,7 +305,7 @@ test_vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
int32x4_t
-test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c)
{
return vqdmlal_high_lane_s16 (a, b, c, 3);
}
@@ -361,7 +361,7 @@ test_vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
int64x2_t
-test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c)
{
return vqdmlal_high_lane_s32 (__a, __b, __c, 1);
}
@@ -417,7 +417,7 @@ test_vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
int32x4_t
-test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c)
{
return vqdmlsl_high_lane_s16 (a, b, c, 3);
}
@@ -473,7 +473,7 @@ test_vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
int64x2_t
-test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c)
{
return vqdmlsl_high_lane_s32 (__a, __b, __c, 1);
}
@@ -529,7 +529,7 @@ test_vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
int32x4_t
-test_vqdmull_high_lane_s16 (int16x8_t a, int16x8_t b)
+test_vqdmull_high_lane_s16 (int16x8_t a, int16x4_t b)
{
return vqdmull_high_lane_s16 (a, b, 3);
}
@@ -585,7 +585,7 @@ test_vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
int64x2_t
-test_vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b)
+test_vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b)
{
return vqdmull_high_lane_s32 (__a, __b, 1);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c
new file mode 100644
index 0000000..1388c3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_high_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c)
+{
+ return vqdmlal_high_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c
new file mode 100644
index 0000000..f90387d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_high_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlal_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t c)
+{
+ return vqdmlal_high_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c
new file mode 100644
index 0000000..5399ce9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_high_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlal_high_laneq_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c
new file mode 100644
index 0000000..e4b5558
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_high_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlal_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+{
+ return vqdmlal_high_laneq_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c
new file mode 100644
index 0000000..7e60c82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+ return vqdmlal_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c
new file mode 100644
index 0000000..c0f508d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlal_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+{
+ return vqdmlal_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c
new file mode 100644
index 0000000..9bf1304
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c)
+{
+ return vqdmlal_laneq_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c
new file mode 100644
index 0000000..5fd9c56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlal_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlal_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t c)
+{
+ return vqdmlal_laneq_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c
new file mode 100644
index 0000000..83f5af5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlalh_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x1_t
+t_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+{
+ return vqdmlalh_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c
new file mode 100644
index 0000000..ef94e95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlals_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x1_t
+t_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+{
+ return vqdmlals_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c
new file mode 100644
index 0000000..276a1a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_high_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c)
+{
+ return vqdmlsl_high_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c
new file mode 100644
index 0000000..2ae58ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_high_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlsl_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t c)
+{
+ return vqdmlsl_high_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c
new file mode 100644
index 0000000..1db5db4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_high_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlsl_high_laneq_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c
new file mode 100644
index 0000000..3a72a7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_high_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlsl_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+{
+ return vqdmlsl_high_laneq_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c
new file mode 100644
index 0000000..0535378
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+ return vqdmlsl_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c
new file mode 100644
index 0000000..b52e51e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+{
+ return vqdmlsl_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c
new file mode 100644
index 0000000..7009a35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsl_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x4_t c)
+{
+ return vqdmlsl_laneq_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c
new file mode 100644
index 0000000..056dfbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlslh_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x1_t
+t_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+{
+ return vqdmlslh_lane_s16 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c
new file mode 100644
index 0000000..9e351bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmlsls_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x1_t
+t_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+{
+ return vqdmlsls_lane_s32 (a, b, c, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c
new file mode 100644
index 0000000..d3c699b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmulh_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int16x4_t
+t_vqdmulh_laneq_s16 (int16x4_t a, int16x8_t b)
+{
+ return vqdmulh_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c
new file mode 100644
index 0000000..c6202ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmulh_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x2_t
+t_vqdmulh_laneq_s32 (int32x2_t a, int32x4_t b)
+{
+ return vqdmulh_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c
new file mode 100644
index 0000000..7635851
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c
@@ -0,0 +1,36 @@
+/* Test the vqdmulhh_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+ int16_t arg1;
+ int16x4_t arg2;
+ int16_t result;
+ int16_t actual;
+ int16_t expected;
+
+ arg1 = -32768;
+ arg2 = vcreate_s16 (0x0000ffff2489e398ULL);
+ actual = vqdmulhh_lane_s16 (arg1, arg2, 2);
+ expected = 1;
+
+ if (expected != actual)
+ {
+ fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual);
+ abort ();
+ }
+
+ return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[hH\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[2\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c
new file mode 100644
index 0000000..809c85a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmulhq_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int16x8_t
+t_vqdmulhq_laneq_s16 (int16x8_t a, int16x8_t b)
+{
+ return vqdmulhq_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c
new file mode 100644
index 0000000..d375fe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmulhq_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmulhq_laneq_s32 (int32x4_t a, int32x4_t b)
+{
+ return vqdmulhq_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c
new file mode 100644
index 0000000..9c27f5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c
@@ -0,0 +1,34 @@
+/* Test the vqdmulhs_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+ int32_t arg1;
+ int32x2_t arg2;
+ int32_t result;
+ int32_t actual;
+ int32_t expected;
+
+ arg1 = 57336;
+ arg2 = vcreate_s32 (0x55897fff7fff0000ULL);
+ actual = vqdmulhs_lane_s32 (arg1, arg2, 0);
+ expected = 57334;
+
+ if (expected != actual)
+ {
+ fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual);
+ abort ();
+ }
+
+ return 0;
+}
+/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c
new file mode 100644
index 0000000..0af320e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_high_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmull_high_lane_s16 (int16x8_t a, int16x4_t b)
+{
+ return vqdmull_high_lane_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c
new file mode 100644
index 0000000..583e8a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_high_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmull_high_lane_s32 (int32x4_t a, int32x2_t b)
+{
+ return vqdmull_high_lane_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c
new file mode 100644
index 0000000..dcfd14c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_high_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t b)
+{
+ return vqdmull_high_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c
new file mode 100644
index 0000000..3e8b652
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_high_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmull_high_laneq_s32 (int32x4_t a, int32x4_t b)
+{
+ return vqdmull_high_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c
new file mode 100644
index 0000000..695d4e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmull_lane_s16 (int16x4_t a, int16x4_t b)
+{
+ return vqdmull_lane_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c
new file mode 100644
index 0000000..e6a02b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmull_lane_s32 (int32x2_t a, int32x2_t b)
+{
+ return vqdmull_lane_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c
new file mode 100644
index 0000000..ba761b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqdmull_laneq_s16 (int16x4_t a, int16x8_t b)
+{
+ return vqdmull_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c
new file mode 100644
index 0000000..82b8e19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmull_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x2_t
+t_vqdmull_laneq_s32 (int32x2_t a, int32x4_t b)
+{
+ return vqdmull_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c
new file mode 100644
index 0000000..fd271e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqdmullh_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x1_t
+t_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b)
+{
+ return vqdmullh_lane_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c
new file mode 100644
index 0000000..1103333
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqdmulls_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64x1_t
+t_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b)
+{
+ return vqdmulls_lane_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c
new file mode 100644
index 0000000..0313f1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqrdmulh_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int16x4_t
+t_vqrdmulh_laneq_s16 (int16x4_t a, int16x8_t b)
+{
+ return vqrdmulh_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c
new file mode 100644
index 0000000..a9124ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqrdmulh_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x2_t
+t_vqrdmulh_laneq_s32 (int32x2_t a, int32x4_t b)
+{
+ return vqrdmulh_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c
new file mode 100644
index 0000000..f21863a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c
@@ -0,0 +1,35 @@
+/* Test the vqrdmulhh_lane_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+ int16_t arg1;
+ int16x4_t arg2;
+ int16_t result;
+ int16_t actual;
+ int16_t expected;
+
+ arg1 = -32768;
+ arg2 = vcreate_s16 (0xd78e000005d78000ULL);
+ actual = vqrdmulhh_lane_s16 (arg1, arg2, 3);
+ expected = 10354;
+
+ if (expected != actual)
+ {
+ fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual);
+ abort ();
+ }
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[hH\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[3\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c
new file mode 100644
index 0000000..488e694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c
@@ -0,0 +1,15 @@
+/* Test the vqrdmulhq_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int16x8_t
+t_vqrdmulhq_laneq_s16 (int16x8_t a, int16x8_t b)
+{
+ return vqrdmulhq_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c
new file mode 100644
index 0000000..42519f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c
@@ -0,0 +1,15 @@
+/* Test the vqrdmulhq_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+t_vqrdmulhq_laneq_s32 (int32x4_t a, int32x4_t b)
+{
+ return vqrdmulhq_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c
new file mode 100644
index 0000000..83d2ba2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c
@@ -0,0 +1,35 @@
+/* Test the vqrdmulhs_lane_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+ int32_t arg1;
+ int32x2_t arg2;
+ int32_t result;
+ int32_t actual;
+ int32_t expected;
+
+ arg1 = -2099281921;
+ arg2 = vcreate_s32 (0x000080007fff0000ULL);
+ actual = vqrdmulhs_lane_s32 (arg1, arg2, 1);
+ expected = -32033;
+
+ if (expected != actual)
+ {
+ fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual);
+ abort ();
+ }
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[1\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr61586.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr61586.c
new file mode 100644
index 0000000..afb1af3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr61586.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mieee" } */
+
+void foo (int *dimensions, double **params, int hh)
+{
+ if (params[hh])
+ ;
+ else if (dimensions[hh] > 0)
+ params[hh][0] = 1.0f;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c
index 17f729b..250d5e4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c
@@ -15,7 +15,6 @@ int main(void)
uint8x8x2_t vd1, vd2;
union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
int i;
- uint8_t odd, even;
vd1 = vzip_u8(v1, vdup_n_u8(0));
vd2 = vzip_u8(v2, vdup_n_u8(0));
@@ -25,17 +24,9 @@ int main(void)
vst1_u8(d3.buf, vd2.val[0]);
vst1_u8(d4.buf, vd2.val[1]);
-#ifdef __ARMEL__
- odd = 1;
- even = 0;
-#else
- odd = 0;
- even = 1;
-#endif
-
for (i = 0; i < 8; i++)
- if ((i % 2 == even && d4.buf[i] != 2)
- || (i % 2 == odd && d4.buf[i] != 0))
+ if ((i % 2 == 0 && d4.buf[i] != 2)
+ || (i % 2 == 1 && d4.buf[i] != 0))
abort ();
return 0;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/pr60991.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr60991.c
new file mode 100644
index 0000000..a09f42a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr60991.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O1" } */
+
+/* This testcase (simplified from the original bug report) exposes
+ PR60991. The code generated for writing the __int24 value corrupts
+ the frame pointer if the offset is <= 63 + MAX_LD_OFFSET */
+
+#include <stdlib.h>
+
+int main(void)
+{
+ volatile char junk[62];
+ junk[0] = 5;
+ volatile __int24 staticConfig = 0;
+
+ if (junk[0] != 5)
+ abort();
+
+ exit(0);
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61055.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61055.c
new file mode 100644
index 0000000..9dd1f42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61055.c
@@ -0,0 +1,88 @@
+/* { dg-do run } */
+/* { dg-options { -fno-peephole2 } } */
+
+#include <stdlib.h>
+
+typedef __UINT16_TYPE__ uint16_t;
+typedef __INT16_TYPE__ int16_t;
+typedef __UINT8_TYPE__ uint8_t;
+
+uint8_t __attribute__((noinline,noclone))
+fun_inc (uint8_t c0)
+{
+ register uint8_t c asm ("r15") = c0;
+
+ /* Force target value into R15 (lower register) */
+ asm ("" : "+l" (c));
+
+ c++;
+ if (c >= 0x80)
+ c = 0;
+
+ asm ("" : "+l" (c));
+
+ return c;
+}
+
+uint8_t __attribute__((noinline,noclone))
+fun_dec (uint8_t c0)
+{
+ register uint8_t c asm ("r15") = c0;
+
+ /* Force target value into R15 (lower register) */
+ asm ("" : "+l" (c));
+
+ c--;
+ if (c < 0x80)
+ c = 0;
+
+ asm ("" : "+l" (c));
+
+ return c;
+}
+
+
+uint8_t __attribute__((noinline,noclone))
+fun_neg (uint8_t c0)
+{
+ register uint8_t c asm ("r15") = c0;
+
+ c = -c;
+ if (c >= 0x80)
+ c = 0;
+
+ return c;
+}
+
+uint16_t __attribute__((noinline,noclone))
+fun_adiw (uint16_t c0)
+{
+ register uint16_t c asm ("r24") = c0;
+
+ /* Force target value into R24 (for ADIW) */
+ asm ("" : "+r" (c));
+
+ c += 2;
+ if (c >= 0x8000)
+ c = 0;
+
+ asm ("" : "+r" (c));
+
+ return c;
+}
+
+
+int main()
+{
+ if (fun_inc (0x7f) != 0)
+ abort();
+
+ if (fun_neg (0x80) != 0)
+ abort();
+
+ if (fun_adiw (0x7ffe) != 0)
+ abort();
+
+ exit (0);
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61443.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61443.c
new file mode 100644
index 0000000..12c6bca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr61443.c
@@ -0,0 +1,134 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define NC __attribute__((noinline,noclone))
+
+void NC vfun (char n, ...)
+{
+ va_list ap;
+
+ va_start (ap, n);
+
+ switch (n)
+ {
+ default:
+ abort();
+ case 1:
+ if (11 != va_arg (ap, int))
+ abort();
+ break;
+ case 2:
+ if (2222 != va_arg (ap, int))
+ abort();
+ break;
+ case 3:
+ if (333333 != va_arg (ap, __int24))
+ abort();
+ break;
+ case 4:
+ if (44444444 != va_arg (ap, long))
+ abort();
+ break;
+ case 8:
+ if (8888888888888888 != va_arg (ap, long long))
+ abort();
+ break;
+ }
+
+ va_end (ap);
+}
+
+
+void NC boo_qi (const __flash char *p)
+{
+ vfun (1, *p);
+}
+
+void NC boox_qi (const __memx char *p)
+{
+ vfun (1, *p);
+}
+
+void NC boo_hi (const __flash int *p)
+{
+ vfun (2, *p);
+}
+
+void NC boox_hi (const __memx int *p)
+{
+ vfun (2, *p);
+}
+
+void NC boo_psi (const __flash __int24 *p)
+{
+ vfun (3, *p);
+}
+
+void NC boox_psi (const __memx __int24 *p)
+{
+ vfun (3, *p);
+}
+
+void NC boo_si (const __flash long *p)
+{
+ vfun (4, *p);
+}
+
+void NC boox_si (const __memx long *p)
+{
+ vfun (4, *p);
+}
+
+void NC boo_di (const __flash long long *p)
+{
+ vfun (8, *p);
+}
+
+void NC boox_di (const __memx long long *p)
+{
+ vfun (8, *p);
+}
+
+const __flash char f_qi = 11;
+const __flash int f_hi = 2222;
+const __flash __int24 f_psi = 333333;
+const __flash long f_si = 44444444;
+const __flash long long f_di = 8888888888888888;
+
+const __memx char x_qi = 11;
+const __memx int x_hi = 2222;
+const __memx __int24 x_psi = 333333;
+const __memx long x_si = 44444444;
+const __memx long long x_di = 8888888888888888;
+
+char r_qi = 11;
+int r_hi = 2222;
+__int24 r_psi = 333333;
+long r_si = 44444444;
+long long r_di = 8888888888888888;
+
+int main (void)
+{
+ boo_qi (&f_qi);
+ boo_hi (&f_hi);
+ boo_psi (&f_psi);
+ boo_si (&f_si);
+ boo_di (&f_di);
+
+ boox_qi (&x_qi);
+ boox_hi (&x_hi);
+ boox_psi (&x_psi);
+ boox_si (&x_si);
+ boox_di (&x_di);
+
+ boox_qi (&r_qi);
+ boox_hi (&r_hi);
+ boox_psi (&r_psi);
+ boox_si (&r_si);
+ boox_di (&r_di);
+
+ exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr57233.c
new file mode 100644
index 0000000..ffc71d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr57233.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/57233 */
+/* { dg-do run { target avx } } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test (void)
+{
+ do_main ();
+}
+
+#undef main
+#define main() do_main ()
+
+#include "../../gcc.dg/pr57233.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr57233.c
new file mode 100644
index 0000000..3fb2608
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr57233.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/57233 */
+/* { dg-do run { target avx2 } } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+ do_main ();
+}
+
+#undef main
+#define main() do_main ()
+
+#include "../../gcc.dg/pr57233.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
index ee1f313..4b249c3 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
index 7e7e018..889bd9f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
index 4d61d7a..c540843 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
index 70bd5cd..e360fde 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpsraw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
index 691e02f..761ad8a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpsrlw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
index 45527f5..c4eeff9 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
index 404c2ee..dc0d937 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
@@ -8,5 +8,5 @@
#include "avx2-vpop-check.h"
-/* { dg-final { scan-assembler-times "vpsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler "vpsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-pr57233.c
new file mode 100644
index 0000000..2f1c23a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-pr57233.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/57233 */
+/* { dg-do run { target avx512f } } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#include "avx512f-check.h"
+
+static void
+avx512f_test (void)
+{
+ do_main ();
+}
+
+#undef main
+#define main() do_main ()
+
+#include "../../gcc.dg/pr57233.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c
index a7ee076..6a0fe15 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-andn-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c
index 72fe026..c7a895c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-andn-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c
index 4ccfbdc..8dbf1eb 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c
@@ -3,4 +3,4 @@
#include "bmi-bextr-1.c"
-/* { dg-final { scan-assembler-times "bmi_bextr_di" 1 } } */
+/* { dg-final { scan-assembler "bmi_bextr_di" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c
index 282a3e4..da47610 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c
@@ -3,4 +3,4 @@
#include "bmi-bextr-2.c"
-/* { dg-final { scan-assembler-times "bmi_bextr_si" 1 } } */
+/* { dg-final { scan-assembler "bmi_bextr_si" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c
index e9e0ecb..ab52571 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsi-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c
index be9ca3f..ccca576 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsi-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c
index 4e6cb7b..c75f33c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsmsk-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c
index f6f6bab..7d3597d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsmsk-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c
index 79241ca..736997d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsr-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c
index d88c16e..6f6b67f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi-blsr-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c
index e283c31..cd469a7 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -mbmi -fno-inline" } */
+/* { dg-options "-O2 -mbmi -fno-inline --param max-default-completely-peeled-insns=0" } */
#include "bmi-tzcnt-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c
index 2cdb3f4..b60a5a1 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mbmi -fno-inline" } */
+/* { dg-options "-O2 -mbmi -fno-inline --param max-default-completely-peeled-insns=0" } */
#include "bmi-tzcnt-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c
index 05be7a8..64be3ba 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mbmi2 -O2 -dp" } */
+/* { dg-options "-mbmi2 -O2 -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi2-bzhi32-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c
index dc4a94c..08fee20 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-mbmi2 -O2 -dp" } */
+/* { dg-options "-mbmi2 -O2 -dp --param max-default-completely-peeled-insns=0" } */
#include "bmi2-bzhi64-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c
index 87888fc..7e52898 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c
@@ -3,4 +3,4 @@
#include "bmi2-pdep32-1.c"
-/* { dg-final { scan-assembler-times "bmi2_pdep_si3" 1 } } */
+/* { dg-final { scan-assembler "bmi2_pdep_si3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c
index 8163c40..24238ca 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c
@@ -3,4 +3,4 @@
#include "bmi2-pdep64-1.c"
-/* { dg-final { scan-assembler-times "bmi2_pdep_di3" 1 } } */
+/* { dg-final { scan-assembler "bmi2_pdep_di3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c
index c4a6dee..5d908b3 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c
@@ -3,4 +3,4 @@
#include "bmi2-pext32-1.c"
-/* { dg-final { scan-assembler-times "bmi2_pext_si3" 1 } } */
+/* { dg-final { scan-assembler "bmi2_pext_si3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c
index aaf06c1..c4fb99c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c
@@ -3,4 +3,4 @@
#include "bmi2-pext64-1.c"
-/* { dg-final { scan-assembler-times "bmi2_pext_di3" 1 } } */
+/* { dg-final { scan-assembler "bmi2_pext_di3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c
index 7a39c67..32036e1 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=k8" } */
+/* { dg-options "-O2 -fno-tree-loop-vectorize -march=k8" } */
/* { dg-final { scan-assembler "sbb" } } */
extern void abort (void);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map
deleted file mode 100644
index 147f922..0000000
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map
+++ /dev/null
@@ -1,3 +0,0 @@
-# clear all hardware capabilities emitted by Sun as: the tests here
-# guard against execution at runtime
-hwcap_1 = V0x0 OVERRIDE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map
deleted file mode 100644
index 95cb14c..0000000
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map
+++ /dev/null
@@ -1,7 +0,0 @@
-# clear all hardware capabilities emitted by Sun as: the tests here
-# guard against execution at runtime
-# uses mapfile v2 syntax which is the only way to clear AT_SUN_CAP_HW2 flags
-$mapfile_version 2
-CAPABILITY {
- HW = ;
-};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp b/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp
index 080e302..d9b36cd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp
@@ -23,6 +23,7 @@ if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
# Load support procs.
load_lib gcc-dg.exp
+load_lib clearcap.exp
# Return 1 if attribute ms_hook_prologue is supported.
proc check_effective_target_ms_hook_prologue { } {
@@ -307,39 +308,6 @@ proc check_effective_target_sha { } {
} "-O2 -msha" ]
}
-# If the linker used understands -M <mapfile>, pass it to clear hardware
-# capabilities set by the Sun assembler.
-# Try mapfile syntax v2 first which is the only way to clear hwcap_2 flags.
-set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcapv2.map"
-
-if ![check_no_compiler_messages mapfilev2 executable {
- int main (void) { return 0; }
-} $clearcap_ldflags ] {
- # If this doesn't work, fall back to the less capable v1 syntax.
- set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcap.map"
-
- if ![check_no_compiler_messages mapfile executable {
- int main (void) { return 0; }
- } $clearcap_ldflags ] {
- unset clearcap_ldflags
- }
-}
-
-if [info exists clearcap_ldflags] {
- if { [info procs gcc_target_compile] != [list] \
- && [info procs saved_gcc_target_compile] == [list] } {
- rename gcc_target_compile saved_gcc_target_compile
-
- proc gcc_target_compile { source dest type options } {
- global clearcap_ldflags
- # Always pass -Wl,-M,<mapfile>, but don't let it show up in gcc.sum.
- lappend options "additional_flags=$clearcap_ldflags"
-
- return [saved_gcc_target_compile $source $dest $type $options]
- }
- }
-}
-
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
@@ -348,6 +316,7 @@ if ![info exists DEFAULT_CFLAGS] then {
# Initialize `dg'.
dg-init
+clearcap-init
# Special case compilation of vect-args.c so we don't have to
# replicate it 10 times.
@@ -367,4 +336,5 @@ set tests [prune $tests $srcdir/$subdir/vect-args.c]
dg-runtest $tests "" $DEFAULT_CFLAGS
# All done.
+clearcap-finish
dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-1.c
new file mode 100644
index 0000000..aa1f424
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-1.c
@@ -0,0 +1,23 @@
+/* Verify -mpatch-functions-for-instrumentation works. */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation" } */
+
+/* Check nop-bytes at beginning. */
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* Check nop-bytes at end. */
+/* { dg-final { scan-assembler "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((noinline))
+void foo()
+{
+ /* Dummy loop. */
+ int x = 0;
+ while (++x);
+}
+
+int main()
+{
+ foo();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-2.c
new file mode 100644
index 0000000..78de867
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation -mno-patch-functions-main-always" } */
+
+/* Function is small to be instrumented with default values. Check there
+ aren't any nop-bytes at beginning or end of function. */
+
+/* { dg-final { scan-assembler-not ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler-not "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((noinline))
+void foo()
+{
+ int x = 0;
+}
+
+int main()
+{
+ foo();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-3.c
new file mode 100644
index 0000000..9e8eb52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation --param function-patch-min-instructions=0" } */
+
+/* Function should have nop-bytes with -mpatch-function-min-instructions=0.
+ Check there are nop-bytes at beginning and end of function. */
+
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((noinline))
+void foo()
+{
+ int x = 0;
+}
+
+int main()
+{
+ foo();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-4.c
new file mode 100644
index 0000000..7a031d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation -mpatch-functions-ignore-loops -mno-patch-functions-main-always" } */
+
+/* Function is too small to be patched when ignoring the loop.
+ Check there aren't any nop-bytes at beginning and end of function. */
+
+/* { dg-final { scan-assembler-not ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler-not "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((noinline))
+void foo()
+{
+ int x = 0;
+ while (++x);
+}
+
+int main()
+{
+ foo();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-5.c
new file mode 100644
index 0000000..cd6a014
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-5.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation -mpatch-functions-ignore-loops --param function-patch-min-instructions=0" } */
+
+/* Function should be patched with nop bytes with given options.
+ Check there are nop-bytes at beginning and end of function. */
+
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((noinline))
+void foo()
+{
+ int x = 0;
+ while (++x);
+}
+
+int main()
+{
+ foo();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-6.c
new file mode 100644
index 0000000..c1d6446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-6.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation" } */
+
+/* 'main' function should always be patched, irrespective of how small it is.
+ Check there are nop-bytes at beginning and end of main. */
+
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+int main()
+{
+ int x = 0;
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-7.c
new file mode 100644
index 0000000..f625298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-7.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation -mno-patch-functions-main-always" } */
+
+/* 'main' shouldn't be patched with the option -mno-patch-functions-main-always.
+ Check there aren't any nop-bytes at beginning and end of main. */
+
+/* { dg-final { scan-assembler-not ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler-not "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+int main()
+{
+ int x = 0;
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-8.c
new file mode 100644
index 0000000..436379c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-8.c
@@ -0,0 +1,29 @@
+/* Verify -mpatch-functions-for-instrumentation works. */
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+
+/* -O2 forces a sibling call for foo from bar. */
+/* { dg-options "-O2 -mpatch-functions-for-instrumentation --param function-patch-min-instructions=0" } */
+
+__attribute__ ((noinline))
+int foo()
+{
+ /* Dummy loop. */
+ int x = 10;
+ int y = 100;
+ while (--x)
+ ++y;
+ return y;
+}
+
+__attribute__ ((noinline))
+int bar()
+{
+ return foo();
+}
+
+int main()
+{
+ bar();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-no-patching.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-no-patching.c
new file mode 100644
index 0000000..cad6f2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-no-patching.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpatch-functions-for-instrumentation -mno-patch-functions-main-always" } */
+
+/* Even complicated functions shouldn't get patched if they have the
+ never_patch_for_instrumentation attribute. */
+
+/* { dg-final { scan-assembler-not ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler-not "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((never_patch_for_instrumentation))
+int foo () {
+ volatile unsigned x = 0;
+ volatile unsigned y = 1;
+ x += y;
+ x *= y;
+ while (++x)
+ foo ();
+ return y;
+}
+
+
+int main ()
+{
+ int x = 0;
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-patching.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-patching.c
new file mode 100644
index 0000000..86ad159
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-force-patching.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O3 -mpatch-functions-for-instrumentation -mno-patch-functions-main-always" } */
+
+/* Functions which have the always_patch attribute should be patched no matter
+ what. Check that there are nop-bytes at the beginning and end of the
+ function. We add -O3 so that the compiler will try to inline foo (but it
+ will be blocked by the attribute). */
+
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+/* { dg-final { scan-assembler "ret(.*).byte\t0x90(.*).byte\t0x90" } } */
+
+__attribute__ ((always_patch_for_instrumentation))
+static int foo () {
+ return 3;
+}
+
+int main () {
+ volatile int x = foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-sibling-call.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-sibling-call.c
new file mode 100644
index 0000000..847a95c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/patch-functions-sibling-call.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* -O2 forces a sibling call. */
+/* { dg-options "-O2 -mpatch-functions-for-instrumentation" } */
+
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90" } } */
+
+/* Checks correct nop-bytes are generated just before a sibling call. */
+/* { dg-final { scan-assembler ".byte\t0xeb,0x09(.*).byte\t0x90(.*)jmp" } } */
+
+/* Not instrumented as function has no loop and is small. */
+__attribute__ ((noinline))
+int foo(int n)
+{
+ int x = 0;
+ return n + 10;
+}
+
+__attribute__ ((noinline))
+int bar(int n)
+{
+ /* Dummy loop. */
+ while (--n)
+ n = n * 2;
+ return foo(n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c
new file mode 100644
index 0000000..ae339bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c
@@ -0,0 +1,13 @@
+/* Test if -mcopyrelocs does the right thing. */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpie -mcopyrelocs" } */
+
+extern int glob_a;
+
+int foo ()
+{
+ return glob_a;
+}
+
+/* glob_a should never be accessed with a GOTPCREL */
+/* { dg-final { scan-assembler-not "glob_a\\@GOTPCREL" { target { x86_64-*-* } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c
new file mode 100644
index 0000000..ed60d03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c
@@ -0,0 +1,13 @@
+/* Test if -mno-copyrelocs does the right thing. */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpie -mno-copyrelocs" } */
+
+extern int glob_a;
+
+int foo ()
+{
+ return glob_a;
+}
+
+/* glob_a should always be accessed via GOT */
+/* { dg-final { scan-assembler "glob_a\\@GOT" { target { x86_64-*-* } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c
index e111574..8ec601d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c
@@ -1,5 +1,5 @@
/* PR target/50038 */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fno-tree-loop-vectorize" } */
void
test (int len, unsigned char *in, unsigned char *out)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57233.c
new file mode 100644
index 0000000..34182fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57233.c
@@ -0,0 +1,15 @@
+/* PR tree-optimization/57233 */
+/* { dg-do compile { target avx } } */
+/* { dg-options "-O2 -mavx -mno-xop" } */
+
+typedef unsigned V4 __attribute__((vector_size(4 * sizeof (int))));
+V4 a;
+
+__attribute__((noinline)) void
+foo (void)
+{
+ a = (a << 2) | (a >> 30);
+}
+
+/* { dg-final { scan-assembler "vpsrld\[^\n\r]*30" } } */
+/* { dg-final { scan-assembler "vpslld\[^\n\r]*2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60868.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60868.c
new file mode 100644
index 0000000..c30bbfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60868.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -minline-all-stringops -minline-stringops-dynamically -march=core2" } */
+
+void bar (float *);
+
+void foo (void)
+{
+ float b[256] = {0};
+ bar(b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60901.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60901.c
new file mode 100644
index 0000000..f0f25a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60901.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O -fselective-scheduling -fschedule-insns -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops -fno-tree-dominator-opts" } */
+
+extern int n;
+extern void bar (void);
+extern int baz (int);
+
+void
+foo (void)
+{
+ int i, j;
+ for (j = 0; j < n; j++)
+ {
+ for (i = 1; i < j; i++)
+ bar ();
+ baz (0);
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60902.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60902.c
new file mode 100644
index 0000000..b81dcd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60902.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+extern void abort ();
+extern void exit (int);
+
+int x;
+
+foo()
+{
+ static int count;
+ count++;
+ if (count > 1)
+ abort ();
+}
+
+static inline int
+frob ()
+{
+ int a;
+ __asm__ ("mov %1, %0\n\t" : "=r" (a) : "m" (x));
+ x++;
+ return a;
+}
+
+int
+main ()
+{
+ int i;
+ for (i = 0; i < 10 && frob () == 0; i++)
+ foo();
+ exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-1.c
new file mode 100644
index 0000000..5a1ac3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrdrnd" } */
+
+extern void bar (int);
+
+void
+foo (unsigned *u)
+{
+ int i = __builtin_ia32_rdrand32_step (u);
+ bar (i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-2.c
new file mode 100644
index 0000000..dd35668
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60909-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrdseed" } */
+
+extern void bar (int);
+
+void
+foo (unsigned *u)
+{
+ int i = __builtin_ia32_rdseed_si_step (u);
+ bar (i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61423.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61423.c
new file mode 100644
index 0000000..5b538a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61423.c
@@ -0,0 +1,38 @@
+/* PR target/61423 */
+/* { dg-do run { target ia32 } } */
+/* { dg-options "-O1 -ftree-vectorize -msse2 -mfpmath=387 -mtune=core2" } */
+
+#define N 1024
+static unsigned int A[N];
+
+double
+__attribute__((noinline))
+func (void)
+{
+ unsigned int sum = 0;
+ unsigned i;
+ double t;
+
+ for (i = 0; i < N; i++)
+ sum += A[i];
+
+ t = sum;
+ return t;
+}
+
+int
+main ()
+{
+ unsigned i;
+ double d;
+
+ for(i = 0; i < N; i++)
+ A[i] = 1;
+
+ d = func();
+
+ if (d != 1024.0)
+ __builtin_abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61446.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61446.c
new file mode 100644
index 0000000..fc32f63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61446.c
@@ -0,0 +1,14 @@
+/* PR rtl-optimization/61446 */
+
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -march=corei7 -mfpmath=387" } */
+
+unsigned long long
+foo (float a)
+{
+ const double dfa = a;
+ const unsigned int hi = dfa / 0x1p32f;
+ const unsigned int lo = dfa - (double) hi * 0x1p32f;
+
+ return ((unsigned long long) hi << (4 * (8))) | lo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-1.c
new file mode 100644
index 0000000..4eec992
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-1.c
@@ -0,0 +1,13 @@
+/* PR target/61599 */
+/* { dg-options "-mcmodel=medium -fdata-sections" { target lp64 } } */
+/* { dg-do compile { target lp64 } } */
+
+char a[1*1024*1024*1024];
+char b[1*1024*1024*1024];
+char c[1*1024*1024*1024];
+
+extern int bar();
+int main()
+{
+ return bar() + c[225];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-2.c
new file mode 100644
index 0000000..22a53a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61599-2.c
@@ -0,0 +1,13 @@
+/* PR target/61599 */
+/* With -mcmodel=medium, all the arrays will be treated as large data. */
+/* { dg-options "-mcmodel=medium -fdata-sections" { target lp64 } } */
+/* { dg-do compile { target lp64 } } */
+
+extern char a[];
+extern char b[];
+extern char c[];
+
+int bar()
+{
+ return a[2] + b[16] + c[256];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c
index 9cf3cc8..efc73f9 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c
@@ -31,4 +31,4 @@ void t3(void)
r[i] = sqrtf (a[i]);
}
-/* { dg-final { scan-assembler-times "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" 3 } } */
+/* { dg-final { scan-assembler "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pr57233.c
new file mode 100644
index 0000000..8a3bb2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pr57233.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/57233 */
+/* { dg-do run { target sse2 } } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+static void
+sse2_test (void)
+{
+ do_main ();
+}
+
+#undef main
+#define main() do_main ()
+
+#include "../../gcc.dg/pr57233.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unaligned-mov.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unaligned-mov.c
new file mode 100644
index 0000000..28470ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unaligned-mov.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=corei7 -O2" } */
+
+#include <emmintrin.h>
+
+double a[1000];
+
+__m128d foo1() {
+ __m128d res;
+ res = _mm_load_sd(&a[1]);
+ res = _mm_loadh_pd(res, &a[2]);
+ return res;
+}
+
+void foo2(__m128d res) {
+ _mm_store_sd(&a[1], res);
+ _mm_storeh_pd(&a[2], res);
+}
+
+/* { dg-final { scan-assembler-times "movup" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
index 96dd8a6..fc92e68 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target sse4 } */
-/* { dg-options "-O2 -msse4.1" } */
+/* { dg-options "-O2 -msse4.1 --param max-default-completely-peeled-insns=0" } */
/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
#include "sse4_1-check.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
index f052c02..72e6807 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target sse4 } */
-/* { dg-options "-O2 -msse4.1" } */
+/* { dg-options "-O2 -msse4.1 --param max-default-completely-peeled-insns=0" } */
/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
#include "sse4_1-check.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
index 0a696b1..0af7ea7 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target sse4 } */
-/* { dg-options "-O2 -msse4.1" } */
+/* { dg-options "-O2 -msse4.1 --param max-default-completely-peeled-insns=0" } */
/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
#include "sse4_1-check.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vec-may_alias.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vec-may_alias.c
new file mode 100644
index 0000000..e970497
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vec-may_alias.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -w -Wno-abi" } */
+
+typedef int v2si __attribute__ ((vector_size (8)));
+typedef short v4hi __attribute__ ((vector_size (8)));
+typedef short v4hia __attribute__ ((vector_size (8), may_alias));
+
+__attribute__ ((noinline, noclone))
+int f (v2si A, int N)
+{ return ((v4hia)A)[N]; }
+
+__attribute__ ((noinline, noclone))
+int g (v2si A, int N)
+{ return ((v4hi)A)[N]; }
+
+int main()
+{
+ v2si x = { 0, 0 }, y = { 1, 1 };
+ if (f (x, 0) || f (x, 1) || f (x, 2) || f (x, 3))
+ __builtin_abort ();
+ if (g (y, 0) != 1 || g (y, 1) || g (y, 2) != 1 || g (y, 3))
+ __builtin_abort ();
+ return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c
index 4ef8385..b8fd06a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fno-tree-loop-vectorize" } */
/* { dg-require-effective-target ia32 } */
long long mac(const int *a, const int *b, long long sqr, long long *sum)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pr57233.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pr57233.c
new file mode 100644
index 0000000..6129dc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pr57233.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/57233 */
+/* { dg-do run { target xop } } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+static void
+xop_test (void)
+{
+ do_main ();
+}
+
+#undef main
+#define main() do_main ()
+
+#include "../../gcc.dg/pr57233.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-1.c
new file mode 100644
index 0000000..c7496c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */
+/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */
+/* { dg-final { scan-assembler-times "addg6s " 1 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+
+unsigned int
+to_bcd (unsigned int a)
+{
+ return __builtin_cdtbcd (a);
+}
+
+unsigned int
+from_bcd (unsigned int a)
+{
+ return __builtin_cbcdtd (a);
+}
+
+unsigned int
+bcd_arith (unsigned int a, unsigned int b)
+{
+ return __builtin_addg6s (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-2.c
new file mode 100644
index 0000000..d330b74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-2.c
@@ -0,0 +1,44 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */
+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+/* { dg-final { scan-assembler-not "mtvsr" } } */
+/* { dg-final { scan-assembler-not "mfvsr" } } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+/* { dg-final { scan-assembler-not "lxvw4x" } } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+/* { dg-final { scan-assembler-not "stvx" } } */
+/* { dg-final { scan-assembler-not "stxvw4x" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
+typedef __int128_t scalar_128_t;
+typedef unsigned long long scalar_64_t;
+
+vector_128_t
+do_add_0 (vector_128_t a, vector_128_t b)
+{
+ return __builtin_bcdadd (a, b, 0);
+}
+
+vector_128_t
+do_add_1 (vector_128_t a, vector_128_t b)
+{
+ return __builtin_bcdadd (a, b, 1);
+}
+
+vector_128_t
+do_sub_0 (vector_128_t a, vector_128_t b)
+{
+ return __builtin_bcdsub (a, b, 0);
+}
+
+vector_128_t
+do_sub_1 (vector_128_t a, vector_128_t b)
+{
+ return __builtin_bcdsub (a, b, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-3.c
new file mode 100644
index 0000000..436cecf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bcd-3.c
@@ -0,0 +1,103 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */
+/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+/* { dg-final { scan-assembler-not "mtvsr" } } */
+/* { dg-final { scan-assembler-not "mfvsr" } } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+/* { dg-final { scan-assembler-not "lxvw4x" } } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+/* { dg-final { scan-assembler-not "stvx" } } */
+/* { dg-final { scan-assembler-not "stxvw4x" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
+typedef __int128_t scalar_128_t;
+typedef unsigned long long scalar_64_t;
+
+/* Test whether the peephole works to allow folding a bcdadd, with a
+ bcdadd_<test> into a single instruction. */
+
+vector_128_t
+do_add_lt (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
+ if (__builtin_bcdadd_lt (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_add_eq (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
+ if (__builtin_bcdadd_eq (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_add_gt (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
+ if (__builtin_bcdadd_gt (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_add_ov (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdadd (a, b, 0);
+ if (__builtin_bcdadd_ov (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_sub_lt (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
+ if (__builtin_bcdsub_lt (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_sub_eq (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
+ if (__builtin_bcdsub_eq (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_sub_gt (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
+ if (__builtin_bcdsub_gt (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
+
+vector_128_t
+do_sub_ov (vector_128_t a, vector_128_t b, int *p)
+{
+ vector_128_t ret = __builtin_bcdsub (a, b, 0);
+ if (__builtin_bcdsub_ov (a, b, 0))
+ *p = 1;
+
+ return ret;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c
new file mode 100644
index 0000000..614f272
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c
@@ -0,0 +1,88 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-times "ddedpd " 4 } } */
+/* { dg-final { scan-assembler-times "denbcd " 2 } } */
+/* { dg-final { scan-assembler-times "dxex " 1 } } */
+/* { dg-final { scan-assembler-times "diex " 1 } } */
+/* { dg-final { scan-assembler-times "dscli " 2 } } */
+/* { dg-final { scan-assembler-times "dscri " 2 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+/* { dg-final { scan-assembler-not "dctqpq" } } */
+/* { dg-final { scan-assembler-not "drdpq" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+/* { dg-final { scan-assembler-not "lfd" } } */
+
+_Decimal64
+do_dedpd_0 (_Decimal64 a)
+{
+ return __builtin_ddedpd (0, a);
+}
+
+_Decimal64
+do_dedpd_1 (_Decimal64 a)
+{
+ return __builtin_ddedpd (1, a);
+}
+
+_Decimal64
+do_dedpd_2 (_Decimal64 a)
+{
+ return __builtin_ddedpd (2, a);
+}
+
+_Decimal64
+do_dedpd_3 (_Decimal64 a)
+{
+ return __builtin_ddedpd (3, a);
+}
+
+_Decimal64
+do_enbcd_0 (_Decimal64 a)
+{
+ return __builtin_denbcd (0, a);
+}
+
+_Decimal64
+do_enbcd_1 (_Decimal64 a)
+{
+ return __builtin_denbcd (1, a);
+}
+
+_Decimal64
+do_xex (_Decimal64 a)
+{
+ return __builtin_dxex (a);
+}
+
+_Decimal64
+do_iex (_Decimal64 a, _Decimal64 b)
+{
+ return __builtin_diex (a, b);
+}
+
+_Decimal64
+do_scli_1 (_Decimal64 a)
+{
+ return __builtin_dscli (a, 1);
+}
+
+_Decimal64
+do_scli_10 (_Decimal64 a)
+{
+ return __builtin_dscli (a, 10);
+}
+
+_Decimal64
+do_scri_1 (_Decimal64 a)
+{
+ return __builtin_dscri (a, 1);
+}
+
+_Decimal64
+do_scri_10 (_Decimal64 a)
+{
+ return __builtin_dscri (a, 10);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c
new file mode 100644
index 0000000..189bc9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c
@@ -0,0 +1,88 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */
+/* { dg-final { scan-assembler-times "denbcdq " 2 } } */
+/* { dg-final { scan-assembler-times "dxexq " 1 } } */
+/* { dg-final { scan-assembler-times "diexq " 1 } } */
+/* { dg-final { scan-assembler-times "dscliq " 2 } } */
+/* { dg-final { scan-assembler-times "dscriq " 2 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+/* { dg-final { scan-assembler-not "dctqpq" } } */
+/* { dg-final { scan-assembler-not "drdpq" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+/* { dg-final { scan-assembler-not "lfd" } } */
+
+_Decimal128
+do_dedpdq_0 (_Decimal128 a)
+{
+ return __builtin_ddedpdq (0, a);
+}
+
+_Decimal128
+do_dedpdq_1 (_Decimal128 a)
+{
+ return __builtin_ddedpdq (1, a);
+}
+
+_Decimal128
+do_dedpdq_2 (_Decimal128 a)
+{
+ return __builtin_ddedpdq (2, a);
+}
+
+_Decimal128
+do_dedpdq_3 (_Decimal128 a)
+{
+ return __builtin_ddedpdq (3, a);
+}
+
+_Decimal128
+do_enbcdq_0 (_Decimal128 a)
+{
+ return __builtin_denbcdq (0, a);
+}
+
+_Decimal128
+do_enbcdq_1 (_Decimal128 a)
+{
+ return __builtin_denbcdq (1, a);
+}
+
+_Decimal128
+do_xexq (_Decimal128 a)
+{
+ return __builtin_dxexq (a);
+}
+
+_Decimal128
+do_iexq (_Decimal128 a, _Decimal128 b)
+{
+ return __builtin_diexq (a, b);
+}
+
+_Decimal128
+do_scliq_1 (_Decimal128 a)
+{
+ return __builtin_dscliq (a, 1);
+}
+
+_Decimal128
+do_scliq_10 (_Decimal128 a)
+{
+ return __builtin_dscliq (a, 10);
+}
+
+_Decimal128
+do_scriq_1 (_Decimal128 a)
+{
+ return __builtin_dscriq (a, 1);
+}
+
+_Decimal128
+do_scriq_10 (_Decimal128 a)
+{
+ return __builtin_dscriq (a, 10);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c
new file mode 100644
index 0000000..5f948b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-times "divwe " 1 } } */
+/* { dg-final { scan-assembler-times "divweo " 1 } } */
+/* { dg-final { scan-assembler-times "divweu " 1 } } */
+/* { dg-final { scan-assembler-times "divweuo " 1 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+
+int
+div_we (int a, int b)
+{
+ return __builtin_divwe (a, b);
+}
+
+int
+div_weo (int a, int b)
+{
+ return __builtin_divweo (a, b);
+}
+
+unsigned int
+div_weu (unsigned int a, unsigned int b)
+{
+ return __builtin_divweu (a, b);
+}
+
+unsigned int
+div_weuo (unsigned int a, unsigned int b)
+{
+ return __builtin_divweuo (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c
new file mode 100644
index 0000000..8ee6c8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-times "divde " 1 } } */
+/* { dg-final { scan-assembler-times "divdeo " 1 } } */
+/* { dg-final { scan-assembler-times "divdeu " 1 } } */
+/* { dg-final { scan-assembler-times "divdeuo " 1 } } */
+/* { dg-final { scan-assembler-not "bl __builtin" } } */
+
+long
+div_de (long a, long b)
+{
+ return __builtin_divde (a, b);
+}
+
+long
+div_deo (long a, long b)
+{
+ return __builtin_divdeo (a, b);
+}
+
+unsigned long
+div_deu (unsigned long a, unsigned long b)
+{
+ return __builtin_divdeu (a, b);
+}
+
+unsigned long
+div_deuo (unsigned long a, unsigned long b)
+{
+ return __builtin_divdeuo (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-ttest.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-ttest.c
new file mode 100644
index 0000000..29cbd5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-ttest.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_htm_ok } */
+/* { dg-options "-O2 -mhtm" } */
+
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,3,30,31" { target { ilp32 } } } } */
+/* { dg-final { scan-assembler "rldicl r?\[0-9\]+,r?\[0-9\]+,35,62" { target { lp64 } } } } */
+
+#include <htmintrin.h>
+long
+ttest (void)
+{
+ return _HTM_STATE(__builtin_ttest());
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack01.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack01.c
new file mode 100644
index 0000000..efac408
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack01.c
@@ -0,0 +1,91 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <altivec.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
+typedef __int128_t scalar_128_t;
+typedef unsigned long long scalar_64_t;
+
+volatile scalar_64_t one = 1;
+volatile scalar_64_t two = 2;
+
+int
+main (void)
+{
+ scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two);
+ vector_128_t v1 = (vector_128_t) { a };
+ vector_128_t v2 = __builtin_pack_vector_int128 (one, two);
+ scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0);
+ scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1);
+ vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1);
+
+ size_t i;
+ union {
+ scalar_128_t i128;
+ vector_128_t v128;
+ scalar_64_t u64;
+ unsigned char uc[sizeof (scalar_128_t)];
+ char c[sizeof (scalar_128_t)];
+ } u, u2;
+
+#ifdef DEBUG
+ {
+ printf ("a = 0x");
+ u.i128 = a;
+ for (i = 0; i < sizeof (scalar_128_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nv1 = 0x");
+ u.v128 = v1;
+ for (i = 0; i < sizeof (scalar_128_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nv2 = 0x");
+ u.v128 = v2;
+ for (i = 0; i < sizeof (scalar_128_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nv3 = 0x");
+ u.v128 = v3;
+ for (i = 0; i < sizeof (scalar_128_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nx0 = 0x");
+ u.u64 = x0;
+ for (i = 0; i < sizeof (scalar_64_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nx1 = 0x");
+ u.u64 = x1;
+ for (i = 0; i < sizeof (scalar_64_t); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\n");
+ }
+#endif
+
+ u2.i128 = a;
+ u.v128 = v1;
+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
+ abort ();
+
+ u.v128 = v2;
+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
+ abort ();
+
+ u.v128 = v3;
+ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack02.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack02.c
new file mode 100644
index 0000000..f85d3ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack02.c
@@ -0,0 +1,96 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-require-effective-target longdouble128 } */
+/* { dg-options "-O2 -mhard-float" } */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <math.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+int
+main (void)
+{
+ double high = pow (2.0, 60);
+ double low = 2.0;
+ long double a = ((long double)high) + ((long double)low);
+ double x0 = __builtin_unpack_longdouble (a, 0);
+ double x1 = __builtin_unpack_longdouble (a, 1);
+ long double b = __builtin_pack_longdouble (x0, x1);
+
+#ifdef DEBUG
+ {
+ size_t i;
+ union {
+ long double ld;
+ double d;
+ unsigned char uc[sizeof (long double)];
+ char c[sizeof (long double)];
+ } u;
+
+ printf ("a = 0x");
+ u.ld = a;
+ for (i = 0; i < sizeof (long double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (", %Lg\n", a);
+
+ printf ("b = 0x");
+ u.ld = b;
+ for (i = 0; i < sizeof (long double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (", %Lg\n", b);
+
+ printf ("hi = 0x");
+ u.d = high;
+ for (i = 0; i < sizeof (double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high);
+
+ printf ("lo = 0x");
+ u.d = low;
+ for (i = 0; i < sizeof (double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low);
+
+ printf ("x0 = 0x");
+ u.d = x0;
+ for (i = 0; i < sizeof (double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0);
+
+ printf ("x1 = 0x");
+ u.d = x1;
+ for (i = 0; i < sizeof (double); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1);
+ }
+#endif
+
+ if (high != x0)
+ abort ();
+
+ if (low != x1)
+ abort ();
+
+ if (a != b)
+ abort ();
+
+ if (x0 != high)
+ abort ();
+
+ if (x1 != low)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack03.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack03.c
new file mode 100644
index 0000000..dfaf2ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pack03.c
@@ -0,0 +1,88 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target dfp_hw } */
+/* { dg-options "-O2 -mhard-dfp" } */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <math.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+int
+main (void)
+{
+ _Decimal128 one = (_Decimal128)1.0;
+ _Decimal128 two = (_Decimal128)2.0;
+ _Decimal128 ten = (_Decimal128)10.0;
+ _Decimal128 a = one;
+ _Decimal128 b;
+ _Decimal128 c;
+ unsigned long long x0;
+ unsigned long long x1;
+ size_t i;
+
+ for (i = 0; i < 25; i++)
+ a *= ten;
+
+ a += two;
+
+ x0 = __builtin_unpack_dec128 (a, 0);
+ x1 = __builtin_unpack_dec128 (a, 1);
+ b = __builtin_pack_dec128 (x0, x1);
+ c = __builtin_dscliq (one, 25) + two;
+
+#ifdef DEBUG
+ {
+ union {
+ _Decimal128 d;
+ unsigned long long ull;
+ unsigned char uc[sizeof (_Decimal128)];
+ } u;
+
+ printf ("a = 0x");
+ u.d = a;
+ for (i = 0; i < sizeof (_Decimal128); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (", %Lg\n", (long double)a);
+
+ printf ("b = 0x");
+ u.d = b;
+ for (i = 0; i < sizeof (_Decimal128); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (", %Lg\n", (long double)b);
+
+ printf ("c = 0x");
+ u.d = c;
+ for (i = 0; i < sizeof (_Decimal128); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf (", %Lg\n", (long double)c);
+
+ printf ("x0 = 0x");
+ u.ull = x0;
+ for (i = 0; i < sizeof (unsigned long long); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\nx1 = 0x");
+ u.ull = x1;
+ for (i = 0; i < sizeof (unsigned long long); i++)
+ printf ("%.2x", u.uc[i]);
+
+ printf ("\n");
+ }
+#endif
+
+ if (a != b)
+ abort ();
+
+ if (a != c)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60735.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60735.c
new file mode 100644
index 0000000..9bac30b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60735.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* In PR60735, the type _Decimal64 generated an insn not found message. */
+
+void
+pr60735 (_Decimal64 *p, _Decimal64 *q)
+{
+ *p = *q;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c
index e6578ef..ea703f0 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c
@@ -1,6 +1,7 @@
/* { dg-do assemble } */
/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */
/* { dg-skip-if "no TFmode" { powerpc-*-eabi* } { "*" } { "" } } */
+/* { dg-require-effective-target longdouble128 } */
/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */
typedef float TFmode __attribute__ ((mode (TF)));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math1.c
new file mode 100644
index 0000000..cdf9251
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "addc" 1 } } */
+/* { dg-final { scan-assembler-times "adde" 1 } } */
+/* { dg-final { scan-assembler-times "subfc" 1 } } */
+/* { dg-final { scan-assembler-times "subfe" 1 } } */
+/* { dg-final { scan-assembler-not "subf " } } */
+
+__int128
+add_128 (__int128 *ptr, __int128 val)
+{
+ return (*ptr + val);
+}
+
+__int128
+sub_128 (__int128 *ptr, __int128 val)
+{
+ return (*ptr - val);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math2.c
new file mode 100644
index 0000000..b9c0330
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ti_math2.c
@@ -0,0 +1,73 @@
+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2 -fno-inline" } */
+
+union U {
+ __int128 i128;
+ struct {
+ long l1;
+ long l2;
+ } s;
+};
+
+union U u1,u2;
+
+__int128
+create_128 (long most_sig, long least_sig)
+{
+ union U u;
+
+#if __LITTLE_ENDIAN__
+ u.s.l1 = least_sig;
+ u.s.l2 = most_sig;
+#else
+ u.s.l1 = most_sig;
+ u.s.l2 = least_sig;
+#endif
+ return u.i128;
+}
+
+long most_sig (union U * u)
+{
+#if __LITTLE_ENDIAN__
+ return (*u).s.l2;
+#else
+ return (*u).s.l1;
+#endif
+}
+
+long least_sig (union U * u)
+{
+#if __LITTLE_ENDIAN__
+ return (*u).s.l1;
+#else
+ return (*u).s.l2;
+#endif
+}
+
+__int128
+add_128 (__int128 *ptr, __int128 val)
+{
+ return (*ptr + val);
+}
+
+__int128
+sub_128 (__int128 *ptr, __int128 val)
+{
+ return (*ptr - val);
+}
+
+int
+main (void)
+{
+ /* Do a simple add/sub to make sure carry is happening between the dwords
+ and that dwords are in correct endian order. */
+ u1.i128 = create_128 (1, -1);
+ u2.i128 = add_128 (&u1.i128, 1);
+ if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0))
+ __builtin_abort ();
+ u2.i128 = sub_128 (&u2.i128, 1);
+ if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1))
+ __builtin_abort ();
+ return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c
deleted file mode 100644
index 59621a4..0000000
--- a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* { dg-do run } */
-/* { dg-options "-O3 -mhtm -Wa,-march=zEC12,-mzarch --save-temps" } */
-
-/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin
- instruction does not automatically preserves them. If the
- transaction body is fully contained in a function the backend tries
- after reload to get rid of the FPR save/restore operations
- triggered by the clobbers. This testcase failed since the backend
- was able to get rid of all FPR saves/restores and since these were
- the only stack operations also of the entire stack space. So even
- the save/restore of the stack pointer was omitted in the end.
- However, since the frame layout has been fixed before, the prologue
- still generated the stack pointer decrement making foo return with
- a modified stack pointer. */
-
-void abort(void);
-
-void __attribute__((noinline))
-foo (int a)
-{
- /* This is just to prevent the tbegin code from actually being
- executed. That way the test may even run on machines prior to
- zEC12. */
- if (a == 42)
- return;
-
- if (__builtin_tbegin (0) == 0)
- __builtin_tend ();
-}
-
-#ifdef __s390x__
-#define GET_STACK_POINTER(SP) \
- asm volatile ("stg %%r15, %0" : "=QRST" (SP));
-#else
-#define GET_STACK_POINTER(SP) \
- asm volatile ("st %%r15, %0" : "=QR" (SP));
-#endif
-
-int main(void)
-{
- unsigned long new_sp, old_sp;
-
- GET_STACK_POINTER (old_sp);
- foo(42);
- GET_STACK_POINTER (new_sp);
-
- if (old_sp != new_sp)
- abort ();
-
- return 0;
-}
-
-/* Make sure no FPR saves/restores are emitted. */
-/* { dg-final { scan-assembler-not "\tstd\t" } } */
-/* { dg-final { scan-assembler-not "\tld\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
index d6fc187..624b7ea 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
@@ -20,6 +20,7 @@
load_lib c-torture.exp
load_lib target-supports.exp
load_lib torture-options.exp
+load_lib clearcap.exp
if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
|| ![is-effective-target lp64]
@@ -28,20 +29,10 @@ if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
}
-# If the linker used understands -M <mapfile>, pass it to clear hardware
-# capabilities set by the Sun assembler.
-set flags ""
-set clearcap_ldflags "-Wl,-M,$srcdir/gcc.target/i386/clearcap.map"
-
-if [check_no_compiler_messages mapfile executable {
- int main (void) { return 0; }
- } $clearcap_ldflags ] {
- set flags $clearcap_ldflags
-}
-
torture-init
+clearcap-init
set-torture-options $C_TORTURE_OPTIONS
-set additional_flags "-W -Wall -mavx $flags"
+set additional_flags "-W -Wall -mavx"
foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
if {[runtest_file_p $runtests $src]} {
@@ -58,4 +49,5 @@ foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
}
}
+clearcap-finish
torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp
index cef6fa1..f8f991e 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp
@@ -20,6 +20,7 @@
load_lib c-torture.exp
load_lib target-supports.exp
load_lib torture-options.exp
+load_lib clearcap.exp
if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
|| ![is-effective-target lp64]
@@ -28,20 +29,10 @@ if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
}
-# If the linker used understands -M <mapfile>, pass it to clear hardware
-# capabilities set by the Sun assembler.
-set flags ""
-set clearcap_ldflags "-Wl,-M,$srcdir/gcc.target/i386/clearcap.map"
-
-if [check_no_compiler_messages mapfile executable {
- int main (void) { return 0; }
- } $clearcap_ldflags ] {
- set flags $clearcap_ldflags
-}
-
torture-init
+clearcap-init
set-torture-options $C_TORTURE_OPTIONS
-set additional_flags "-W -Wall -mavx512f $flags"
+set additional_flags "-W -Wall -mavx512f"
foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
if {[runtest_file_p $runtests $src]} {
@@ -58,4 +49,5 @@ foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
}
}
+clearcap-finish
torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
index 2a54bc8..df4c406 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=sysv" } */
+/* { dg-options "-O2 -fno-tree-loop-vectorize -mabi=sysv" } */
extern int glb1, gbl2, gbl3;