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| author | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
| commit | 1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch) | |
| tree | c607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c | |
| parent | 283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff) | |
| download | toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2 toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip | |
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c')
| -rw-r--r-- | gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c new file mode 100644 index 000000000..3a7a2538e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c @@ -0,0 +1,27 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */ + +void bar1 (void); +void bar2 (void); +void bar3 (void); + +NOMIPS16 void +foo (int *x, int sel, int n) +{ + if (sel) + { + bar1 (); + x[0] = 1; + } + else + { + bar2 (); + x[1] = 0; + } + /* If there is one copy of this code, reached by two unconditional edges, + then it shouldn't need a third cache barrier. */ + x[2] = 2; + while (n--) + bar3 (); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */ |