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| author | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
| commit | 1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch) | |
| tree | c607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.target/mips | |
| parent | 283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff) | |
| download | toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2 toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip | |
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/mips')
456 files changed, 21010 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c new file mode 100644 index 000000000..f3bed5963 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mlong64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +int foo (int *x, int i) +{ + return x[i] + i; +} +/* { dg-final { scan-assembler-not "\tmove" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c new file mode 100644 index 000000000..75bd1b664 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp32 -mlong32" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c new file mode 100644 index 000000000..1649433e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp32 -mlong64" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c new file mode 100644 index 000000000..03d7c2718 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp64 -mlong32" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c new file mode 100644 index 000000000..bb6fa17ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=eabi -mgp64 -mlong64" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h new file mode 100644 index 000000000..f47a2e304 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h @@ -0,0 +1,74 @@ +#define FOR_EACH_SCALAR(F) \ + F(sc, signed char) \ + F(uc, unsigned char) \ + F(ss, short) \ + F(us, unsigned short) \ + F(si, int) \ + F(ui, unsigned int) \ + F(sl, long) \ + F(ul, unsigned long) \ + F(sll, long long) \ + F(ull, unsigned long long) \ + F(f, float) \ + F(d, double) \ + F(ld, long double) \ + F(ptr, void *) + +#define EXTERN(SUFFIX, TYPE) extern TYPE x##SUFFIX; +#define STATIC(SUFFIX, TYPE) static TYPE s##SUFFIX; +#define COMMON(SUFFIX, TYPE) TYPE c##SUFFIX; + +#define GETADDR(SUFFIX, TYPE) \ + TYPE *get##SUFFIX (int which) \ + { \ + return (which == 0 ? &c##SUFFIX \ + : which == 1 ? &s##SUFFIX \ + : &x##SUFFIX); \ + } + +#define COPY(SUFFIX, TYPE) c##SUFFIX = s##SUFFIX; s##SUFFIX = x##SUFFIX; + +FOR_EACH_SCALAR (EXTERN) +FOR_EACH_SCALAR (STATIC) +FOR_EACH_SCALAR (COMMON) + +FOR_EACH_SCALAR (GETADDR) + +void +copy (void) +{ + FOR_EACH_SCALAR (COPY); +} + +extern void foo (int); + +void +sibcall1 (void) +{ + foo (1); +} + +void +sibcall2 (void) +{ + foo (csi + ssi + xsi); +} + +static void +sibcall3 (void) +{ + foo (1); + foo (2); + foo (3); +} + +extern void bar (void (*) (void)); + +int +nested (int x) +{ + void sub (void) { foo (x); } + bar (sub); + bar (sibcall3); + return 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c new file mode 100644 index 000000000..11dfe2bc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 -mabicalls -mno-shared -mno-plt" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c new file mode 100644 index 000000000..ffbe62c48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 -fpic" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c new file mode 100644 index 000000000..f6fa20d12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=n32 -mlong32 addressing=absolute" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c new file mode 100644 index 000000000..a30b573cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 -mabicalls -mno-shared -mno-plt" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c new file mode 100644 index 000000000..f9729a3dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 -fpic" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c new file mode 100644 index 000000000..b064bf5e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=n32 -mlong64 addressing=absolute" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c new file mode 100644 index 000000000..6a5240912 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 -mabicalls -mno-shared -mno-plt" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c new file mode 100644 index 000000000..6a5203e8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 -fpic" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c new file mode 100644 index 000000000..d5f52d94c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=64 -mlong32 addressing=absolute" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c new file mode 100644 index 000000000..113bbcc5a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 -mabicalls -mno-shared -mno-plt" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c new file mode 100644 index 000000000..5f734687c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 -fpic" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c new file mode 100644 index 000000000..19e6d91d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=64 -mlong64 addressing=absolute" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c new file mode 100644 index 000000000..fb1b888d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 -mabicalls -mno-shared -mno-plt" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c new file mode 100644 index 000000000..64a7f5854 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 -fpic" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c new file mode 100644 index 000000000..790122077 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=32 -mlong32 addressing=absolute" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c new file mode 100644 index 000000000..2f28aeb61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 -mabicalls -mno-shared -mno-plt" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c new file mode 100644 index 000000000..89cd9a207 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 -fpic" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c new file mode 100644 index 000000000..840e9aa13 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=32 -mlong64 addressing=absolute" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c new file mode 100644 index 000000000..832550e45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 -mabicalls -mno-shared -mno-plt" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c new file mode 100644 index 000000000..e06b88292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 -fpic" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c new file mode 100644 index 000000000..54ac2d707 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong32 addressing=absolute" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c new file mode 100644 index 000000000..94848f4e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=o64 -mlong64 -mabicalls -mno-shared -mno-plt" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c new file mode 100644 index 000000000..8c2ca36d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c @@ -0,0 +1,3 @@ +/* { dg-options "-mabi=o64 -mlong64 -fpic" } */ +/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c new file mode 100644 index 000000000..02633567c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c @@ -0,0 +1,2 @@ +/* { dg-options "-mabi=o64 -mlong64 -mno-abicalls" } */ +#include "abi-main.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c new file mode 100644 index 000000000..3a132deaf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c @@ -0,0 +1,35 @@ +/* Check that certain preprocessor macros are defined, and do some + consistency checks. */ +/* { dg-do compile } */ + +const char *compiled_for = _MIPS_ARCH; +const char *optimized_for = _MIPS_TUNE; + +#if __mips_fpr != 32 && __mips_fpr != 64 +#error Bad __mips_fpr +#endif + +/* Test complementary macro pairs: exactly one of each pair + must be defined. */ + +#if defined (_R3000) == defined (_R4000) +#error _R3000 / _R4000 mismatch +#endif + +#if defined (__mips_hard_float) == defined (__mips_soft_float) +#error __mips_hard_float / __mips_soft_float mismatch +#endif + +#if defined (_MIPSEL) == defined (_MIPSEB) +#error _MIPSEL / _MIPSEB mismatch +#endif + +/* Check for __mips64 consistency. */ + +#if defined (__mips64) != defined (_R4000) +#error __mips64 / _R4000 mismatch +#endif + +#if defined (__mips64) && __mips != 3 && __mips != 4 && __mips != 64 +#error __mips64 / __mips mismatch +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c new file mode 100644 index 000000000..192756525 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c @@ -0,0 +1,18 @@ +/* Check the _MIPSEB and _MIPSEL macros are accurate. */ +/* { dg-do run } */ +extern void abort (void); +extern void exit (int); + +short foo = 1; +int main () +{ + char *p = (char *) &foo; + +#ifdef _MIPSEB + if (p[0] != 0 || p[1] != 1) +#else + if (p[0] != 1 || p[1] != 0) +#endif + abort (); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c new file mode 100644 index 000000000..6a79ce674 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c @@ -0,0 +1,39 @@ +/* __mips, and related defines, guarantee that certain assembly + instructions can be used. Check a few examples. */ +/* { dg-do run } */ +/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */ +extern void abort (void); +extern void exit (int); + +typedef int int32 __attribute__ ((mode (SI))); +typedef int int64 __attribute__ ((mode (DI))); +int foo (float inf, int64 in64, int32 in32) +{ + int64 res64; + int32 res32; + +#if __mips != 1 && defined (__mips_hard_float) && !defined (__mips16) + __asm__ ("trunc.w.s %0, %1" : "=f" (res32) : "f" (inf)); + if (res32 != 11) + abort (); +#endif + +#if defined (__mips64) + __asm__ ("daddu %0, %1, %1" : "=r" (res64) : "r" (in64)); + if (res64 != 50) + abort (); +#endif + +#if (__mips == 4 || __mips == 32 || __mips == 64) && !defined (__mips16) + __asm__ ("move %0,%.\n\tmovn %0,%1,%2" + : "=&r" (res32) : "r" (in32), "r" (in64 != 0)); + if (res32 != 60) + abort (); +#endif +} + +int main () +{ + foo (11.4f, 25, 60); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c new file mode 100644 index 000000000..8df268946 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c @@ -0,0 +1,14 @@ +/* PR target/17565. GCC used to put the asm into the delay slot + of the call. */ +/* { dg-do assemble } */ + +NOMIPS16 int foo (int n) +{ + register int k asm ("$16") = n; + if (k > 0) + { + bar (); + asm ("li %0,0x12345678" : "=r" (k)); + } + return k; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c new file mode 100644 index 000000000..839d75c2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ + +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target mips_llsc } 0 } */ + +extern void abort (void); +extern void exit (int); + +NOMIPS16 int main () +{ +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 + unsigned v = 0; + __sync_synchronize (); + + if (!__sync_bool_compare_and_swap (&v, 0, 30000)) + abort(); + if (30000 != __sync_val_compare_and_swap (&v, 30000, 100001)) + abort(); + __sync_sub_and_fetch (&v, 0x8001); + __sync_sub_and_fetch (&v, 0x7fff); + if (v != 34465) + abort(); + if (__sync_nand_and_fetch (&v, 0xff) != -162) + abort(); + if (__sync_fetch_and_add (&v, 262) != -162) + abort(); + if (v != 100) + abort(); + if (__sync_or_and_fetch (&v, 0xf001) != 0xf065) + abort(); + if (__sync_and_and_fetch (&v, 0x1000) != 0x1000) + abort(); + if (__sync_xor_and_fetch (&v, 0xa51040) != 0xa50040) + abort(); + __sync_and_and_fetch (&v, 7); + if (__sync_lock_test_and_set(&v, 1) != 0) + abort(); + if (v != 1) + abort(); + __sync_lock_release (&v); + if (v != 0) + abort(); +#endif + exit(0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c new file mode 100644 index 000000000..506295b61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "isa>=2 -mabi=32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\taddiu\t" } } */ +/* { dg-final { scan-assembler-not "\tsubu" } } */ + +NOMIPS16 unsigned long +f(unsigned long *p) +{ + return __sync_fetch_and_sub (p, 5); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c new file mode 100644 index 000000000..6ef50e8a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c @@ -0,0 +1,14 @@ +/* Octeon targets should use "bbit" instructions for these "if" statements, + but we test for "bbit" elsewhere. On other targets, we should implement + the "if" statements using an "andi" instruction followed by a branch + on zero. */ +/* { dg-options "forbid_cpu=octeon.*" } */ + +void bar (void); +NOMIPS16 void f1 (int x) { if (x & 4) bar (); } +NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); } +NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); } +NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); } +/* { dg-final { scan-assembler "\tandi\t.*\tandi\t.*\tandi\t.*\tandi\t" } } */ +/* { dg-final { scan-assembler-not "\tsrl\t" } } */ +/* { dg-final { scan-assembler-not "\tsra\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c new file mode 100644 index 000000000..e2b1b5f6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c new file mode 100644 index 000000000..962eb1b5d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c @@ -0,0 +1,17 @@ +/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */ +/* { dg-final { scan-assembler "\tld\t\\\$28," } } */ +/* { dg-final { scan-assembler "\taddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ +/* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */ +/* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c new file mode 100644 index 000000000..4aef160ad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=64" } */ +/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c new file mode 100644 index 000000000..8a6fb049f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c @@ -0,0 +1,17 @@ +/* { dg-options "-mshared -mabi=64" } */ +/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */ +/* { dg-final { scan-assembler "\tld\t\\\$28," } } */ +/* { dg-final { scan-assembler "\tdaddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */ +/* { dg-final { scan-assembler "\tdaddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c new file mode 100644 index 000000000..026417e16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c @@ -0,0 +1,23 @@ +/* An executable version of branch-2.c. */ +/* { dg-do run } */ + +#include "branch-helper.h" + +void __attribute__((noinline)) +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} + +int +main (void) +{ + int x = 0; + int y = 1; + + foo (&x); + foo (&y); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c new file mode 100644 index 000000000..dee7a0504 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c @@ -0,0 +1,23 @@ +/* An executable version of branch-3.c. */ +/* { dg-do run } */ + +#include "branch-helper.h" + +void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} + +int +main (void) +{ + int x = 0; + int y = 1; + + foo (&x); + foo (&y); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c new file mode 100644 index 000000000..6409c4cc5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=32" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|cpload)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\.cprestore" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c new file mode 100644 index 000000000..5fcfece3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=32" } */ +/* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\.cprestore" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c new file mode 100644 index 000000000..31e4909e5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c @@ -0,0 +1,12 @@ +/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c new file mode 100644 index 000000000..1e9c120c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c @@ -0,0 +1,14 @@ +/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-final { scan-assembler "\taddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ +/* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\\$28" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c new file mode 100644 index 000000000..77e0340eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c @@ -0,0 +1,12 @@ +/* { dg-options "-mshared -mabi=64" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c new file mode 100644 index 000000000..8ad6808c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c @@ -0,0 +1,14 @@ +/* { dg-options "-mshared -mabi=64" } */ +/* { dg-final { scan-assembler "\tdaddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\\$28" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c new file mode 100644 index 000000000..ba5f95437 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=32" } */ +/* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c new file mode 100644 index 000000000..cad1c003c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c @@ -0,0 +1,18 @@ +/* { dg-options "-mshared -mabi=32" } */ +/* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */ +/* { dg-final { scan-assembler "\t\\.cprestore\t16\n" } } */ +/* { dg-final { scan-assembler "\tlw\t\\\$1,16\\(\\\$(fp|sp)\\)\n" } } */ +/* { dg-final { scan-assembler "\tlw\t\\\$1,%got\\(\[^)\]*\\)\\(\\\$1\\)\n" } } */ +/* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%lo\\(\[^)\]*\\)\n" } } */ +/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\\$28" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0x1fffc; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c new file mode 100644 index 000000000..f72f2acfb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c @@ -0,0 +1,9 @@ +/* { dg-options "-mbranch-cost=1 isa>=4" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +NOMIPS16 int +foo (int x, int y, int z, int k) +{ + return x == k ? x + y : z - x; +} +/* { dg-final { scan-assembler-not "\t(movz|movn)\t" } } */ +/* { dg-final { scan-assembler "\t(bne|beq)\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c new file mode 100644 index 000000000..3b2c4a13e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c @@ -0,0 +1,9 @@ +/* { dg-options "-mbranch-cost=10 isa>=4" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +NOMIPS16 int +foo (int x, int y, int z, int k) +{ + return x == k ? x + y : z - x; +} +/* { dg-final { scan-assembler "\t(movz|movn)\t" } } */ +/* { dg-final { scan-assembler-not "\t(bne|beq)\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h new file mode 100644 index 000000000..85399be4c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h @@ -0,0 +1,37 @@ +/* DN(X) generates 2**N copies of asm instruction X. */ +#define D0(X) X +#define D1(X) X "\n\t" X +#define D2(X) D1 (D1 (X)) +#define D3(X) D2 (D1 (X)) +#define D4(X) D2 (D2 (X)) +#define D5(X) D4 (D1 (X)) +#define D6(X) D4 (D2 (X)) +#define D7(X) D4 (D2 (D1 (X))) +#define D8(X) D4 (D4 (X)) +#define D9(X) D8 (D1 (X)) +#define D10(X) D8 (D2 (X)) +#define D11(X) D8 (D2 (D1 (X))) +#define D12(X) D8 (D4 (X)) +#define D13(X) D8 (D4 (D1 (X))) +#define D14(X) D8 (D4 (D2 (X))) + +/* Emit something that is 0x1fff8 bytes long, which is the largest + permissible range for non-MIPS16 forward branches. */ +#define OCCUPY_0x1fff8 \ + asm (D14 ("nop") "\n\t" \ + D13 ("nop") "\n\t" \ + D12 ("nop") "\n\t" \ + D11 ("nop") "\n\t" \ + D10 ("nop") "\n\t" \ + D9 ("nop") "\n\t" \ + D8 ("nop") "\n\t" \ + D7 ("nop") "\n\t" \ + D6 ("nop") "\n\t" \ + D5 ("nop") "\n\t" \ + D4 ("nop") "\n\t" \ + D3 ("nop") "\n\t" \ + D2 ("nop") "\n\t" \ + D1 ("nop")) + +/* Likewise emit something that is 0x1fffc bytes long. */ +#define OCCUPY_0x1fffc do { asm ("nop"); OCCUPY_0x1fff8; } while (0) diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c new file mode 100644 index 000000000..24016f269 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return ((x << 8) & 0xff00) | ((x >> 8) & 0xff); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c new file mode 100644 index 000000000..e0ca496b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c @@ -0,0 +1,9 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return __builtin_bswap16 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c new file mode 100644 index 000000000..5d2086fd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c @@ -0,0 +1,14 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c new file mode 100644 index 000000000..ac37a0114 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c new file mode 100644 index 000000000..45520e4ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c @@ -0,0 +1,20 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c new file mode 100644 index 000000000..1145357fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c @@ -0,0 +1,12 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c new file mode 100644 index 000000000..f5c3dd307 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c @@ -0,0 +1,31 @@ +/* { dg-options "isa>=3" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 void +f1 (int *area) +{ + __builtin_mips_cache (20, area); +} + +NOMIPS16 void +f2 (const short *area) +{ + __builtin_mips_cache (24, area + 10); +} + +NOMIPS16 void +f3 (volatile unsigned int *area, int offset) +{ + __builtin_mips_cache (0, area + offset); +} + +NOMIPS16 void +f4 (const volatile unsigned char *area) +{ + __builtin_mips_cache (4, area - 80); +} + +/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c new file mode 100644 index 000000000..e4b7acefa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c @@ -0,0 +1,49 @@ +/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=32" } */ +/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrs?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrs?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrs?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */ + +__attribute__ ((noinline)) static void staticfunc () { asm (""); } +int normal (); +void normal2 (); + +NOMIPS16 f (int *p) +{ + *p = normal (); + normal2 (); + staticfunc (); + return 1; +} + +int tail (); + +NOMIPS16 h () +{ + return tail (); +} + +void tail2 (); + +NOMIPS16 void g () +{ + tail2 (); +} + +__attribute__ ((visibility ("hidden"))) void tail3 (); + +NOMIPS16 void j () +{ + tail3 (); +} + +__attribute__ ((noinline)) static void tail4 () { asm (""); } + +NOMIPS16 void k () +{ + tail4 (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c new file mode 100644 index 000000000..c2fc8eaad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c @@ -0,0 +1,10 @@ +/* See through some simple data-flow. */ +/* { dg-options "-mrelax-pic-calls" } */ +/* { dg-final { scan-assembler-times "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" 2 } } */ + +NOMIPS16 f () +{ + g (); + g (); + return 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c new file mode 100644 index 000000000..37609088d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c @@ -0,0 +1,11 @@ +/* { dg-options "-mrelax-pic-calls -mno-shared" } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" } } */ +/* { dg-require-visibility "" } */ + +__attribute__ ((visibility ("hidden"))) void g (); + +NOMIPS16 f () +{ + g (); + return 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c new file mode 100644 index 000000000..049e33882 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c @@ -0,0 +1,9 @@ +/* See through some simple data-flow. */ +/* { dg-options "-mrelax-pic-calls" } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalr\t" } } */ + +NOMIPS16 f (int i) +{ + while (i--) + g (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c new file mode 100644 index 000000000..2e58178ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c @@ -0,0 +1,51 @@ +/* Like call-1.c, but for n32. We cannot use sibling calls for tail and tail2 + in this case (PR target/57260). */ +/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=n32" } */ +/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */ + +__attribute__ ((noinline)) static void staticfunc () { asm (""); } +int normal (); +void normal2 (); + +NOMIPS16 f (int *p) +{ + *p = normal (); + normal2 (); + staticfunc (); + return 1; +} + +int tail (); + +NOMIPS16 h () +{ + return tail (); +} + +void tail2 (); + +NOMIPS16 void g () +{ + tail2 (); +} + +__attribute__ ((visibility ("hidden"))) void tail3 (); + +NOMIPS16 void j () +{ + tail3 (); +} + +__attribute__ ((noinline)) static void tail4 () { asm (""); } + +NOMIPS16 void k () +{ + tail4 (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c new file mode 100644 index 000000000..86f3dc4a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c @@ -0,0 +1,50 @@ +/* Like call-5.c, but for n64. */ +/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=64" } */ +/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */ + +__attribute__ ((noinline)) static void staticfunc () { asm (""); } +int normal (); +void normal2 (); + +NOMIPS16 f (int *p) +{ + *p = normal (); + normal2 (); + staticfunc (); + return 1; +} + +int tail (); + +NOMIPS16 h () +{ + return tail (); +} + +void tail2 (); + +NOMIPS16 void g () +{ + tail2 (); +} + +__attribute__ ((visibility ("hidden"))) void tail3 (); + +NOMIPS16 void j () +{ + tail3 (); +} + +__attribute__ ((noinline)) static void tail4 () { asm (""); } + +NOMIPS16 void k () +{ + tail4 (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c new file mode 100644 index 000000000..5c86b6c8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c @@ -0,0 +1,21 @@ +/* Check that we save all call-saved GPRs in a MIPS16 __builtin_eh_return + function. */ +/* { dg-options "(-mips16) isa_rev=0" } */ + +void bar (void); + +MIPS16 void +foo (int x) +{ + __builtin_unwind_init (); + __builtin_eh_return (x, bar); +} +/* { dg-final { scan-assembler "\\\$16" } } */ +/* { dg-final { scan-assembler "\\\$17" } } */ +/* { dg-final { scan-assembler "\\\$18" } } */ +/* { dg-final { scan-assembler "\\\$19" } } */ +/* { dg-final { scan-assembler "\\\$20" } } */ +/* { dg-final { scan-assembler "\\\$21" } } */ +/* { dg-final { scan-assembler "\\\$22" } } */ +/* { dg-final { scan-assembler "\\\$23" } } */ +/* { dg-final { scan-assembler "\\\$(30|fp)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c new file mode 100644 index 000000000..b55c30ab0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c @@ -0,0 +1,19 @@ +/* Check that we save non-MIPS16 GPRs if they are explicitly clobbered. */ +/* { dg-options "(-mips16) isa_rev=0" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ + +MIPS16 void +foo (void) +{ + asm volatile ("" ::: "$19", "$23", "$24", "$30"); +} +/* { dg-final { scan-assembler-not "\\\$16" } } */ +/* { dg-final { scan-assembler-not "\\\$17" } } */ +/* { dg-final { scan-assembler-not "\\\$18" } } */ +/* { dg-final { scan-assembler "\\\$19" } } */ +/* { dg-final { scan-assembler-not "\\\$20" } } */ +/* { dg-final { scan-assembler-not "\\\$21" } } */ +/* { dg-final { scan-assembler-not "\\\$22" } } */ +/* { dg-final { scan-assembler "\\\$23" } } */ +/* { dg-final { scan-assembler-not "\\\$24" } } */ +/* { dg-final { scan-assembler "\\\$(30|fp)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c new file mode 100644 index 000000000..84cdb3b88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c @@ -0,0 +1,22 @@ +/* Check that we save all call-saved GPRs in a MIPS16 __builtin_setjmp + function. */ +/* { dg-options "(-mips16) isa_rev=0" } */ + +void bar (void); +extern int buf[]; + +MIPS16 void +foo (int x) +{ + if (__builtin_setjmp (buf) == 0) + bar(); +} +/* { dg-final { scan-assembler "\\\$16" } } */ +/* { dg-final { scan-assembler "\\\$17" } } */ +/* { dg-final { scan-assembler "\\\$18" } } */ +/* { dg-final { scan-assembler "\\\$19" } } */ +/* { dg-final { scan-assembler "\\\$20" } } */ +/* { dg-final { scan-assembler "\\\$21" } } */ +/* { dg-final { scan-assembler "\\\$22" } } */ +/* { dg-final { scan-assembler "\\\$23" } } */ +/* { dg-final { scan-assembler "\\\$(30|fp)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c new file mode 100644 index 000000000..f1554f593 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msynci isa_rev>=2" } */ +/* { dg-final { scan-assembler "\tsynci\t" } } */ +/* { dg-final { scan-assembler "\tjr.hb\t" } } */ +/* { dg-final { scan-assembler-not "_flush_cache|mips_sync_icache|_cacheflush" } } */ + +NOMIPS16 void f() +{ + int size = 40; + char *memory = __builtin_alloca(size); + __builtin___clear_cache(memory, memory + size); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c new file mode 100644 index 000000000..f1f7f8190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mips32" } */ +/* { dg-final { scan-assembler-not "\tsynci" } } */ +/* { dg-final { scan-assembler-not "\tjr.hb" } } */ +/* { dg-final { scan-assembler "_flush_cache|mips_sync_icache|_cacheflush" } } */ + +void f() +{ + int size = 40; + char *memory = __builtin_alloca(size); + __builtin___clear_cache(memory, memory + size); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c new file mode 100644 index 000000000..b3e864df6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c @@ -0,0 +1,51 @@ +/* { dg-options "(-mips16) -mcode-readable=yes -mgp32 addressing=absolute" } */ +/* { dg-skip-if ".half requires -O" { *-*-* } { "-O0" } { "" } } */ + +volatile int x1; +volatile int x2; +volatile int x3; +volatile int x4; +volatile int x5; +volatile int x6; +volatile int x7; +volatile int x8; +volatile int x9; +volatile int x10; +volatile int x11; + +MIPS16 int +foo (int i, volatile *x) +{ + switch (i) + { + case 1: return x1 + x[0]; + case 2: return x2 + x[1]; + case 3: return x3 + x[2]; + case 4: return x4 + x[3]; + case 5: return x5 + x[4]; + case 6: return x6 + x[5]; + case 7: return x7 + x[6]; + case 8: return x8 + x[7]; + case 9: return x9 + x[8]; + case 10: return x10 + x[9]; + case 11: return x11 + x[10]; + default: return 0; + } +} + +extern int k[]; + +MIPS16 int * +bar (void) +{ + return k; +} + +/* { dg-final { scan-assembler "\tla\t" } } */ +/* { dg-final { scan-assembler "\t\\.half\t" } } */ +/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */ +/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */ + +/* { dg-final { scan-assembler "\t\\.word\tk\n" } } */ +/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */ +/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c new file mode 100644 index 000000000..3d325049d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c @@ -0,0 +1,49 @@ +/* { dg-options "(-mips16) -mcode-readable=pcrel -mgp32 addressing=absolute" } */ + +volatile int x1; +volatile int x2; +volatile int x3; +volatile int x4; +volatile int x5; +volatile int x6; +volatile int x7; +volatile int x8; +volatile int x9; +volatile int x10; +volatile int x11; + +MIPS16 int +foo (int i, volatile *x) +{ + switch (i) + { + case 1: return x1 + x[0]; + case 2: return x2 + x[1]; + case 3: return x3 + x[2]; + case 4: return x4 + x[3]; + case 5: return x5 + x[4]; + case 6: return x6 + x[5]; + case 7: return x7 + x[6]; + case 8: return x8 + x[7]; + case 9: return x9 + x[8]; + case 10: return x10 + x[9]; + case 11: return x11 + x[10]; + default: return 0; + } +} + +extern int k[]; + +MIPS16 int * +bar (void) +{ + return k; +} + +/* { dg-final { scan-assembler-not "\tla\t" } } */ +/* { dg-final { scan-assembler-not "\t\\.half\t" } } */ +/* { dg-final { scan-assembler "\t\\.word\t\[^\n\]*L" } } */ + +/* { dg-final { scan-assembler "\t\\.word\tk\n" } } */ +/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */ +/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c new file mode 100644 index 000000000..aaf187493 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c @@ -0,0 +1,50 @@ +/* { dg-options "(-mips16) -mcode-readable=no -mgp32 addressing=absolute" } */ + +volatile int x1; +volatile int x2; +volatile int x3; +volatile int x4; +volatile int x5; +volatile int x6; +volatile int x7; +volatile int x8; +volatile int x9; +volatile int x10; +volatile int x11; + +MIPS16 int +foo (int i, volatile *x) +{ + switch (i) + { + case 1: return x1 + x[0]; + case 2: return x2 + x[1]; + case 3: return x3 + x[2]; + case 4: return x4 + x[3]; + case 5: return x5 + x[4]; + case 6: return x6 + x[5]; + case 7: return x7 + x[6]; + case 8: return x8 + x[7]; + case 9: return x9 + x[8]; + case 10: return x10 + x[9]; + case 11: return x11 + x[10]; + default: return 0; + } +} + +extern int k[]; + +MIPS16 int * +bar (void) +{ + return k; +} + +/* { dg-final { scan-assembler-not "\tla\t" } } */ +/* { dg-final { scan-assembler-not "\t\\.half\t" } } */ +/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */ +/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */ + +/* { dg-final { scan-assembler-not "\t\\.word\tk\n" } } */ +/* { dg-final { scan-assembler "%hi\\(k\\)" } } */ +/* { dg-final { scan-assembler "%lo\\(k\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c new file mode 100644 index 000000000..4db89f874 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c @@ -0,0 +1,51 @@ +/* { dg-options "(-mips16) -mcode-readable=yes -mabi=eabi -mgp64" } */ +/* { dg-skip-if ".half requires -O" { *-*-* } { "-O0" } { "" } } */ + +volatile int x1; +volatile int x2; +volatile int x3; +volatile int x4; +volatile int x5; +volatile int x6; +volatile int x7; +volatile int x8; +volatile int x9; +volatile int x10; +volatile int x11; + +MIPS16 int +foo (int i, volatile *x) +{ + switch (i) + { + case 1: return x1 + x[0]; + case 2: return x2 + x[1]; + case 3: return x3 + x[2]; + case 4: return x4 + x[3]; + case 5: return x5 + x[4]; + case 6: return x6 + x[5]; + case 7: return x7 + x[6]; + case 8: return x8 + x[7]; + case 9: return x9 + x[8]; + case 10: return x10 + x[9]; + case 11: return x11 + x[10]; + default: return 0; + } +} + +extern int k[]; + +MIPS16 int * +bar (void) +{ + return k; +} + +/* { dg-final { scan-assembler "\tla\t" } } */ +/* { dg-final { scan-assembler "\t\\.half\t" } } */ +/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */ +/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */ + +/* { dg-final { scan-assembler "\t\\.dword\tk\n" } } */ +/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */ +/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c new file mode 100644 index 000000000..a5f01e4ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c @@ -0,0 +1,10 @@ +/* Derive a constant (0x1233ffff) from an intermediate value + (0x1234000) used to build another constant. */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "0x12330000|305332224" } } */ +/* { dg-final { scan-assembler "\td?addiu\t\\\$5,\\\$\[0-9\]*,-1" } } */ + +NOMIPS16 void f () +{ + g (0x12340001, 0x1233ffff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c new file mode 100644 index 000000000..8dad5a70b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c @@ -0,0 +1,9 @@ +/* Derive a constant (0x30001) from another constant. */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "0x300000|196608" } } */ +/* { dg-final { scan-assembler "\td?addiu\t\\\$5,\\\$\[0-9\]*,32763" } } */ + +NOMIPS16 void f () +{ + g (0x28006, 0x30001); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c new file mode 100644 index 000000000..08234a6e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c new file mode 100644 index 000000000..fb8953def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c new file mode 100644 index 000000000..ff129292a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c new file mode 100644 index 000000000..57866ceb0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c new file mode 100644 index 000000000..cf746a663 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c @@ -0,0 +1,17 @@ +/* { dg-options "(-mips16) -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +typedef int int32_t; +typedef unsigned int uint32_t; +typedef long long int64_t; +typedef unsigned long long uint64_t; + +MIPS16 int32_t f1 (int32_t x, int32_t y) { return x / y + x % y; } +MIPS16 uint32_t f2 (uint32_t x, uint32_t y) { return x / y + x % y; } +MIPS16 int64_t f3 (int64_t x, int64_t y) { return x / y + x % y; } +MIPS16 uint64_t f4 (uint64_t x, uint64_t y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tdiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tdivu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tddiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tddivu\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c new file mode 100644 index 000000000..257ca923d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c new file mode 100644 index 000000000..b9ae3684e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c new file mode 100644 index 000000000..5f05d8e78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tddivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c new file mode 100644 index 000000000..294cc7f24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c new file mode 100644 index 000000000..fb8953def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c new file mode 100644 index 000000000..ff129292a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c new file mode 100644 index 000000000..57866ceb0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdivu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x % y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c new file mode 100644 index 000000000..294cc7f24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c @@ -0,0 +1,12 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-final { scan-assembler "\tdiv\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x / y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c new file mode 100644 index 000000000..f8c0b8b44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c @@ -0,0 +1,10 @@ +/* { dg-options "forbid_cpu=octeon.* -mgp64" } */ +/* { dg-final { scan-assembler "\tdmult\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tdmul\t" } } */ + +long long +f (long long a, long long b) +{ + return a * b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c new file mode 100644 index 000000000..a48f561f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { fixed_point } } } */ +/* This test requires widening_mul */ +/* { dg-options "-mgp32 -mdsp -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tdpaq_sa.l.w\t\\\$ac" 3 } } */ + +NOMIPS16 _Sat long long _Fract +f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) +{ + return (_Sat long long _Fract) x * y + z; +} + +NOMIPS16 _Sat long long _Fract +f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) +{ + return z + (_Sat long long _Fract) y * x; +} + +NOMIPS16 _Sat long long _Fract +f3 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) +{ + _Sat long long _Fract t = (_Sat long long _Fract) x * y; + int temp = 5; + if (temp == 5) + z = t + z; /* Need to put z at the end. GCC does not swap operands to + match the ssmadd pattern, because types are saturating. */ + return z; +} + +long long _Fract +f4 (long _Fract x, long _Fract y, long long _Fract z) +{ + return (long long _Fract) x * y + z; +} + +long long _Fract +f5 (long _Fract x, long _Fract y, long long _Fract z) +{ + return z + (long long _Fract) y * x; +} + +long long _Fract +f6 (long _Fract x, long _Fract y, long long _Fract z) +{ + long long _Fract t = (long long _Fract) x * y; + int temp = 5; + if (temp == 5) + z = t + z; /* Need to put z at the end. GCC does not swap operands to + match the ssmadd pattern, because types are saturating. */ + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c new file mode 100644 index 000000000..fb63a1db8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { fixed_point } } } */ +/* This test requires widening_mul */ +/* { dg-options "-mgp32 -mdsp -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tdpsq_sa.l.w\t\\\$ac" 2 } } */ + +NOMIPS16 _Sat long long _Fract +f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) +{ + return z - (_Sat long long _Fract) x * y; +} + +NOMIPS16 _Sat long long _Fract +f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) +{ + _Sat long long _Fract t = (_Sat long long _Fract) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} + +long long _Fract +f3 (long _Fract x, long _Fract y, long long _Fract z) +{ + return z - (long long _Fract) x * y; +} + +long long _Fract +f4 (long _Fract x, long _Fract y, long long _Fract z) +{ + long long _Fract t = (long long _Fract) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c new file mode 100644 index 000000000..e53189cad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(ID, TYPE1, TYPE2) \ + union u##ID { \ + TYPE1 m1[sizeof (TYPE2) / sizeof (TYPE1)]; \ + TYPE2 m2; \ + }; \ + \ + /* The MIPS16 versions of the shifts we need are too \ + expensive. */ \ + TYPE1 __attribute__((nomips16)) \ + f##ID (TYPE2 x, union u##ID *u) \ + { \ + u->m2 = x; \ + return (u->m1[0] \ + + u->m1[sizeof (TYPE2) / sizeof (TYPE1) - 1]); \ + } \ + \ + TYPE1 __attribute__((nomips16)) \ + g##ID (union u##ID *u) \ + { \ + u->m2 = 0; \ + return (u->m1[0] | u->m1[1]); \ + } + +TEST (1, unsigned int, unsigned long long); +TEST (2, int, long long); +TEST (3, unsigned short, unsigned long long); +TEST (4, short, long long); +TEST (5, unsigned char, unsigned long long); +TEST (6, signed char, long long); + +TEST (7, unsigned short, unsigned int); +TEST (8, short, int); +TEST (9, unsigned char, unsigned int); +TEST (10, signed char, int); + +TEST (11, unsigned char, unsigned short); +TEST (12, signed char, short); + +/* { dg-final { scan-assembler-not "\tlh\t" } } */ +/* { dg-final { scan-assembler-not "\tlhu\t" } } */ +/* { dg-final { scan-assembler-not "\tlw\t" } } */ +/* { dg-final { scan-assembler-not "\tlwu\t" } } */ +/* { dg-final { scan-assembler-not "\tlb\t" } } */ +/* { dg-final { scan-assembler-not "\tlbu\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c new file mode 100644 index 000000000..4bf449b86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c @@ -0,0 +1,69 @@ +/* { dg-do run } */ +/* { dg-options "-mdsp -mgp32" } */ + +extern void abort (void); +extern void exit (int); + +NOMIPS16 void __attribute__ ((noinline)) +test1 (int i) +{ + __builtin_mips_wrdsp (i, 63); +} + +NOMIPS16 void __attribute__ ((noinline)) +test2 () +{ + long long a = 0; + __builtin_mips_extpdp (a, 3); +} + +NOMIPS16 void __attribute__ ((noinline)) +test3 (int i) +{ + long long a = 0; + __builtin_mips_extpdp (a, i); +} + +NOMIPS16 void __attribute__ ((noinline)) +test4 () +{ + long long a = 0; + int i = 0; + __builtin_mips_mthlip (a, i); +} + +NOMIPS16 int +main () +{ + int cntl; + + /* Test 1: wrdsp */ + __builtin_mips_wrdsp (0,63); + test1 (63); + cntl = __builtin_mips_rddsp (63); + if (cntl != 63) + abort (); + + /* Test 2: extpdp */ + __builtin_mips_wrdsp (63,63); + test2 (); + cntl = __builtin_mips_rddsp (63); + if (cntl != 59) + abort (); + + /* Test 3: extpdpv */ + __builtin_mips_wrdsp (63,63); + test3 (10); + cntl = __builtin_mips_rddsp (63); + if (cntl != 52) + abort (); + + /* Test 4: mthlip */ + __builtin_mips_wrdsp (8,63); + test4 (); + cntl = __builtin_mips_rddsp (63); + if (cntl != 40) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c new file mode 100644 index 000000000..8fa20a090 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c @@ -0,0 +1,11 @@ +/* Test MIPS32 DSP LHX instruction */ +/* { dg-do compile } */ +/* { dg-options "-mgp32 -mdsp" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler "\tlhx\t" } } */ + +NOMIPS16 signed short test (signed short *a, int index) +{ + return a[index]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c new file mode 100644 index 000000000..42c4688cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c @@ -0,0 +1,10 @@ +/* Test MIPS32 DSP LHX instruction */ +/* { dg-do compile } */ +/* { dg-options "-mgp32 -mdsp" } */ + +/* { dg-final { scan-assembler-not "\tlhx\t" } } */ + +NOMIPS16 unsigned short test (unsigned short *a, int index) +{ + return a[index]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c new file mode 100644 index 000000000..b668e0c6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c @@ -0,0 +1,19 @@ +/* Test MIPS32 DSP REV 2 MULT instruction. Tune for a CPU that has + pipelined mult. */ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-mgp32 -mdspr2 -mtune=74kc -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* See PR target/51729 for the reason behind the XFAILs. */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\\\$ac1" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "\\\$ac2" { xfail *-*-* } } } */ + +typedef long long a64; + +NOMIPS16 a64 test (a64 *a, int *b, int *c) +{ + a[0] = (a64) b[0] * c[0]; + a[1] = (a64) b[1] * c[1]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c new file mode 100644 index 000000000..886e4ca88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c @@ -0,0 +1,18 @@ +/* Test MIPS32 DSP REV 2 MULTU instruction. Tune for a CPU that has + pipelined multu. */ +/* { dg-do compile } */ +/* { dg-options "-mgp32 -mdspr2 -mtune=74kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* See PR target/51729 for the reason behind the XFAILs. */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler "\\\$ac1" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "\\\$ac2" { xfail *-*-* } } } */ + +typedef unsigned long long a64; + +NOMIPS16 a64 test (a64 *a, unsigned int *b, unsigned int *c) +{ + a[0] = (a64) b[0] * c[0]; + a[1] = (a64) b[1] * c[1]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c new file mode 100644 index 000000000..177b5033b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "\tand" } } */ + +struct +{ + unsigned long long a:9; + unsigned long long d:35; + unsigned long long e:10; + unsigned long long f:10; +} t; + +NOMIPS16 unsigned long long +f (void) +{ + return t.d; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c new file mode 100644 index 000000000..320d42d2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c @@ -0,0 +1,15 @@ +/* Turn the truncate,zero_extend,lshiftrt sequence before the or into a + zero_extract. The truncate is due to TARGET_PROMOTE_PROTOTYPES, the + zero_extend to PROMOTE_MODE. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp64 -mlong64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "\tand" } } */ +/* { dg-final { scan-assembler-not "\td?srl" } } */ + +NOMIPS16 void +f (unsigned char x, unsigned char *r) +{ + *r = 0x50 | (x >> 4); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c new file mode 100644 index 000000000..66780551b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c @@ -0,0 +1,15 @@ +/* For MIPS64r2 use DEXT rather than DSLL/DSRL to zero-extend. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "\td?sll" } } */ + +NOMIPS16 unsigned long long +f (unsigned *i) +{ + unsigned j = *i; + j >>= 1; /* enforce this is all done in SI mode */ + j++; /* don't merge the shift and the extension */ + return j; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c new file mode 100644 index 000000000..16b848c35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c @@ -0,0 +1,12 @@ +/* For MIPS64r2 use DEXT rather than DSLL/DSRL for clear_upper32. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "\td?sll" } } */ + +NOMIPS16 unsigned long long +f (unsigned long long i) +{ + return i & 0xffffffffull; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c new file mode 100644 index 000000000..8bab2148f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c @@ -0,0 +1,12 @@ +/* For MIPS32r2 use EXT when ANDing with low-order bitmasks. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\text\t" } } */ +/* { dg-final { scan-assembler-not "\tandi?\t" } } */ + +NOMIPS16 unsigned +f (unsigned i) +{ + return i & 0x7ffffff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c new file mode 100644 index 000000000..e12cbe6e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c @@ -0,0 +1,12 @@ +/* For MIPS64r2 use DEXT when ANDing with low-order bitmasks. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "\tandi?\t" } } */ + +NOMIPS16 unsigned long long +f (unsigned long long i) +{ + return i & 0x7ffffffffff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c new file mode 100644 index 000000000..2e23dd652 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c @@ -0,0 +1,12 @@ +/* No need to use ext if we can use andi. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tandi\t" } } */ +/* { dg-final { scan-assembler-not "\td?ext\t" } } */ + +NOMIPS16 unsigned +f (unsigned i) +{ + return i & 0x7fff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c new file mode 100644 index 000000000..9ceee7b9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c @@ -0,0 +1,11 @@ +/* Also make sure we don't use ext for MIPS*r1. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev<=1" } */ +/* { dg-final { scan-assembler "\tand\t" } } */ +/* { dg-final { scan-assembler-not "\td?ext\t" } } */ + +unsigned +f (unsigned i) +{ + return i & 0x7fffff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c new file mode 100644 index 000000000..36f0f3fd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2" } */ +/* { dg-final { scan-assembler "\td?ext\t" } } */ +/* { dg-final { scan-assembler "\td?ins\t" } } */ + +struct A +{ + unsigned int i : 2; + unsigned int j : 3; + unsigned int k : 4; + unsigned int l : 5; +}; + +void func (struct A); + +NOMIPS16 unsigned int f1 (struct A a) +{ + return a.j; +} + +NOMIPS16 struct A f2 (struct A a, int i) +{ + a.j = i; + return a; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c new file mode 100644 index 000000000..9240ea558 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c @@ -0,0 +1,23 @@ +/* { dg-options "-mgp64 forbid_cpu=octeon.*" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */ +/* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */ +/* { dg-final { scan-assembler-not "\tsll\t" } } */ + +#define TEST_CHAR(T, N) \ + NOMIPS16 T \ + f##N (long long d, T *a, T *r) \ + { \ + T b = (signed char) d; *r = b + *a; \ + } +#define TEST_SHORT(T, N) \ + NOMIPS16 T \ + g##N (long long d, T *a, T *r) \ + { \ + T b = (short) d; *r = b + *a; \ + } +#define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N) + +TEST (int, 1); +TEST (long long, 2); +TEST_CHAR (short, 3); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c new file mode 100644 index 000000000..a2036a899 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c @@ -0,0 +1,12 @@ +/* Check the shift_shift alternative of the AND patterns. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev<=1 -mgp64" } */ +/* { dg-final { scan-assembler "\tdsrl\t" } } */ +/* { dg-final { scan-assembler "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\td?ext\t" } } */ + +unsigned long long +f (unsigned long long i) +{ + return i & 0xffffffff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c new file mode 100644 index 000000000..211d561d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=2008" } */ + +NOMIPS16 double +fabs_2008 (double d) +{ + return __builtin_fabs (d); +} + +/* { dg-final { scan-assembler "\tabs\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c new file mode 100644 index 000000000..dabc9d09c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=legacy" } */ + +NOMIPS16 double +fabs_legacy (double d) +{ + return __builtin_fabs (d); +} + +/* { dg-final { scan-assembler-not "\tabs\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c new file mode 100644 index 000000000..2b0363abc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=2008" } */ + +NOMIPS16 float +fabsf_2008 (float f) +{ + return __builtin_fabsf (f); +} + +/* { dg-final { scan-assembler "\tabs\\.s\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c new file mode 100644 index 000000000..7278f7d77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=legacy" } */ + +NOMIPS16 float +fabsf_legacy (float f) +{ + return __builtin_fabsf (f); +} + +/* { dg-final { scan-assembler-not "\tabs\\.s\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c new file mode 100644 index 000000000..edf4d70c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_fetch_and_add (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_fetch_and_add (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_fetch_and_add (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c new file mode 100644 index 000000000..ab353b6b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_and_and_fetch (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_and_and_fetch (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_and_and_fetch (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c new file mode 100644 index 000000000..30f6038b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_xor_and_fetch (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_xor_and_fetch (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_xor_and_fetch (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c new file mode 100644 index 000000000..855000df2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_nand_and_fetch (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_nand_and_fetch (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_nand_and_fetch (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c new file mode 100644 index 000000000..aa2d236f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_bool_compare_and_swap (z, 0, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_bool_compare_and_swap (z, 0, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_bool_compare_and_swap (z, 0, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c new file mode 100644 index 000000000..542e02f9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_val_compare_and_swap (z, 0, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_val_compare_and_swap (z, 0, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_val_compare_and_swap (z, 0, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c new file mode 100644 index 000000000..f44a725ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + int result; + + result = __sync_lock_test_and_set (z, 42); + __sync_lock_release (z); + return result; +} + +NOMIPS16 short +f2 (short *z) +{ + short result; + + result = __sync_lock_test_and_set (z, 42); + __sync_lock_release (z); + return result; +} + +NOMIPS16 char +f3 (char *z) +{ + char result; + + result = __sync_lock_test_and_set (z, 42); + __sync_lock_release (z); + return result; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c new file mode 100644 index 000000000..88a591841 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z, int amt) +{ + return __sync_fetch_and_sub (z, amt); +} + +NOMIPS16 short +f2 (short *z, short amt) +{ + return __sync_fetch_and_sub (z, amt); +} + +NOMIPS16 char +f3 (char *z, char amt) +{ + return __sync_fetch_and_sub (z, amt); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c new file mode 100644 index 000000000..fbeeca10f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_fetch_and_or (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_fetch_and_or (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_fetch_and_or (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c new file mode 100644 index 000000000..344c6277b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_fetch_and_and (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_fetch_and_and (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_fetch_and_and (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c new file mode 100644 index 000000000..a775a6c0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_fetch_and_xor (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_fetch_and_xor (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_fetch_and_xor (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c new file mode 100644 index 000000000..62f8fdfb4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_fetch_and_nand (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_fetch_and_nand (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_fetch_and_nand (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c new file mode 100644 index 000000000..635326c5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_add_and_fetch (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_add_and_fetch (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_add_and_fetch (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c new file mode 100644 index 000000000..68978494d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z, int amt) +{ + return __sync_sub_and_fetch (z, amt); +} + +NOMIPS16 short +f2 (short *z, short amt) +{ + return __sync_sub_and_fetch (z, amt); +} + +NOMIPS16 char +f3 (char *z, char amt) +{ + return __sync_sub_and_fetch (z, amt); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c new file mode 100644 index 000000000..3d140b1bc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mfix-r10000" } */ +/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */ + +NOMIPS16 int +f1 (int *z) +{ + return __sync_or_and_fetch (z, 42); +} + +NOMIPS16 short +f2 (short *z) +{ + return __sync_or_and_fetch (z, 42); +} + +NOMIPS16 char +f3 (char *z) +{ + return __sync_or_and_fetch (z, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c new file mode 100644 index 000000000..5c812f256 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c @@ -0,0 +1,7 @@ +/* { dg-options "-march=r4000 -mfix-r4000 -dp" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef int int32_t; +typedef int uint32_t; +NOMIPS16 int32_t foo (int32_t x, int32_t y) { return x * y; } +NOMIPS16 uint32_t bar (uint32_t x, uint32_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c new file mode 100644 index 000000000..7227bc8c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c @@ -0,0 +1,9 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-options "-mips3 -mfix-r4000 -mgp64 -EL -fno-split-wide-types -dp" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +NOMIPS16 uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c new file mode 100644 index 000000000..1ea7a7c40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c @@ -0,0 +1,6 @@ +/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-skip-if "using DDIV gives a shorter sequence" { *-*-* } { "-Os" } { "" } } */ +typedef long long int64_t; +NOMIPS16 int64_t foo (int64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c new file mode 100644 index 000000000..a2afabbc7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c @@ -0,0 +1,6 @@ +/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-skip-if "using DDIVU gives a shorter sequence" { *-*-* } { "-Os" } { "" } } */ +typedef unsigned long long uint64_t; +NOMIPS16 uint64_t foo (uint64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c new file mode 100644 index 000000000..0261b16b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c @@ -0,0 +1,9 @@ +/* This test requires widening_mul */ +/* { dg-options "-mips1 -mfix-r4000 -dp -EB -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef int int32_t; +typedef long long int64_t; +NOMIPS16 int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c new file mode 100644 index 000000000..195a9d10c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c @@ -0,0 +1,8 @@ +/* { dg-options "-mips1 -mfix-r4000 -dp -EB" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +NOMIPS16 uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c new file mode 100644 index 000000000..7a66182f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c @@ -0,0 +1,10 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* This test requires widening_mul */ +/* { dg-options "-mips1 -mfix-r4000 -fno-split-wide-types -dp -EL -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef int int32_t; +typedef long long int64_t; +NOMIPS16 int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c new file mode 100644 index 000000000..0c0630800 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c @@ -0,0 +1,9 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-options "-mips1 -mfix-r4000 -fno-split-wide-types -dp -EL" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +NOMIPS16 uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c new file mode 100644 index 000000000..9647a900c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c @@ -0,0 +1,7 @@ +/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef long long int64_t; +typedef unsigned long long uint64_t; +NOMIPS16 int64_t foo (int64_t x, int64_t y) { return x * y; } +NOMIPS16 uint64_t bar (uint64_t x, uint64_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c new file mode 100644 index 000000000..ddba30383 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c @@ -0,0 +1,9 @@ +/* This test requires widening_mul */ +/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp -EB -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +NOMIPS16 int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c new file mode 100644 index 000000000..4ae670622 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c @@ -0,0 +1,8 @@ +/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp -EB" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +NOMIPS16 uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c new file mode 100644 index 000000000..316715c59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c @@ -0,0 +1,10 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* This test requires widening_mul */ +/* { dg-options "-mips3 -mfix-r4000 -mgp64 -fno-split-wide-types -dp -EL -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +NOMIPS16 int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c new file mode 100644 index 000000000..f4eb492e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=vr4130 -mfix-vr4130" } */ +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y) +{ + return x % y; +} +/* { dg-final { scan-assembler "\tmacchi\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c new file mode 100644 index 000000000..18708cb45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=vr4130 -mfix-vr4130" } */ +NOMIPS16 int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; } +/* { dg-final { scan-assembler "\tmacc\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c new file mode 100644 index 000000000..d3399d10c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ +NOMIPS16 unsigned long long +foo (unsigned long long x, unsigned long long y) +{ + return x % y; +} +/* { dg-final { scan-assembler "\tdmacchi\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c new file mode 100644 index 000000000..8b307c6e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ +NOMIPS16 long long +foo (void) +{ + long long r; + asm ("# foo" : "=l" (r)); + return r; +} +/* { dg-final { scan-assembler "\tdmacc\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c new file mode 100644 index 000000000..810c82c2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c @@ -0,0 +1,218 @@ +/* Test scalar fixed-point instructions */ +/* { dg-do compile { target { fixed_point } } } */ +/* { dg-options "-mdspr2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\taddu\t" 10 } } */ +/* { dg-final { scan-assembler-times "\tsubu\t" 10 } } */ +/* { dg-final { scan-assembler "\taddu_s.qb\t" } } */ +/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\taddq_s.w\t" 2 } } */ +/* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */ +/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tsubq_s.w\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tmulq_rs.w\t" 1 } } */ + +short _Fract non_sat_test1 (short _Fract a, short _Fract b) +{ + return a + b; +} + +_Fract non_sat_test2 (_Fract a, _Fract b) +{ + return a + b; +} + +long _Fract non_sat_test3 (long _Fract a, long _Fract b) +{ + return a + b; +} + +unsigned short _Fract non_sat_test4 (unsigned short _Fract a, + unsigned short _Fract b) +{ + return a + b; +} + +unsigned _Fract non_sat_test5 (unsigned _Fract a, unsigned _Fract b) +{ + return a + b; +} + +unsigned long _Fract non_sat_test6 (unsigned long _Fract a, + unsigned long _Fract b) +{ + return a + b; +} + +short _Accum non_sat_test7 (short _Accum a, short _Accum b) +{ + return a + b; +} + +_Accum non_sat_test8 (_Accum a, _Accum b) +{ + return a + b; +} + +unsigned short _Accum non_sat_test9 (unsigned short _Accum a, + unsigned short _Accum b) +{ + return a + b; +} + +unsigned _Accum non_sat_test10 (unsigned _Accum a, unsigned _Accum b) +{ + return a + b; +} + +short _Fract non_sat_test11 (short _Fract a, short _Fract b) +{ + return a - b; +} + +_Fract non_sat_test12 (_Fract a, _Fract b) +{ + return a - b; +} + +long _Fract non_sat_test13 (long _Fract a, long _Fract b) +{ + return a - b; +} + +unsigned short _Fract non_sat_test14 (unsigned short _Fract a, + unsigned short _Fract b) +{ + return a - b; +} + +unsigned _Fract non_sat_test15 (unsigned _Fract a, unsigned _Fract b) +{ + return a - b; +} + +unsigned long _Fract non_sat_test16 (unsigned long _Fract a, + unsigned long _Fract b) +{ + return a - b; +} + +short _Accum non_sat_test17 (short _Accum a, short _Accum b) +{ + return a - b; +} + +_Accum non_sat_test18 (_Accum a, _Accum b) +{ + return a - b; +} + +unsigned short _Accum non_sat_test19 (unsigned short _Accum a, + unsigned short _Accum b) +{ + return a - b; +} + +unsigned _Accum non_sat_test20 (unsigned _Accum a, unsigned _Accum b) +{ + return a - b; +} + +NOMIPS16 _Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a, + _Sat unsigned short _Fract b) +{ + return a + b; +} + +NOMIPS16 _Sat unsigned _Fract test2 (_Sat unsigned _Fract a, + _Sat unsigned _Fract b) +{ + return a + b; +} + +NOMIPS16 _Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a, + _Sat unsigned short _Accum b) +{ + return a + b; +} + +NOMIPS16 _Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b) +{ + return a + b; +} + +NOMIPS16 _Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b) +{ + return a + b; +} + +NOMIPS16 _Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b) +{ + return a + b; +} + +NOMIPS16 _Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b) +{ + return a + b; +} + +NOMIPS16 _Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a, + _Sat unsigned short _Fract b) +{ + return a - b; +} + +NOMIPS16 _Sat unsigned _Fract test9 (_Sat unsigned _Fract a, + _Sat unsigned _Fract b) +{ + return a - b; +} + +NOMIPS16 _Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a, + _Sat unsigned short _Accum b) +{ + return a - b; +} + +NOMIPS16 _Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b) +{ + return a - b; +} + +NOMIPS16 _Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b) +{ + return a - b; +} + +NOMIPS16 _Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b) +{ + return a - b; +} + +NOMIPS16 _Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b) +{ + return a - b; +} + +NOMIPS16 _Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b) +{ + return a * b; +} + +NOMIPS16 _Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b) +{ + return a * b; +} + +NOMIPS16 _Fract test17 (_Fract a, _Fract b) +{ + return a * b; +} + +NOMIPS16 long _Fract test18 (long _Fract a, long _Fract b) +{ + return a * b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c new file mode 100644 index 000000000..ddd9660f1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c @@ -0,0 +1,133 @@ +/* Test vector fixed-point instructions */ +/* { dg-do compile { target { fixed_point } } } */ +/* { dg-options "-mdspr2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\taddu_s.qb\t" 1 } } */ +/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tsubu_s.qb\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */ + +typedef _Sat unsigned short _Fract sat_v4uqq __attribute__ ((vector_size(4))); +typedef _Sat unsigned _Fract sat_v2uhq __attribute__ ((vector_size(4))); +typedef _Sat unsigned short _Accum sat_v2uha __attribute__ ((vector_size(4))); +typedef _Sat _Fract sat_v2hq __attribute__ ((vector_size(4))); +typedef _Sat short _Accum sat_v2ha __attribute__ ((vector_size(4))); + +typedef unsigned short _Fract v4uqq __attribute__ ((vector_size(4))); +typedef unsigned _Fract v2uhq __attribute__ ((vector_size(4))); +typedef unsigned short _Accum v2uha __attribute__ ((vector_size(4))); +typedef _Fract v2hq __attribute__ ((vector_size(4))); +typedef short _Accum v2ha __attribute__ ((vector_size(4))); + +NOMIPS16 sat_v2hq test1 (sat_v2hq a, sat_v2hq b) +{ + return a + b; +} + +NOMIPS16 sat_v2ha test2 (sat_v2ha a, sat_v2ha b) +{ + return a + b; +} + +NOMIPS16 sat_v2hq test3 (sat_v2hq a, sat_v2hq b) +{ + return a - b; +} + +NOMIPS16 sat_v2ha test4 (sat_v2ha a, sat_v2ha b) +{ + return a - b; +} + +NOMIPS16 sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b) +{ + return a + b; +} + +NOMIPS16 sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b) +{ + return a + b; +} + +NOMIPS16 sat_v2uha test7 (sat_v2uha a, sat_v2uha b) +{ + return a + b; +} + +NOMIPS16 sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b) +{ + return a - b; +} + +NOMIPS16 sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b) +{ + return a - b; +} + +NOMIPS16 sat_v2uha test10 (sat_v2uha a, sat_v2uha b) +{ + return a - b; +} + +NOMIPS16 sat_v2hq test11 (sat_v2hq a, sat_v2hq b) +{ + return a * b; +} + +NOMIPS16 v2hq test12 (v2hq a, v2hq b) +{ + return a + b; +} + +NOMIPS16 v2hq test13 (v2hq a, v2hq b) +{ + return a - b; +} + +NOMIPS16 v2hq test14 (v2hq a, v2hq b) +{ + return a * b; +} + +NOMIPS16 v2ha test15 (v2ha a, v2ha b) +{ + return a + b; +} + +NOMIPS16 v2ha test16 (v2ha a, v2ha b) +{ + return a - b; +} + +NOMIPS16 v4uqq test17 (v4uqq a, v4uqq b) +{ + return a + b; +} + +NOMIPS16 v4uqq test18 (v4uqq a, v4uqq b) +{ + return a - b; +} + +NOMIPS16 v2uhq test19 (v2uhq a, v2uhq b) +{ + return a + b; +} + +NOMIPS16 v2uhq test20 (v2uhq a, v2uhq b) +{ + return a - b; +} + +NOMIPS16 v2uha test21 (v2uha a, v2uha b) +{ + return a + b; +} + +NOMIPS16 v2uha test22 (v2uha a, v2uha b) +{ + return a - b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c new file mode 100644 index 000000000..899268af7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=2008" } */ + +NOMIPS16 double +fneg_2008 (double d) +{ + return -d; +} + +/* { dg-final { scan-assembler "\tneg\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c new file mode 100644 index 000000000..38f810cf9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=legacy" } */ + +NOMIPS16 double +fneg_legacy (double d) +{ + return -d; +} + +/* { dg-final { scan-assembler-not "\tneg\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c new file mode 100644 index 000000000..a64a6e693 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=2008" } */ + +NOMIPS16 float +fnegf_2008 (float f) +{ + return -f; +} + +/* { dg-final { scan-assembler "\tneg\\.s\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c new file mode 100644 index 000000000..e628c2bd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mabs=legacy" } */ + +NOMIPS16 float +fnegf_legacy (float f) +{ + return -f; +} + +/* { dg-final { scan-assembler-not "\tneg\\.s\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c new file mode 100644 index 000000000..c0594ff35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c @@ -0,0 +1,6 @@ +/* We used to use c.lt.fmt instead of c.ule.fmt here. */ +/* { dg-options "-mhard-float" } */ +NOMIPS16 int f1 (float x, float y) { return __builtin_isless (x, y); } +NOMIPS16 int f2 (double x, double y) { return __builtin_isless (x, y); } +/* { dg-final { scan-assembler "\tc\\.ule\\.s\t" } } */ +/* { dg-final { scan-assembler "\tc\\.ule\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c new file mode 100644 index 000000000..23d5cb0c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c @@ -0,0 +1,6 @@ +/* We used to use c.le.fmt instead of c.ult.fmt here. */ +/* { dg-options "-mhard-float" } */ +NOMIPS16 int f1 (float x, float y) { return __builtin_islessequal (x, y); } +NOMIPS16 int f2 (double x, double y) { return __builtin_islessequal (x, y); } +/* { dg-final { scan-assembler "\tc\\.ult\\.s\t" } } */ +/* { dg-final { scan-assembler "\tc\\.ult\\.d\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c new file mode 100644 index 000000000..51a5f1723 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c @@ -0,0 +1,27 @@ +/* { dg-options "-mabi=32 -mhard-float -mips1 -EL" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 void +foo (double d, double *x) +{ + *x = d; +} + +NOMIPS16 double +bar (double d) +{ + register double l1 asm ("$8") = d; + register double l2 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm volatile ("#foo" :: "f" (l2)); + return l1; +} + +/* { dg-final { scan-assembler "\tswc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tswc1\t\\\$f13,4\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f13\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f1\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c new file mode 100644 index 000000000..ffe614fcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c @@ -0,0 +1,27 @@ +/* { dg-options "-mabi=32 -mhard-float -mips1 -EB" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 void +foo (double d, double *x) +{ + *x = d; +} + +NOMIPS16 double +bar (double d) +{ + register double l1 asm ("$8") = d; + register double l2 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm volatile ("#foo" :: "f" (l2)); + return l1; +} + +/* { dg-final { scan-assembler "\tswc1\t\\\$f12,4\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tswc1\t\\\$f13,0\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f13\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f1\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c new file mode 100644 index 000000000..80db0710c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c @@ -0,0 +1,19 @@ +/* { dg-options "-mabi=32 -mfp64 -EL" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 double +foo (double d) +{ + register double l1 asm ("$8") = d; + register double l2 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm volatile ("#foo" :: "f" (l2)); + return l1; +} + +/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmfhc1\t\\\$9,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tmthc1\t\\\$9,\\\$f0\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c new file mode 100644 index 000000000..d8f78586c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c @@ -0,0 +1,19 @@ +/* { dg-options "-mabi=32 -mfp64 -EB" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 double +foo (double d) +{ + register double l1 asm ("$8") = d; + register double l2 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm volatile ("#foo" :: "f" (l2)); + return l1; +} + +/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmfhc1\t\\\$8,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tmthc1\t\\\$8,\\\$f0\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c new file mode 100644 index 000000000..18d888049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c @@ -0,0 +1,35 @@ +/* { dg-options "-mabi=64 -mhard-float -EL" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-require-effective-target mips_newabi_large_long_double } */ + +NOMIPS16 void +foo (long double d, long double *x) +{ + *x = d; +} + +NOMIPS16 long double +bar (long double d, long double *x) +{ + register long double l1 asm ("$8") = d; + register long double l2 asm ("$10") = x[1]; + register long double l3 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm ("#foo" : "=d" (l2) : "d" (l2)); + asm volatile ("#foo" :: "f" (l3)); + x[1] = l1; + return l2; +} + +/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */ +/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c new file mode 100644 index 000000000..30a83ec66 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c @@ -0,0 +1,35 @@ +/* { dg-options "-mabi=64 -mhard-float -EB" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-require-effective-target mips_newabi_large_long_double } */ + +NOMIPS16 void +foo (long double d, long double *x) +{ + *x = d; +} + +NOMIPS16 long double +bar (long double d, long double *x) +{ + register long double l1 asm ("$8") = d; + register long double l2 asm ("$10") = x[1]; + register long double l3 asm ("$f20") = 0.0; + asm ("#foo" : "=d" (l1) : "d" (l1)); + asm ("#foo" : "=d" (l2) : "d" (l2)); + asm volatile ("#foo" :: "f" (l3)); + x[1] = l1; + return l2; +} + +/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */ +/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */ +/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */ +/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c new file mode 100644 index 000000000..56d7ccd63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c @@ -0,0 +1,36 @@ +/* { dg-options "(-mips16) -mabi=64 -EL" } */ + +extern long double g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 long double +foo (long double i1, long double i2, long double i3, long double i4, + long double *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = 1.0; + x[3] = g[4]; + x[4] = *(long double *) (lstuff + 0x7fff); + return *(long double *) (gstuff + 0x7fff); +} + +MIPS16 long double +bar (long double i1, long double i2, long double i3, long double i4, + long double *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = 1.0; + x[3] = g[4]; + x[4] = *(long double *) (lstuff + 0x7fff); + return *(long double *) (gstuff + 0x7fff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c new file mode 100644 index 000000000..bf64193b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c @@ -0,0 +1,36 @@ +/* { dg-options "(-mips16) -mabi=64 -EB" } */ + +extern long double g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 long double +foo (long double i1, long double i2, long double i3, long double i4, + long double *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = 1.0; + x[3] = g[4]; + x[4] = *(long double *) (lstuff + 0x7fff); + return *(long double *) (gstuff + 0x7fff); +} + +MIPS16 long double +bar (long double i1, long double i2, long double i3, long double i4, + long double *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = 1.0; + x[3] = g[4]; + x[4] = *(long double *) (lstuff + 0x7fff); + return *(long double *) (gstuff + 0x7fff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c new file mode 100644 index 000000000..74df7de14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c @@ -0,0 +1,22 @@ +/* { dg-do preprocess } */ +/* { dg-options "isa>=2 -mgp32" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c new file mode 100644 index 000000000..3a03ba349 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c @@ -0,0 +1,22 @@ +/* { dg-do preprocess } */ +/* { dg-options "-mgp64" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c new file mode 100644 index 000000000..b47a2ceb2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c @@ -0,0 +1,21 @@ +/* { dg-options "isa>=2 -mgp32 -mips16" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c new file mode 100644 index 000000000..78a12440a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c @@ -0,0 +1,21 @@ +/* { dg-options "-mgp64 -mips16" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c new file mode 100644 index 000000000..46379b257 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c @@ -0,0 +1,9 @@ +/* { dg-options "-mhard-float" } */ + +NOMIPS16 unsigned int +foo (void) +{ + return __builtin_mips_get_fcsr (); +} + +/* { dg-final { scan-assembler "cfc1\t\\\$2,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c new file mode 100644 index 000000000..29a97d309 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-mhard-float (-mips16)" } */ + +MIPS16 unsigned int +foo (void) +{ + return __builtin_mips_get_fcsr (); +} + +/* { dg-final { scan-assembler "__mips16_get_fcsr" } } */ +/* { dg-final { scan-assembler "cfc1\t\\\$2,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c new file mode 100644 index 000000000..02bb8ae9e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tins\t" } } */ + +struct +{ + unsigned int i : 2; + unsigned int j : 3; + unsigned int k : 4; +} s; + +NOMIPS16 void +foo (void) +{ + s.j = 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c new file mode 100644 index 000000000..916bc4b5e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-meb isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tins\t|\tdins\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tsll\t|\tins\t" 1 } } */ + +/* When inserting something into the top bit of a 32-bit structure, + we must make sure that the register remains properly sign-extended. + There are two ways of doing this: + + - use purely 32-bit bit manipulations (a single INS, matched twice here). + - use a 64-bit bit manipulation (DINS), and sign-extend the result. We + check for this extension using SLL. */ + +struct s +{ + int a:3; + int b:29; +}; + +NOMIPS16 void +f (int a) +{ + struct s s; + asm volatile ("" : "=r"(s)); + s.a = a; + asm volatile ("" :: "r"(s)); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c new file mode 100644 index 000000000..77a554d21 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c @@ -0,0 +1,38 @@ +/* { dg-options "(-mips16) -mgp64 -EL" } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c new file mode 100644 index 000000000..930c36f9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c @@ -0,0 +1,38 @@ +/* { dg-options "(-mips16) -mgp64 -EB" } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp new file mode 100644 index 000000000..cfa64b192 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp @@ -0,0 +1,72 @@ +# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Run compatibility tests in which the "alt" compiler tries to force +# MIPS16 mode. + +# We can only guarantee MIPS16 runtime support for certain targets. +if { ![istarget mipsisa*-*-elf*] && ![istarget mips64vr*-*-elf*] } { + return +} + +load_lib gcc-dg.exp + +# Check whether the flags are compatible with MIPS16 code generation. +if { ![check_effective_target_mips16_attribute] } { + return +} + +# Save the old value of CFLAGS_FOR_TARGET, if any. +global saved_CFLAGS_FOR_TARGET +if { [info exists CFLAGS_FOR_TARGET] } { + set saved_CFLAGS_FOR_TARGET $CFLAGS_FOR_TARGET +} else { + unset -nocomplain saved_CFLAGS_FOR_TARGET +} + +# The "alt" compiler is the normal compiler with an extra "-mips16" argument. +proc compat-use-alt-compiler { } { + global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET + + if { [info exists saved_CFLAGS_FOR_TARGET] } { + set CFLAGS_FOR_TARGET [concat $saved_CFLAGS_FOR_TARGET "-mips16"] + } else { + set CFLAGS_FOR_TARGET "-mips16" + } +} + +# Make the compiler under test the default. +proc compat-use-tst-compiler { } { + global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET + + if { [info exists saved_CFLAGS_FOR_TARGET] } { + set CFLAGS_FOR_TARGET $saved_CFLAGS_FOR_TARGET + } else { + unset -nocomplain CFLAGS_FOR_TARGET + } +} + +load_lib compat.exp + +gcc_init +foreach src [lsort [find $srcdir/$subdir mips16_*_main.c]] { + if { [runtest_file_p $runtests $src] } { + compat-execute $src "mips16_inter" 1 + } +} +compat-use-tst-compiler diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c new file mode 100644 index 000000000..df18c7670 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c @@ -0,0 +1,10 @@ +extern void init (void); +extern void test (void); + +int +main (void) +{ + init (); + test (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c new file mode 100644 index 000000000..38339cad8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c @@ -0,0 +1,176 @@ +#include <stdlib.h> + +/* All the function pointers are declared and initialized in + mips16-stubs-2.c. */ + +extern double the_result; + +extern void v0 (void); +extern void v1 (float); +extern void v5 (float, float); +extern void v9 (float, double); +extern void v2 (double); +extern void v6 (double, float); +extern void v10 (double, double); + +extern float f0 (void); +extern float f1 (float); +extern float f5 (float, float); +extern float f9 (float, double); +extern float f2 (double); +extern float f6 (double, float); +extern float f10 (double, double); + +extern double d0 (void); +extern double d1 (float); +extern double d5 (float, float); +extern double d9 (float, double); +extern double d2 (double); +extern double d6 (double, float); +extern double d10 (double, double); + +extern _Complex float cf0 (void); +extern _Complex float cf1 (float); +extern _Complex float cf5 (float, float); +extern _Complex float cf9 (float, double); +extern _Complex float cf2 (double); +extern _Complex float cf6 (double, float); +extern _Complex float cf10 (double, double); + +extern _Complex double cd0 (void); +extern _Complex double cd1 (float); +extern _Complex double cd5 (float, float); +extern _Complex double cd9 (float, double); +extern _Complex double cd2 (double); +extern _Complex double cd6 (double, float); +extern _Complex double cd10 (double, double); + +extern void (*pv0) (void); +extern void (*pv1) (float); +extern void (*pv5) (float, float); +extern void (*pv9) (float, double); +extern void (*pv2) (double); +extern void (*pv6) (double, float); +extern void (*pv10) (double, double); + +extern float (*pf0) (void); +extern float (*pf1) (float); +extern float (*pf5) (float, float); +extern float (*pf9) (float, double); +extern float (*pf2) (double); +extern float (*pf6) (double, float); +extern float (*pf10) (double, double); + +extern double (*pd0) (void); +extern double (*pd1) (float); +extern double (*pd5) (float, float); +extern double (*pd9) (float, double); +extern double (*pd2) (double); +extern double (*pd6) (double, float); +extern double (*pd10) (double, double); + +extern _Complex float (*pcf0) (void); +extern _Complex float (*pcf1) (float); +extern _Complex float (*pcf5) (float, float); +extern _Complex float (*pcf9) (float, double); +extern _Complex float (*pcf2) (double); +extern _Complex float (*pcf6) (double, float); +extern _Complex float (*pcf10) (double, double); + +extern _Complex double (*pcd0) (void); +extern _Complex double (*pcd1) (float); +extern _Complex double (*pcd5) (float, float); +extern _Complex double (*pcd9) (float, double); +extern _Complex double (*pcd2) (double); +extern _Complex double (*pcd6) (double, float); +extern _Complex double (*pcd10) (double, double); + +/* Macros for results checking. */ +#define CHECK_RESULT(x, y) if ((x) != (y)) abort () +#define CHECK_VOID_RESULT(x, y) CHECK_RESULT (((x), the_result), y) + +/* Call functions through pointers and check against expected results. */ +void +test (void) +{ + + CHECK_VOID_RESULT (v0 (), 1.0); + CHECK_VOID_RESULT (v1 (1.0), 2.0); + CHECK_VOID_RESULT (v5 (5.0, 6.0), 12.0); + CHECK_VOID_RESULT (v9 (9.0, 10.0), 20.0); + CHECK_VOID_RESULT (v2 (2.0), 3.0); + CHECK_VOID_RESULT (v6 (6.0, 7.0), 14.0); + CHECK_VOID_RESULT (v10 (10.0, 11.0), 22.0); + + CHECK_RESULT (f0 (), 1.0); + CHECK_RESULT (f1 (1.0), 2.0); + CHECK_RESULT (f5 (5.0, 6.0), 12.0); + CHECK_RESULT (f9 (9.0, 10.0), 20.0); + CHECK_RESULT (f2 (2.0), 3.0); + CHECK_RESULT (f6 (6.0, 7.0), 14.0); + CHECK_RESULT (f10 (10.0, 11.0), 22.0); + + CHECK_RESULT (d0 (), 1.0); + CHECK_RESULT (d1 (1.0), 2.0); + CHECK_RESULT (d5 (5.0, 6.0), 12.0); + CHECK_RESULT (d9 (9.0, 10.0), 20.0); + CHECK_RESULT (d2 (2.0), 3.0); + CHECK_RESULT (d6 (6.0, 7.0), 14.0); + CHECK_RESULT (d10 (10.0, 11.0), 22.0); + + CHECK_RESULT (cf0 (), 1.0 + 0.0i); + CHECK_RESULT (cf1 (1.0), 2.0 + 1.0i); + CHECK_RESULT (cf5 (5.0, 6.0), 12.0 + 5.0i); + CHECK_RESULT (cf9 (9.0, 10.0), 20.0 + 9.0i); + CHECK_RESULT (cf2 (2.0), 3.0 + 2.0i); + CHECK_RESULT (cf6 (6.0, 7.0), 14.0 + 6.0i); + CHECK_RESULT (cf10 (10.0, 11.0), 22.0 + 10.0i); + + CHECK_RESULT (cd0 (), 1.0 + 0.0i); + CHECK_RESULT (cd1 (1.0), 2.0 + 1.0i); + CHECK_RESULT (cd5 (5.0, 6.0), 12.0 + 5.0i); + CHECK_RESULT (cd9 (9.0, 10.0), 20.0 + 9.0i); + CHECK_RESULT (cd2 (2.0), 3.0 + 2.0i); + CHECK_RESULT (cd6 (6.0, 7.0), 14.0 + 6.0i); + CHECK_RESULT (cd10 (10.0, 11.0), 22.0 + 10.0i); + + CHECK_VOID_RESULT ((*pv0) (), 1.0); + CHECK_VOID_RESULT ((*pv1) (1.0), 2.0); + CHECK_VOID_RESULT ((*pv5) (5.0, 6.0), 12.0); + CHECK_VOID_RESULT ((*pv9) (9.0, 10.0), 20.0); + CHECK_VOID_RESULT ((*pv2) (2.0), 3.0); + CHECK_VOID_RESULT ((*pv6) (6.0, 7.0), 14.0); + CHECK_VOID_RESULT ((*pv10) (10.0, 11.0), 22.0); + + CHECK_RESULT ((*pf0) (), 1.0); + CHECK_RESULT ((*pf1) (1.0), 2.0); + CHECK_RESULT ((*pf5) (5.0, 6.0), 12.0); + CHECK_RESULT ((*pf9) (9.0, 10.0), 20.0); + CHECK_RESULT ((*pf2) (2.0), 3.0); + CHECK_RESULT ((*pf6) (6.0, 7.0), 14.0); + CHECK_RESULT ((*pf10) (10.0, 11.0), 22.0); + + CHECK_RESULT ((*pd0) (), 1.0); + CHECK_RESULT ((*pd1) (1.0), 2.0); + CHECK_RESULT ((*pd5) (5.0, 6.0), 12.0); + CHECK_RESULT ((*pd9) (9.0, 10.0), 20.0); + CHECK_RESULT ((*pd2) (2.0), 3.0); + CHECK_RESULT ((*pd6) (6.0, 7.0), 14.0); + CHECK_RESULT ((*pd10) (10.0, 11.0), 22.0); + + CHECK_RESULT ((*pcf0) (), 1.0 + 0.0i); + CHECK_RESULT ((*pcf1) (1.0), 2.0 + 1.0i); + CHECK_RESULT ((*pcf5) (5.0, 6.0), 12.0 + 5.0i); + CHECK_RESULT ((*pcf9) (9.0, 10.0), 20.0 + 9.0i); + CHECK_RESULT ((*pcf2) (2.0), 3.0 + 2.0i); + CHECK_RESULT ((*pcf6) (6.0, 7.0), 14.0 + 6.0i); + CHECK_RESULT ((*pcf10) (10.0, 11.0), 22.0 + 10.0i); + + CHECK_RESULT ((*pcd0) (), 1.0 + 0.0i); + CHECK_RESULT ((*pcd1) (1.0), 2.0 + 1.0i); + CHECK_RESULT ((*pcd5) (5.0, 6.0), 12.0 + 5.0i); + CHECK_RESULT ((*pcd9) (9.0, 10.0), 20.0 + 9.0i); + CHECK_RESULT ((*pcd2) (2.0), 3.0 + 2.0i); + CHECK_RESULT ((*pcd6) (6.0, 7.0), 14.0 + 6.0i); + CHECK_RESULT ((*pcd10) (10.0, 11.0), 22.0 + 10.0i); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c new file mode 100644 index 000000000..b7a4d7f32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c @@ -0,0 +1,133 @@ +/* All test functions return the sum of arguments, plus 1. + Void-returning functions put the result in the_result. + Complex-returning functions return their signature number as the + (constant) imaginary part of the result. */ + +double the_result; + +void v0 (void) { the_result = 1.0; } +void v1 (float x) { the_result = 1.0 + x; } +void v5 (float x, float y) { the_result = 1.0 + x + y; } +void v9 (float x, double y) { the_result = 1.0 + x + y; } +void v2 (double x) { the_result = 1.0 + x; } +void v6 (double x, float y) { the_result = 1.0 + x + y; } +void v10 (double x, double y) { the_result = 1.0 + x + y; } + +float f0 (void) { return 1.0; } +float f1 (float x) { return 1.0 + x; } +float f5 (float x, float y) { return 1.0 + x + y; } +float f9 (float x, double y) { return 1.0 + x + y; } +float f2 (double x) { return 1.0 + x; } +float f6 (double x, float y) { return 1.0 + x + y; } +float f10 (double x, double y) { return 1.0 + x + y; } + +double d0 (void) { return 1.0; } +double d1 (float x) { return 1.0 + x; } +double d5 (float x, float y) { return 1.0 + x + y; } +double d9 (float x, double y) { return 1.0 + x + y; } +double d2 (double x) { return 1.0 + x; } +double d6 (double x, float y) { return 1.0 + x + y; } +double d10 (double x, double y) { return 1.0 + x + y; } + +_Complex float cf0 (void) { return 1.0 + 0.0i; } +_Complex float cf1 (float x) { return 1.0 + x + 1.0i; } +_Complex float cf5 (float x, float y) { return 1.0 + x + y + 5.0i; } +_Complex float cf9 (float x, double y) { return 1.0 + x + y + 9.0i; } +_Complex float cf2 (double x) { return 1.0 + x + 2.0i; } +_Complex float cf6 (double x, float y) { return 1.0 + x + y + 6.0i; } +_Complex float cf10 (double x, double y) { return 1.0 + x + y + 10.0i; } + +_Complex double cd0 (void) { return 1.0 + 0.0i; } +_Complex double cd1 (float x) { return 1.0 + x + 1.0i; } +_Complex double cd5 (float x, float y) { return 1.0 + x + y + 5.0i; } +_Complex double cd9 (float x, double y) { return 1.0 + x + y + 9.0i; } +_Complex double cd2 (double x) { return 1.0 + x + 2.0i; } +_Complex double cd6 (double x, float y) { return 1.0 + x + y + 6.0i; } +_Complex double cd10 (double x, double y) { return 1.0 + x + y + 10.0i; } + + +/* Declare and initialize all the pointer-to-function variables. */ + +void (*pv0) (void); +void (*pv1) (float); +void (*pv5) (float, float); +void (*pv9) (float, double); +void (*pv2) (double); +void (*pv6) (double, float); +void (*pv10) (double, double); + +float (*pf0) (void); +float (*pf1) (float); +float (*pf5) (float, float); +float (*pf9) (float, double); +float (*pf2) (double); +float (*pf6) (double, float); +float (*pf10) (double, double); + +double (*pd0) (void); +double (*pd1) (float); +double (*pd5) (float, float); +double (*pd9) (float, double); +double (*pd2) (double); +double (*pd6) (double, float); +double (*pd10) (double, double); + +_Complex float (*pcf0) (void); +_Complex float (*pcf1) (float); +_Complex float (*pcf5) (float, float); +_Complex float (*pcf9) (float, double); +_Complex float (*pcf2) (double); +_Complex float (*pcf6) (double, float); +_Complex float (*pcf10) (double, double); + +_Complex double (*pcd0) (void); +_Complex double (*pcd1) (float); +_Complex double (*pcd5) (float, float); +_Complex double (*pcd9) (float, double); +_Complex double (*pcd2) (double); +_Complex double (*pcd6) (double, float); +_Complex double (*pcd10) (double, double); + +void +init (void) +{ + pv0 = v0; + pv1 = v1; + pv5 = v5; + pv9 = v9; + pv2 = v2; + pv6 = v6; + pv10 = v10; + + pf0 = f0; + pf1 = f1; + pf5 = f5; + pf9 = f9; + pf2 = f2; + pf6 = f6; + pf10 = f10; + + pd0 = d0; + pd1 = d1; + pd5 = d5; + pd9 = d9; + pd2 = d2; + pd6 = d6; + pd10 = d10; + + pcf0 = cf0; + pcf1 = cf1; + pcf5 = cf5; + pcf9 = cf9; + pcf2 = cf2; + pcf6 = cf6; + pcf10 = cf10; + + pcd0 = cd0; + pcd1 = cd1; + pcd5 = cd5; + pcd9 = cd9; + pcd2 = cd2; + pcd6 = cd6; + pcd10 = cd10; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c new file mode 100644 index 000000000..9ab32bf5a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c @@ -0,0 +1,15 @@ +/* Make sure that we emit .cfa_restore notes for LO and HI. */ +/* { dg-options "-mips32r2 -msoft-float -g" } */ +/* { dg-skip-if "forbidding a frame pointer makes this a code quallity test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */ + +extern void f (void); + +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) +v1 (void) +{ + f (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c new file mode 100644 index 000000000..298e04677 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c @@ -0,0 +1,34 @@ +/* Make sure that we emit .cfa_restore notes for LO, HI and GPRs. */ +/* { dg-options "-mips32r2 -msoft-float -g" } */ +/* { dg-skip-if "forbidding a frame pointer makes this a code quallity test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 1\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 2\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 3\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 4\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 5\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 6\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 7\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 8\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 9\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 10\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 11\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 12\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 13\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 14\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 15\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 24\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 25\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 31\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */ +/* { dg-final { scan-assembler "\t\\\.cfi_def_cfa_offset 0\n" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */ +/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */ + +extern void f (void); + +NOMIPS16 void __attribute__ ((interrupt)) +v1 (void) +{ + f (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c new file mode 100644 index 000000000..073c772ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c @@ -0,0 +1,23 @@ +/* Test attributes for interrupt handlers */ +/* { dg-do assemble } */ +/* { dg-options "-mips32r2 -msoft-float" } */ + +void f () { } + +NOMIPS16 void __attribute__ ((interrupt)) v0 () { } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) v1 () { } +NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked)) v2 () { } +NOMIPS16 void __attribute__ ((interrupt, use_debug_exception_return)) v3 () { } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked)) v4 () { } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, use_debug_exception_return)) v5 () { } +NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked, use_debug_exception_return)) v6 () { } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked, use_debug_exception_return)) v7 () { } + +NOMIPS16 void __attribute__ ((interrupt)) w0 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) w1 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked)) w2 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, use_debug_exception_return)) w3 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked)) w4 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, use_debug_exception_return)) w5 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked, use_debug_exception_return)) w6 () { t(); } +NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked, use_debug_exception_return)) w7 () { t(); } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c new file mode 100644 index 000000000..a30594840 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mshared -mexplicit-relocs -fno-delayed-branch -fno-unroll-loops" } */ +/* We can load into something other than $25 when not optimizing, + then immediately move into $25. */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void bar (void); + +NOMIPS16 void +foo (int n) +{ + while (n--) + { + bar (); + bar (); + } +} + +/* There should be exactly five uses of $25: one to set up $gp, two to + load the address of bar (), and two to call it. */ +/* { dg-final { scan-assembler-times "\tl.\t\\\$25,%call16\\\(bar\\\)" 2 } } */ +/* { dg-final { scan-assembler-times "\tjalrs?\t\\\$25" 2 } } */ +/* { dg-final { scan-assembler "(\\\$28,|\t.cpload\t)\\\$25" } } */ +/* { dg-final { scan-assembler-times "\\\$25" 5 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c new file mode 100644 index 000000000..5ccfe5149 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=32 -pg -mno-abicalls -mlong-calls" } */ +/* { dg-final { scan-assembler-not "\tjal\t_mcount" } } */ +NOMIPS16 void +foo (void) +{ +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c new file mode 100644 index 000000000..2efc3ef3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c @@ -0,0 +1,16 @@ +/* { dg-options "isa=loongson" } */ + +typedef int st; +typedef unsigned int ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tmultu.g\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tdivu.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tmodu.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tdiv.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tmod.g\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c new file mode 100644 index 000000000..07523aa4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c @@ -0,0 +1,16 @@ +/* { dg-options "isa=loongson -mgp64" } */ + +typedef long long st; +typedef unsigned long long ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tdmultu.g\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tddivu.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tdmodu.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tddiv.g\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tdmod.g\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c new file mode 100644 index 000000000..778d73981 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c @@ -0,0 +1,37 @@ +/* Test case for SHIFT_COUNT_TRUNCATED on Loongson. */ + +/* { dg-do run } */ +/* loongson.h does not handle or check for MIPS16ness. There doesn't + seem any good reason for it to, given that the Loongson processors + do not support MIPS16. */ +/* { dg-options "isa=loongson -mhard-float -mno-mips16" } */ +/* See PR 52155. */ +/* { dg-options "isa=loongson -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */ + +#include "loongson.h" +#include <assert.h> + +typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; + +void +main1 (int shift) +{ + int32x2_encap_t s; + int32x2_encap_t r; + + s.a[0] = 0xffffffff; + s.a[1] = 0xffffffff; + /* Loongson SIMD use low-order 7 bits to specify the shift amount. + Thus V2SI << 0x40 == 0. The below expression 'shift & 0x3f' will be + mis-optimized as 'shift', if SHIFT_COUNT_TRUNCATED is nonzero. */ + r.v = psllw_s (s.v, (shift & 0x3f)); + assert (r.a[0] == 0xffffffff); + assert (r.a[1] == 0xffffffff); +} + +int +main (void) +{ + main1 (0x40); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c new file mode 100644 index 000000000..ae3565f47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c @@ -0,0 +1,1966 @@ +/* Test cases for ST Microelectronics Loongson-2E/2F SIMD intrinsics. + Copyright (C) 2008 Free Software Foundation, Inc. + Contributed by CodeSourcery. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* { dg-do run } */ +/* loongson.h does not handle or check for MIPS16ness. There doesn't + seem any good reason for it to, given that the Loongson processors + do not support MIPS16. */ +/* { dg-options "isa=loongson -mhard-float -mno-mips16 -flax-vector-conversions" } */ + +#include "loongson.h" +#include <stdio.h> +#include <stdint.h> +#include <assert.h> +#include <limits.h> + +typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; +typedef union { int16x4_t v; int16_t a[4]; } int16x4_encap_t; +typedef union { int8x8_t v; int8_t a[8]; } int8x8_encap_t; +typedef union { uint32x2_t v; uint32_t a[2]; } uint32x2_encap_t; +typedef union { uint16x4_t v; uint16_t a[4]; } uint16x4_encap_t; +typedef union { uint8x8_t v; uint8_t a[8]; } uint8x8_encap_t; + +#define UINT16x4_MAX USHRT_MAX +#define UINT8x8_MAX UCHAR_MAX +#define INT8x8_MAX SCHAR_MAX +#define INT16x4_MAX SHRT_MAX +#define INT32x2_MAX INT_MAX + +static void test_packsswh (void) +{ + int32x2_encap_t s, t; + int16x4_encap_t r; + s.a[0] = INT16x4_MAX - 2; + s.a[1] = INT16x4_MAX - 1; + t.a[0] = INT16x4_MAX; + t.a[1] = INT16x4_MAX + 1; + r.v = packsswh (s.v, t.v); + assert (r.a[0] == INT16x4_MAX - 2); + assert (r.a[1] == INT16x4_MAX - 1); + assert (r.a[2] == INT16x4_MAX); + assert (r.a[3] == INT16x4_MAX); +} + +static void test_packsshb (void) +{ + int16x4_encap_t s, t; + int8x8_encap_t r; + s.a[0] = INT8x8_MAX - 6; + s.a[1] = INT8x8_MAX - 5; + s.a[2] = INT8x8_MAX - 4; + s.a[3] = INT8x8_MAX - 3; + t.a[0] = INT8x8_MAX - 2; + t.a[1] = INT8x8_MAX - 1; + t.a[2] = INT8x8_MAX; + t.a[3] = INT8x8_MAX + 1; + r.v = packsshb (s.v, t.v); + assert (r.a[0] == INT8x8_MAX - 6); + assert (r.a[1] == INT8x8_MAX - 5); + assert (r.a[2] == INT8x8_MAX - 4); + assert (r.a[3] == INT8x8_MAX - 3); + assert (r.a[4] == INT8x8_MAX - 2); + assert (r.a[5] == INT8x8_MAX - 1); + assert (r.a[6] == INT8x8_MAX); + assert (r.a[7] == INT8x8_MAX); +} + +static void test_packushb (void) +{ + uint16x4_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = UINT8x8_MAX - 6; + s.a[1] = UINT8x8_MAX - 5; + s.a[2] = UINT8x8_MAX - 4; + s.a[3] = UINT8x8_MAX - 3; + t.a[0] = UINT8x8_MAX - 2; + t.a[1] = UINT8x8_MAX - 1; + t.a[2] = UINT8x8_MAX; + t.a[3] = UINT8x8_MAX + 1; + r.v = packushb (s.v, t.v); + assert (r.a[0] == UINT8x8_MAX - 6); + assert (r.a[1] == UINT8x8_MAX - 5); + assert (r.a[2] == UINT8x8_MAX - 4); + assert (r.a[3] == UINT8x8_MAX - 3); + assert (r.a[4] == UINT8x8_MAX - 2); + assert (r.a[5] == UINT8x8_MAX - 1); + assert (r.a[6] == UINT8x8_MAX); + assert (r.a[7] == UINT8x8_MAX); +} + +static void test_paddw_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + t.a[0] = 3; + t.a[1] = 4; + r.v = paddw_u (s.v, t.v); + assert (r.a[0] == 4); + assert (r.a[1] == 6); +} + +static void test_paddw_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = -2; + s.a[1] = -1; + t.a[0] = 3; + t.a[1] = 4; + r.v = paddw_s (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == 3); +} + +static void test_paddh_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + s.a[2] = 3; + s.a[3] = 4; + t.a[0] = 5; + t.a[1] = 6; + t.a[2] = 7; + t.a[3] = 8; + r.v = paddh_u (s.v, t.v); + assert (r.a[0] == 6); + assert (r.a[1] == 8); + assert (r.a[2] == 10); + assert (r.a[3] == 12); +} + +static void test_paddh_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -10; + s.a[1] = -20; + s.a[2] = -30; + s.a[3] = -40; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + r.v = paddh_s (s.v, t.v); + assert (r.a[0] == -9); + assert (r.a[1] == -18); + assert (r.a[2] == -27); + assert (r.a[3] == -36); +} + +static void test_paddb_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + s.a[2] = 3; + s.a[3] = 4; + s.a[4] = 5; + s.a[5] = 6; + s.a[6] = 7; + s.a[7] = 8; + t.a[0] = 9; + t.a[1] = 10; + t.a[2] = 11; + t.a[3] = 12; + t.a[4] = 13; + t.a[5] = 14; + t.a[6] = 15; + t.a[7] = 16; + r.v = paddb_u (s.v, t.v); + assert (r.a[0] == 10); + assert (r.a[1] == 12); + assert (r.a[2] == 14); + assert (r.a[3] == 16); + assert (r.a[4] == 18); + assert (r.a[5] == 20); + assert (r.a[6] == 22); + assert (r.a[7] == 24); +} + +static void test_paddb_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -10; + s.a[1] = -20; + s.a[2] = -30; + s.a[3] = -40; + s.a[4] = -50; + s.a[5] = -60; + s.a[6] = -70; + s.a[7] = -80; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + t.a[4] = 5; + t.a[5] = 6; + t.a[6] = 7; + t.a[7] = 8; + r.v = paddb_s (s.v, t.v); + assert (r.a[0] == -9); + assert (r.a[1] == -18); + assert (r.a[2] == -27); + assert (r.a[3] == -36); + assert (r.a[4] == -45); + assert (r.a[5] == -54); + assert (r.a[6] == -63); + assert (r.a[7] == -72); +} + +static void test_paddd_u (void) +{ + uint64_t d = 123456; + uint64_t e = 789012; + uint64_t r; + r = paddd_u (d, e); + assert (r == 912468); +} + +static void test_paddd_s (void) +{ + int64_t d = 123456; + int64_t e = -789012; + int64_t r; + r = paddd_s (d, e); + assert (r == -665556); +} + +static void test_paddsh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = 0; + s.a[2] = 1; + s.a[3] = 2; + t.a[0] = INT16x4_MAX; + t.a[1] = INT16x4_MAX; + t.a[2] = INT16x4_MAX; + t.a[3] = INT16x4_MAX; + r.v = paddsh (s.v, t.v); + assert (r.a[0] == INT16x4_MAX - 1); + assert (r.a[1] == INT16x4_MAX); + assert (r.a[2] == INT16x4_MAX); + assert (r.a[3] == INT16x4_MAX); +} + +static void test_paddsb (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -6; + s.a[1] = -5; + s.a[2] = -4; + s.a[3] = -3; + s.a[4] = -2; + s.a[5] = -1; + s.a[6] = 0; + s.a[7] = 1; + t.a[0] = INT8x8_MAX; + t.a[1] = INT8x8_MAX; + t.a[2] = INT8x8_MAX; + t.a[3] = INT8x8_MAX; + t.a[4] = INT8x8_MAX; + t.a[5] = INT8x8_MAX; + t.a[6] = INT8x8_MAX; + t.a[7] = INT8x8_MAX; + r.v = paddsb (s.v, t.v); + assert (r.a[0] == INT8x8_MAX - 6); + assert (r.a[1] == INT8x8_MAX - 5); + assert (r.a[2] == INT8x8_MAX - 4); + assert (r.a[3] == INT8x8_MAX - 3); + assert (r.a[4] == INT8x8_MAX - 2); + assert (r.a[5] == INT8x8_MAX - 1); + assert (r.a[6] == INT8x8_MAX); + assert (r.a[7] == INT8x8_MAX); +} + +static void test_paddush (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 0; + s.a[1] = 1; + s.a[2] = 0; + s.a[3] = 1; + t.a[0] = UINT16x4_MAX; + t.a[1] = UINT16x4_MAX; + t.a[2] = UINT16x4_MAX; + t.a[3] = UINT16x4_MAX; + r.v = paddush (s.v, t.v); + assert (r.a[0] == UINT16x4_MAX); + assert (r.a[1] == UINT16x4_MAX); + assert (r.a[2] == UINT16x4_MAX); + assert (r.a[3] == UINT16x4_MAX); +} + +static void test_paddusb (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 0; + s.a[1] = 1; + s.a[2] = 0; + s.a[3] = 1; + s.a[4] = 0; + s.a[5] = 1; + s.a[6] = 0; + s.a[7] = 1; + t.a[0] = UINT8x8_MAX; + t.a[1] = UINT8x8_MAX; + t.a[2] = UINT8x8_MAX; + t.a[3] = UINT8x8_MAX; + t.a[4] = UINT8x8_MAX; + t.a[5] = UINT8x8_MAX; + t.a[6] = UINT8x8_MAX; + t.a[7] = UINT8x8_MAX; + r.v = paddusb (s.v, t.v); + assert (r.a[0] == UINT8x8_MAX); + assert (r.a[1] == UINT8x8_MAX); + assert (r.a[2] == UINT8x8_MAX); + assert (r.a[3] == UINT8x8_MAX); + assert (r.a[4] == UINT8x8_MAX); + assert (r.a[5] == UINT8x8_MAX); + assert (r.a[6] == UINT8x8_MAX); + assert (r.a[7] == UINT8x8_MAX); +} + +static void test_pandn_ud (void) +{ + uint64_t d1 = 0x0000ffff0000ffffull; + uint64_t d2 = 0x0000ffff0000ffffull; + uint64_t r; + r = pandn_ud (d1, d2); + assert (r == 0); +} + +static void test_pandn_sd (void) +{ + int64_t d1 = (int64_t) 0x0000000000000000ull; + int64_t d2 = (int64_t) 0xfffffffffffffffeull; + int64_t r; + r = pandn_sd (d1, d2); + assert (r == -2); +} + +static void test_pandn_uw (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 0xffffffff; + s.a[1] = 0x00000000; + t.a[0] = 0x00000000; + t.a[1] = 0xffffffff; + r.v = pandn_uw (s.v, t.v); + assert (r.a[0] == 0x00000000); + assert (r.a[1] == 0xffffffff); +} + +static void test_pandn_sw (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = 0xffffffff; + s.a[1] = 0x00000000; + t.a[0] = 0xffffffff; + t.a[1] = 0xfffffffe; + r.v = pandn_sw (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -2); +} + +static void test_pandn_uh (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 0xffff; + s.a[1] = 0x0000; + s.a[2] = 0xffff; + s.a[3] = 0x0000; + t.a[0] = 0x0000; + t.a[1] = 0xffff; + t.a[2] = 0x0000; + t.a[3] = 0xffff; + r.v = pandn_uh (s.v, t.v); + assert (r.a[0] == 0x0000); + assert (r.a[1] == 0xffff); + assert (r.a[2] == 0x0000); + assert (r.a[3] == 0xffff); +} + +static void test_pandn_sh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = 0xffff; + s.a[1] = 0x0000; + s.a[2] = 0xffff; + s.a[3] = 0x0000; + t.a[0] = 0xffff; + t.a[1] = 0xfffe; + t.a[2] = 0xffff; + t.a[3] = 0xfffe; + r.v = pandn_sh (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -2); + assert (r.a[2] == 0); + assert (r.a[3] == -2); +} + +static void test_pandn_ub (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 0xff; + s.a[1] = 0x00; + s.a[2] = 0xff; + s.a[3] = 0x00; + s.a[4] = 0xff; + s.a[5] = 0x00; + s.a[6] = 0xff; + s.a[7] = 0x00; + t.a[0] = 0x00; + t.a[1] = 0xff; + t.a[2] = 0x00; + t.a[3] = 0xff; + t.a[4] = 0x00; + t.a[5] = 0xff; + t.a[6] = 0x00; + t.a[7] = 0xff; + r.v = pandn_ub (s.v, t.v); + assert (r.a[0] == 0x00); + assert (r.a[1] == 0xff); + assert (r.a[2] == 0x00); + assert (r.a[3] == 0xff); + assert (r.a[4] == 0x00); + assert (r.a[5] == 0xff); + assert (r.a[6] == 0x00); + assert (r.a[7] == 0xff); +} + +static void test_pandn_sb (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = 0xff; + s.a[1] = 0x00; + s.a[2] = 0xff; + s.a[3] = 0x00; + s.a[4] = 0xff; + s.a[5] = 0x00; + s.a[6] = 0xff; + s.a[7] = 0x00; + t.a[0] = 0xff; + t.a[1] = 0xfe; + t.a[2] = 0xff; + t.a[3] = 0xfe; + t.a[4] = 0xff; + t.a[5] = 0xfe; + t.a[6] = 0xff; + t.a[7] = 0xfe; + r.v = pandn_sb (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -2); + assert (r.a[2] == 0); + assert (r.a[3] == -2); + assert (r.a[4] == 0); + assert (r.a[5] == -2); + assert (r.a[6] == 0); + assert (r.a[7] == -2); +} + +static void test_pavgh (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + s.a[2] = 3; + s.a[3] = 4; + t.a[0] = 5; + t.a[1] = 6; + t.a[2] = 7; + t.a[3] = 8; + r.v = pavgh (s.v, t.v); + assert (r.a[0] == 3); + assert (r.a[1] == 4); + assert (r.a[2] == 5); + assert (r.a[3] == 6); +} + +static void test_pavgb (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + s.a[2] = 3; + s.a[3] = 4; + s.a[4] = 1; + s.a[5] = 2; + s.a[6] = 3; + s.a[7] = 4; + t.a[0] = 5; + t.a[1] = 6; + t.a[2] = 7; + t.a[3] = 8; + t.a[4] = 5; + t.a[5] = 6; + t.a[6] = 7; + t.a[7] = 8; + r.v = pavgb (s.v, t.v); + assert (r.a[0] == 3); + assert (r.a[1] == 4); + assert (r.a[2] == 5); + assert (r.a[3] == 6); + assert (r.a[4] == 3); + assert (r.a[5] == 4); + assert (r.a[6] == 5); + assert (r.a[7] == 6); +} + +static void test_pcmpeqw_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 42; + s.a[1] = 43; + t.a[0] = 43; + t.a[1] = 43; + r.v = pcmpeqw_u (s.v, t.v); + assert (r.a[0] == 0x00000000); + assert (r.a[1] == 0xffffffff); +} + +static void test_pcmpeqh_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 42; + s.a[1] = 43; + s.a[2] = 42; + s.a[3] = 43; + t.a[0] = 43; + t.a[1] = 43; + t.a[2] = 43; + t.a[3] = 43; + r.v = pcmpeqh_u (s.v, t.v); + assert (r.a[0] == 0x0000); + assert (r.a[1] == 0xffff); + assert (r.a[2] == 0x0000); + assert (r.a[3] == 0xffff); +} + +static void test_pcmpeqb_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 42; + s.a[1] = 43; + s.a[2] = 42; + s.a[3] = 43; + s.a[4] = 42; + s.a[5] = 43; + s.a[6] = 42; + s.a[7] = 43; + t.a[0] = 43; + t.a[1] = 43; + t.a[2] = 43; + t.a[3] = 43; + t.a[4] = 43; + t.a[5] = 43; + t.a[6] = 43; + t.a[7] = 43; + r.v = pcmpeqb_u (s.v, t.v); + assert (r.a[0] == 0x00); + assert (r.a[1] == 0xff); + assert (r.a[2] == 0x00); + assert (r.a[3] == 0xff); + assert (r.a[4] == 0x00); + assert (r.a[5] == 0xff); + assert (r.a[6] == 0x00); + assert (r.a[7] == 0xff); +} + +static void test_pcmpeqw_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = -42; + s.a[1] = -42; + t.a[0] = 42; + t.a[1] = -42; + r.v = pcmpeqw_s (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -1); +} + +static void test_pcmpeqh_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -42; + s.a[1] = -42; + s.a[2] = -42; + s.a[3] = -42; + t.a[0] = 42; + t.a[1] = -42; + t.a[2] = 42; + t.a[3] = -42; + r.v = pcmpeqh_s (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -1); + assert (r.a[2] == 0); + assert (r.a[3] == -1); +} + +static void test_pcmpeqb_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -42; + s.a[1] = -42; + s.a[2] = -42; + s.a[3] = -42; + s.a[4] = -42; + s.a[5] = -42; + s.a[6] = -42; + s.a[7] = -42; + t.a[0] = 42; + t.a[1] = -42; + t.a[2] = 42; + t.a[3] = -42; + t.a[4] = 42; + t.a[5] = -42; + t.a[6] = 42; + t.a[7] = -42; + r.v = pcmpeqb_s (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == -1); + assert (r.a[2] == 0); + assert (r.a[3] == -1); + assert (r.a[4] == 0); + assert (r.a[5] == -1); + assert (r.a[6] == 0); + assert (r.a[7] == -1); +} + +static void test_pcmpgtw_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 42; + s.a[1] = 43; + t.a[0] = 43; + t.a[1] = 42; + r.v = pcmpgtw_u (s.v, t.v); + assert (r.a[0] == 0x00000000); + assert (r.a[1] == 0xffffffff); +} + +static void test_pcmpgth_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 40; + s.a[1] = 41; + s.a[2] = 42; + s.a[3] = 43; + t.a[0] = 40; + t.a[1] = 41; + t.a[2] = 43; + t.a[3] = 42; + r.v = pcmpgth_u (s.v, t.v); + assert (r.a[0] == 0x0000); + assert (r.a[1] == 0x0000); + assert (r.a[2] == 0x0000); + assert (r.a[3] == 0xffff); +} + +static void test_pcmpgtb_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 40; + s.a[1] = 41; + s.a[2] = 42; + s.a[3] = 43; + s.a[4] = 44; + s.a[5] = 45; + s.a[6] = 46; + s.a[7] = 47; + t.a[0] = 48; + t.a[1] = 47; + t.a[2] = 46; + t.a[3] = 45; + t.a[4] = 44; + t.a[5] = 43; + t.a[6] = 42; + t.a[7] = 41; + r.v = pcmpgtb_u (s.v, t.v); + assert (r.a[0] == 0x00); + assert (r.a[1] == 0x00); + assert (r.a[2] == 0x00); + assert (r.a[3] == 0x00); + assert (r.a[4] == 0x00); + assert (r.a[5] == 0xff); + assert (r.a[6] == 0xff); + assert (r.a[7] == 0xff); +} + +static void test_pcmpgtw_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = 42; + s.a[1] = -42; + t.a[0] = -42; + t.a[1] = -42; + r.v = pcmpgtw_s (s.v, t.v); + assert (r.a[0] == -1); + assert (r.a[1] == 0); +} + +static void test_pcmpgth_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -42; + s.a[1] = -42; + s.a[2] = -42; + s.a[3] = -42; + t.a[0] = 42; + t.a[1] = 43; + t.a[2] = 44; + t.a[3] = -43; + r.v = pcmpgth_s (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == -1); +} + +static void test_pcmpgtb_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -42; + s.a[1] = -42; + s.a[2] = -42; + s.a[3] = -42; + s.a[4] = 42; + s.a[5] = 42; + s.a[6] = 42; + s.a[7] = 42; + t.a[0] = -45; + t.a[1] = -44; + t.a[2] = -43; + t.a[3] = -42; + t.a[4] = 42; + t.a[5] = 43; + t.a[6] = 41; + t.a[7] = 40; + r.v = pcmpgtb_s (s.v, t.v); + assert (r.a[0] == -1); + assert (r.a[1] == -1); + assert (r.a[2] == -1); + assert (r.a[3] == 0); + assert (r.a[4] == 0); + assert (r.a[5] == 0); + assert (r.a[6] == -1); + assert (r.a[7] == -1); +} + +static void test_pextrh_u (void) +{ + uint16x4_encap_t s; + uint16x4_encap_t r; + s.a[0] = 40; + s.a[1] = 41; + s.a[2] = 42; + s.a[3] = 43; + r.v = pextrh_u (s.v, 1); + assert (r.a[0] == 41); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); +} + +static void test_pextrh_s (void) +{ + int16x4_encap_t s; + int16x4_encap_t r; + s.a[0] = -40; + s.a[1] = -41; + s.a[2] = -42; + s.a[3] = -43; + r.v = pextrh_s (s.v, 2); + assert (r.a[0] == -42); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); +} + +static void test_pinsrh_0123_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 42; + s.a[1] = 0; + s.a[2] = 0; + s.a[3] = 0; + t.a[0] = 0; + t.a[1] = 0; + t.a[2] = 0; + t.a[3] = 0; + r.v = pinsrh_0_u (t.v, s.v); + r.v = pinsrh_1_u (r.v, s.v); + r.v = pinsrh_2_u (r.v, s.v); + r.v = pinsrh_3_u (r.v, s.v); + assert (r.a[0] == 42); + assert (r.a[1] == 42); + assert (r.a[2] == 42); + assert (r.a[3] == 42); +} + +static void test_pinsrh_0123_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -42; + s.a[1] = 0; + s.a[2] = 0; + s.a[3] = 0; + t.a[0] = 0; + t.a[1] = 0; + t.a[2] = 0; + t.a[3] = 0; + r.v = pinsrh_0_s (t.v, s.v); + r.v = pinsrh_1_s (r.v, s.v); + r.v = pinsrh_2_s (r.v, s.v); + r.v = pinsrh_3_s (r.v, s.v); + assert (r.a[0] == -42); + assert (r.a[1] == -42); + assert (r.a[2] == -42); + assert (r.a[3] == -42); +} + +static void test_pmaddhw (void) +{ + int16x4_encap_t s, t; + int32x2_encap_t r; + s.a[0] = -5; + s.a[1] = -4; + s.a[2] = -3; + s.a[3] = -2; + t.a[0] = 10; + t.a[1] = 11; + t.a[2] = 12; + t.a[3] = 13; + r.v = pmaddhw (s.v, t.v); + assert (r.a[0] == (-5*10 + -4*11)); + assert (r.a[1] == (-3*12 + -2*13)); +} + +static void test_pmaxsh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -20; + s.a[1] = 40; + s.a[2] = -10; + s.a[3] = 50; + t.a[0] = 20; + t.a[1] = -40; + t.a[2] = 10; + t.a[3] = -50; + r.v = pmaxsh (s.v, t.v); + assert (r.a[0] == 20); + assert (r.a[1] == 40); + assert (r.a[2] == 10); + assert (r.a[3] == 50); +} + +static void test_pmaxub (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 10; + s.a[1] = 20; + s.a[2] = 30; + s.a[3] = 40; + s.a[4] = 50; + s.a[5] = 60; + s.a[6] = 70; + s.a[7] = 80; + t.a[0] = 80; + t.a[1] = 70; + t.a[2] = 60; + t.a[3] = 50; + t.a[4] = 40; + t.a[5] = 30; + t.a[6] = 20; + t.a[7] = 10; + r.v = pmaxub (s.v, t.v); + assert (r.a[0] == 80); + assert (r.a[1] == 70); + assert (r.a[2] == 60); + assert (r.a[3] == 50); + assert (r.a[4] == 50); + assert (r.a[5] == 60); + assert (r.a[6] == 70); + assert (r.a[7] == 80); +} + +static void test_pminsh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -20; + s.a[1] = 40; + s.a[2] = -10; + s.a[3] = 50; + t.a[0] = 20; + t.a[1] = -40; + t.a[2] = 10; + t.a[3] = -50; + r.v = pminsh (s.v, t.v); + assert (r.a[0] == -20); + assert (r.a[1] == -40); + assert (r.a[2] == -10); + assert (r.a[3] == -50); +} + +static void test_pminub (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 10; + s.a[1] = 20; + s.a[2] = 30; + s.a[3] = 40; + s.a[4] = 50; + s.a[5] = 60; + s.a[6] = 70; + s.a[7] = 80; + t.a[0] = 80; + t.a[1] = 70; + t.a[2] = 60; + t.a[3] = 50; + t.a[4] = 40; + t.a[5] = 30; + t.a[6] = 20; + t.a[7] = 10; + r.v = pminub (s.v, t.v); + assert (r.a[0] == 10); + assert (r.a[1] == 20); + assert (r.a[2] == 30); + assert (r.a[3] == 40); + assert (r.a[4] == 40); + assert (r.a[5] == 30); + assert (r.a[6] == 20); + assert (r.a[7] == 10); +} + +static void test_pmovmskb_u (void) +{ + uint8x8_encap_t s; + uint8x8_encap_t r; + s.a[0] = 0xf0; + s.a[1] = 0x40; + s.a[2] = 0xf0; + s.a[3] = 0x40; + s.a[4] = 0xf0; + s.a[5] = 0x40; + s.a[6] = 0xf0; + s.a[7] = 0x40; + r.v = pmovmskb_u (s.v); + assert (r.a[0] == 0x55); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); + assert (r.a[4] == 0); + assert (r.a[5] == 0); + assert (r.a[6] == 0); + assert (r.a[7] == 0); +} + +static void test_pmovmskb_s (void) +{ + int8x8_encap_t s; + int8x8_encap_t r; + s.a[0] = -1; + s.a[1] = 1; + s.a[2] = -1; + s.a[3] = 1; + s.a[4] = -1; + s.a[5] = 1; + s.a[6] = -1; + s.a[7] = 1; + r.v = pmovmskb_s (s.v); + assert (r.a[0] == 0x55); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); + assert (r.a[4] == 0); + assert (r.a[5] == 0); + assert (r.a[6] == 0); + assert (r.a[7] == 0); +} + +static void test_pmulhuh (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 0xff00; + s.a[1] = 0xff00; + s.a[2] = 0xff00; + s.a[3] = 0xff00; + t.a[0] = 16; + t.a[1] = 16; + t.a[2] = 16; + t.a[3] = 16; + r.v = pmulhuh (s.v, t.v); + assert (r.a[0] == 0x000f); + assert (r.a[1] == 0x000f); + assert (r.a[2] == 0x000f); + assert (r.a[3] == 0x000f); +} + +static void test_pmulhh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = 0x0ff0; + s.a[1] = 0x0ff0; + s.a[2] = 0x0ff0; + s.a[3] = 0x0ff0; + t.a[0] = -16*16; + t.a[1] = -16*16; + t.a[2] = -16*16; + t.a[3] = -16*16; + r.v = pmulhh (s.v, t.v); + assert (r.a[0] == -16); + assert (r.a[1] == -16); + assert (r.a[2] == -16); + assert (r.a[3] == -16); +} + +static void test_pmullh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = 0x0ff0; + s.a[1] = 0x0ff0; + s.a[2] = 0x0ff0; + s.a[3] = 0x0ff0; + t.a[0] = -16*16; + t.a[1] = -16*16; + t.a[2] = -16*16; + t.a[3] = -16*16; + r.v = pmullh (s.v, t.v); + assert (r.a[0] == 4096); + assert (r.a[1] == 4096); + assert (r.a[2] == 4096); + assert (r.a[3] == 4096); +} + +static void test_pmuluw (void) +{ + uint32x2_encap_t s, t; + uint64_t r; + s.a[0] = 0xdeadbeef; + s.a[1] = 0; + t.a[0] = 0x0f00baaa; + t.a[1] = 0; + r = pmuluw (s.v, t.v); + assert (r == 0xd0cd08e1d1a70b6ull); +} + +static void test_pasubub (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 10; + s.a[1] = 20; + s.a[2] = 30; + s.a[3] = 40; + s.a[4] = 50; + s.a[5] = 60; + s.a[6] = 70; + s.a[7] = 80; + t.a[0] = 80; + t.a[1] = 70; + t.a[2] = 60; + t.a[3] = 50; + t.a[4] = 40; + t.a[5] = 30; + t.a[6] = 20; + t.a[7] = 10; + r.v = pasubub (s.v, t.v); + assert (r.a[0] == 70); + assert (r.a[1] == 50); + assert (r.a[2] == 30); + assert (r.a[3] == 10); + assert (r.a[4] == 10); + assert (r.a[5] == 30); + assert (r.a[6] == 50); + assert (r.a[7] == 70); +} + +static void test_biadd (void) +{ + uint8x8_encap_t s; + uint16x4_encap_t r; + s.a[0] = 10; + s.a[1] = 20; + s.a[2] = 30; + s.a[3] = 40; + s.a[4] = 50; + s.a[5] = 60; + s.a[6] = 70; + s.a[7] = 80; + r.v = biadd (s.v); + assert (r.a[0] == 360); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); +} + +static void test_psadbh (void) +{ + uint8x8_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 10; + s.a[1] = 20; + s.a[2] = 30; + s.a[3] = 40; + s.a[4] = 50; + s.a[5] = 60; + s.a[6] = 70; + s.a[7] = 80; + t.a[0] = 80; + t.a[1] = 70; + t.a[2] = 60; + t.a[3] = 50; + t.a[4] = 40; + t.a[5] = 30; + t.a[6] = 20; + t.a[7] = 10; + r.v = psadbh (s.v, t.v); + assert (r.a[0] == 0x0140); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); +} + +static void test_pshufh_u (void) +{ + uint16x4_encap_t s; + uint16x4_encap_t r; + s.a[0] = 1; + s.a[1] = 2; + s.a[2] = 3; + s.a[3] = 4; + r.a[0] = 0; + r.a[1] = 0; + r.a[2] = 0; + r.a[3] = 0; + r.v = pshufh_u (r.v, s.v, 0xe5); + assert (r.a[0] == 2); + assert (r.a[1] == 2); + assert (r.a[2] == 3); + assert (r.a[3] == 4); +} + +static void test_pshufh_s (void) +{ + int16x4_encap_t s; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = 2; + s.a[2] = -3; + s.a[3] = 4; + r.a[0] = 0; + r.a[1] = 0; + r.a[2] = 0; + r.a[3] = 0; + r.v = pshufh_s (r.v, s.v, 0xe5); + assert (r.a[0] == 2); + assert (r.a[1] == 2); + assert (r.a[2] == -3); + assert (r.a[3] == 4); +} + +static void test_psllh_u (void) +{ + uint16x4_encap_t s; + uint16x4_encap_t r; + s.a[0] = 0xffff; + s.a[1] = 0xffff; + s.a[2] = 0xffff; + s.a[3] = 0xffff; + r.v = psllh_u (s.v, 1); + assert (r.a[0] == 0xfffe); + assert (r.a[1] == 0xfffe); + assert (r.a[2] == 0xfffe); + assert (r.a[3] == 0xfffe); +} + +static void test_psllw_u (void) +{ + uint32x2_encap_t s; + uint32x2_encap_t r; + s.a[0] = 0xffffffff; + s.a[1] = 0xffffffff; + r.v = psllw_u (s.v, 2); + assert (r.a[0] == 0xfffffffc); + assert (r.a[1] == 0xfffffffc); +} + +static void test_psllh_s (void) +{ + int16x4_encap_t s; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = -1; + s.a[2] = -1; + s.a[3] = -1; + r.v = psllh_s (s.v, 1); + assert (r.a[0] == -2); + assert (r.a[1] == -2); + assert (r.a[2] == -2); + assert (r.a[3] == -2); +} + +static void test_psllw_s (void) +{ + int32x2_encap_t s; + int32x2_encap_t r; + s.a[0] = -1; + s.a[1] = -1; + r.v = psllw_s (s.v, 2); + assert (r.a[0] == -4); + assert (r.a[1] == -4); +} + +static void test_psrah_u (void) +{ + uint16x4_encap_t s; + uint16x4_encap_t r; + s.a[0] = 0xffef; + s.a[1] = 0xffef; + s.a[2] = 0xffef; + s.a[3] = 0xffef; + r.v = psrah_u (s.v, 1); + assert (r.a[0] == 0xfff7); + assert (r.a[1] == 0xfff7); + assert (r.a[2] == 0xfff7); + assert (r.a[3] == 0xfff7); +} + +static void test_psraw_u (void) +{ + uint32x2_encap_t s; + uint32x2_encap_t r; + s.a[0] = 0xffffffef; + s.a[1] = 0xffffffef; + r.v = psraw_u (s.v, 1); + assert (r.a[0] == 0xfffffff7); + assert (r.a[1] == 0xfffffff7); +} + +static void test_psrah_s (void) +{ + int16x4_encap_t s; + int16x4_encap_t r; + s.a[0] = -2; + s.a[1] = -2; + s.a[2] = -2; + s.a[3] = -2; + r.v = psrah_s (s.v, 1); + assert (r.a[0] == -1); + assert (r.a[1] == -1); + assert (r.a[2] == -1); + assert (r.a[3] == -1); +} + +static void test_psraw_s (void) +{ + int32x2_encap_t s; + int32x2_encap_t r; + s.a[0] = -2; + s.a[1] = -2; + r.v = psraw_s (s.v, 1); + assert (r.a[0] == -1); + assert (r.a[1] == -1); +} + +static void test_psrlh_u (void) +{ + uint16x4_encap_t s; + uint16x4_encap_t r; + s.a[0] = 0xffef; + s.a[1] = 0xffef; + s.a[2] = 0xffef; + s.a[3] = 0xffef; + r.v = psrlh_u (s.v, 1); + assert (r.a[0] == 0x7ff7); + assert (r.a[1] == 0x7ff7); + assert (r.a[2] == 0x7ff7); + assert (r.a[3] == 0x7ff7); +} + +static void test_psrlw_u (void) +{ + uint32x2_encap_t s; + uint32x2_encap_t r; + s.a[0] = 0xffffffef; + s.a[1] = 0xffffffef; + r.v = psrlw_u (s.v, 1); + assert (r.a[0] == 0x7ffffff7); + assert (r.a[1] == 0x7ffffff7); +} + +static void test_psrlh_s (void) +{ + int16x4_encap_t s; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = -1; + s.a[2] = -1; + s.a[3] = -1; + r.v = psrlh_s (s.v, 1); + assert (r.a[0] == INT16x4_MAX); + assert (r.a[1] == INT16x4_MAX); + assert (r.a[2] == INT16x4_MAX); + assert (r.a[3] == INT16x4_MAX); +} + +static void test_psrlw_s (void) +{ + int32x2_encap_t s; + int32x2_encap_t r; + s.a[0] = -1; + s.a[1] = -1; + r.v = psrlw_s (s.v, 1); + assert (r.a[0] == INT32x2_MAX); + assert (r.a[1] == INT32x2_MAX); +} + +static void test_psubw_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 3; + s.a[1] = 4; + t.a[0] = 2; + t.a[1] = 1; + r.v = psubw_u (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == 3); +} + +static void test_psubw_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = -2; + s.a[1] = -1; + t.a[0] = 3; + t.a[1] = -4; + r.v = psubw_s (s.v, t.v); + assert (r.a[0] == -5); + assert (r.a[1] == 3); +} + +static void test_psubh_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 5; + s.a[1] = 6; + s.a[2] = 7; + s.a[3] = 8; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + r.v = psubh_u (s.v, t.v); + assert (r.a[0] == 4); + assert (r.a[1] == 4); + assert (r.a[2] == 4); + assert (r.a[3] == 4); +} + +static void test_psubh_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -10; + s.a[1] = -20; + s.a[2] = -30; + s.a[3] = -40; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + r.v = psubh_s (s.v, t.v); + assert (r.a[0] == -11); + assert (r.a[1] == -22); + assert (r.a[2] == -33); + assert (r.a[3] == -44); +} + +static void test_psubb_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 10; + s.a[1] = 11; + s.a[2] = 12; + s.a[3] = 13; + s.a[4] = 14; + s.a[5] = 15; + s.a[6] = 16; + s.a[7] = 17; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + t.a[4] = 5; + t.a[5] = 6; + t.a[6] = 7; + t.a[7] = 8; + r.v = psubb_u (s.v, t.v); + assert (r.a[0] == 9); + assert (r.a[1] == 9); + assert (r.a[2] == 9); + assert (r.a[3] == 9); + assert (r.a[4] == 9); + assert (r.a[5] == 9); + assert (r.a[6] == 9); + assert (r.a[7] == 9); +} + +static void test_psubb_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -10; + s.a[1] = -20; + s.a[2] = -30; + s.a[3] = -40; + s.a[4] = -50; + s.a[5] = -60; + s.a[6] = -70; + s.a[7] = -80; + t.a[0] = 1; + t.a[1] = 2; + t.a[2] = 3; + t.a[3] = 4; + t.a[4] = 5; + t.a[5] = 6; + t.a[6] = 7; + t.a[7] = 8; + r.v = psubb_s (s.v, t.v); + assert (r.a[0] == -11); + assert (r.a[1] == -22); + assert (r.a[2] == -33); + assert (r.a[3] == -44); + assert (r.a[4] == -55); + assert (r.a[5] == -66); + assert (r.a[6] == -77); + assert (r.a[7] == -88); +} + +static void test_psubd_u (void) +{ + uint64_t d = 789012; + uint64_t e = 123456; + uint64_t r; + r = psubd_u (d, e); + assert (r == 665556); +} + +static void test_psubd_s (void) +{ + int64_t d = 123456; + int64_t e = -789012; + int64_t r; + r = psubd_s (d, e); + assert (r == 912468); +} + +static void test_psubsh (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = 0; + s.a[2] = 1; + s.a[3] = 2; + t.a[0] = -INT16x4_MAX; + t.a[1] = -INT16x4_MAX; + t.a[2] = -INT16x4_MAX; + t.a[3] = -INT16x4_MAX; + r.v = psubsh (s.v, t.v); + assert (r.a[0] == INT16x4_MAX - 1); + assert (r.a[1] == INT16x4_MAX); + assert (r.a[2] == INT16x4_MAX); + assert (r.a[3] == INT16x4_MAX); +} + +static void test_psubsb (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -6; + s.a[1] = -5; + s.a[2] = -4; + s.a[3] = -3; + s.a[4] = -2; + s.a[5] = -1; + s.a[6] = 0; + s.a[7] = 1; + t.a[0] = -INT8x8_MAX; + t.a[1] = -INT8x8_MAX; + t.a[2] = -INT8x8_MAX; + t.a[3] = -INT8x8_MAX; + t.a[4] = -INT8x8_MAX; + t.a[5] = -INT8x8_MAX; + t.a[6] = -INT8x8_MAX; + t.a[7] = -INT8x8_MAX; + r.v = psubsb (s.v, t.v); + assert (r.a[0] == INT8x8_MAX - 6); + assert (r.a[1] == INT8x8_MAX - 5); + assert (r.a[2] == INT8x8_MAX - 4); + assert (r.a[3] == INT8x8_MAX - 3); + assert (r.a[4] == INT8x8_MAX - 2); + assert (r.a[5] == INT8x8_MAX - 1); + assert (r.a[6] == INT8x8_MAX); + assert (r.a[7] == INT8x8_MAX); +} + +static void test_psubush (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 0; + s.a[1] = 1; + s.a[2] = 2; + s.a[3] = 3; + t.a[0] = 1; + t.a[1] = 1; + t.a[2] = 3; + t.a[3] = 3; + r.v = psubush (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); +} + +static void test_psubusb (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 0; + s.a[1] = 1; + s.a[2] = 2; + s.a[3] = 3; + s.a[4] = 4; + s.a[5] = 5; + s.a[6] = 6; + s.a[7] = 7; + t.a[0] = 1; + t.a[1] = 1; + t.a[2] = 3; + t.a[3] = 3; + t.a[4] = 5; + t.a[5] = 5; + t.a[6] = 7; + t.a[7] = 7; + r.v = psubusb (s.v, t.v); + assert (r.a[0] == 0); + assert (r.a[1] == 0); + assert (r.a[2] == 0); + assert (r.a[3] == 0); + assert (r.a[4] == 0); + assert (r.a[5] == 0); + assert (r.a[6] == 0); + assert (r.a[7] == 0); +} + +static void test_punpckhbh_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -1; + s.a[1] = -3; + s.a[2] = -5; + s.a[3] = -7; + s.a[4] = -9; + s.a[5] = -11; + s.a[6] = -13; + s.a[7] = -15; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + t.a[4] = 10; + t.a[5] = 12; + t.a[6] = 14; + t.a[7] = 16; + r.v = punpckhbh_s (s.v, t.v); + assert (r.a[0] == -9); + assert (r.a[1] == 10); + assert (r.a[2] == -11); + assert (r.a[3] == 12); + assert (r.a[4] == -13); + assert (r.a[5] == 14); + assert (r.a[6] == -15); + assert (r.a[7] == 16); +} + +static void test_punpckhbh_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + s.a[2] = 5; + s.a[3] = 7; + s.a[4] = 9; + s.a[5] = 11; + s.a[6] = 13; + s.a[7] = 15; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + t.a[4] = 10; + t.a[5] = 12; + t.a[6] = 14; + t.a[7] = 16; + r.v = punpckhbh_u (s.v, t.v); + assert (r.a[0] == 9); + assert (r.a[1] == 10); + assert (r.a[2] == 11); + assert (r.a[3] == 12); + assert (r.a[4] == 13); + assert (r.a[5] == 14); + assert (r.a[6] == 15); + assert (r.a[7] == 16); +} + +static void test_punpckhhw_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = 3; + s.a[2] = -5; + s.a[3] = 7; + t.a[0] = -2; + t.a[1] = 4; + t.a[2] = -6; + t.a[3] = 8; + r.v = punpckhhw_s (s.v, t.v); + assert (r.a[0] == -5); + assert (r.a[1] == -6); + assert (r.a[2] == 7); + assert (r.a[3] == 8); +} + +static void test_punpckhhw_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + s.a[2] = 5; + s.a[3] = 7; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + r.v = punpckhhw_u (s.v, t.v); + assert (r.a[0] == 5); + assert (r.a[1] == 6); + assert (r.a[2] == 7); + assert (r.a[3] == 8); +} + +static void test_punpckhwd_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + t.a[0] = 2; + t.a[1] = -4; + r.v = punpckhwd_s (s.v, t.v); + assert (r.a[0] == 3); + assert (r.a[1] == -4); +} + +static void test_punpckhwd_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + t.a[0] = 2; + t.a[1] = 4; + r.v = punpckhwd_u (s.v, t.v); + assert (r.a[0] == 3); + assert (r.a[1] == 4); +} + +static void test_punpcklbh_s (void) +{ + int8x8_encap_t s, t; + int8x8_encap_t r; + s.a[0] = -1; + s.a[1] = -3; + s.a[2] = -5; + s.a[3] = -7; + s.a[4] = -9; + s.a[5] = -11; + s.a[6] = -13; + s.a[7] = -15; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + t.a[4] = 10; + t.a[5] = 12; + t.a[6] = 14; + t.a[7] = 16; + r.v = punpcklbh_s (s.v, t.v); + assert (r.a[0] == -1); + assert (r.a[1] == 2); + assert (r.a[2] == -3); + assert (r.a[3] == 4); + assert (r.a[4] == -5); + assert (r.a[5] == 6); + assert (r.a[6] == -7); + assert (r.a[7] == 8); +} + +static void test_punpcklbh_u (void) +{ + uint8x8_encap_t s, t; + uint8x8_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + s.a[2] = 5; + s.a[3] = 7; + s.a[4] = 9; + s.a[5] = 11; + s.a[6] = 13; + s.a[7] = 15; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + t.a[4] = 10; + t.a[5] = 12; + t.a[6] = 14; + t.a[7] = 16; + r.v = punpcklbh_u (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == 2); + assert (r.a[2] == 3); + assert (r.a[3] == 4); + assert (r.a[4] == 5); + assert (r.a[5] == 6); + assert (r.a[6] == 7); + assert (r.a[7] == 8); +} + +static void test_punpcklhw_s (void) +{ + int16x4_encap_t s, t; + int16x4_encap_t r; + s.a[0] = -1; + s.a[1] = 3; + s.a[2] = -5; + s.a[3] = 7; + t.a[0] = -2; + t.a[1] = 4; + t.a[2] = -6; + t.a[3] = 8; + r.v = punpcklhw_s (s.v, t.v); + assert (r.a[0] == -1); + assert (r.a[1] == -2); + assert (r.a[2] == 3); + assert (r.a[3] == 4); +} + +static void test_punpcklhw_u (void) +{ + uint16x4_encap_t s, t; + uint16x4_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + s.a[2] = 5; + s.a[3] = 7; + t.a[0] = 2; + t.a[1] = 4; + t.a[2] = 6; + t.a[3] = 8; + r.v = punpcklhw_u (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == 2); + assert (r.a[2] == 3); + assert (r.a[3] == 4); +} + +static void test_punpcklwd_s (void) +{ + int32x2_encap_t s, t; + int32x2_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + t.a[0] = -2; + t.a[1] = 4; + r.v = punpcklwd_s (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == -2); +} + +static void test_punpcklwd_u (void) +{ + uint32x2_encap_t s, t; + uint32x2_encap_t r; + s.a[0] = 1; + s.a[1] = 3; + t.a[0] = 2; + t.a[1] = 4; + r.v = punpcklwd_u (s.v, t.v); + assert (r.a[0] == 1); + assert (r.a[1] == 2); +} + +int main (void) +{ + test_packsswh (); + test_packsshb (); + test_packushb (); + test_paddw_u (); + test_paddw_s (); + test_paddh_u (); + test_paddh_s (); + test_paddb_u (); + test_paddb_s (); + test_paddd_u (); + test_paddd_s (); + test_paddsh (); + test_paddsb (); + test_paddush (); + test_paddusb (); + test_pandn_ud (); + test_pandn_sd (); + test_pandn_uw (); + test_pandn_sw (); + test_pandn_uh (); + test_pandn_sh (); + test_pandn_ub (); + test_pandn_sb (); + test_pavgh (); + test_pavgb (); + test_pcmpeqw_u (); + test_pcmpeqh_u (); + test_pcmpeqb_u (); + test_pcmpeqw_s (); + test_pcmpeqh_s (); + test_pcmpeqb_s (); + test_pcmpgtw_u (); + test_pcmpgth_u (); + test_pcmpgtb_u (); + test_pcmpgtw_s (); + test_pcmpgth_s (); + test_pcmpgtb_s (); + test_pextrh_u (); + test_pextrh_s (); + test_pinsrh_0123_u (); + test_pinsrh_0123_s (); + test_pmaddhw (); + test_pmaxsh (); + test_pmaxub (); + test_pminsh (); + test_pminub (); + test_pmovmskb_u (); + test_pmovmskb_s (); + test_pmulhuh (); + test_pmulhh (); + test_pmullh (); + test_pmuluw (); + test_pasubub (); + test_biadd (); + test_psadbh (); + test_pshufh_u (); + test_pshufh_s (); + test_psllh_u (); + test_psllw_u (); + test_psllh_s (); + test_psllw_s (); + test_psrah_u (); + test_psraw_u (); + test_psrah_s (); + test_psraw_s (); + test_psrlh_u (); + test_psrlw_u (); + test_psrlh_s (); + test_psrlw_s (); + test_psubw_u (); + test_psubw_s (); + test_psubh_u (); + test_psubh_s (); + test_psubb_u (); + test_psubb_s (); + test_psubd_u (); + test_psubd_s (); + test_psubsh (); + test_psubsb (); + test_psubush (); + test_psubusb (); + test_punpckhbh_s (); + test_punpckhbh_u (); + test_punpckhhw_s (); + test_punpckhhw_u (); + test_punpckhwd_s (); + test_punpckhwd_u (); + test_punpcklbh_s (); + test_punpcklbh_u (); + test_punpcklhw_s (); + test_punpcklhw_u (); + test_punpcklwd_s (); + test_punpcklwd_u (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c new file mode 100644 index 000000000..1c4d010b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=loongson3a" } */ + +typedef int st; +typedef unsigned int ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tgsmultu\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tgsdivu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsmodu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsmod\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c new file mode 100644 index 000000000..9695b3f62 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=loongson3a -mgp64" } */ + +typedef long long st; +typedef unsigned long long ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tgsdmultu\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tgsddivu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdmodu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsddiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdmod\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c new file mode 100644 index 000000000..416673b46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr4130 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return (long long) x * y + z; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + return z + (long long) y * x; +} + +NOMIPS16 long long +f3 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c new file mode 100644 index 000000000..ce0d9eb6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return (long long) x * y + z; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + return z + (long long) y * x; +} + +NOMIPS16 long long +f3 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c new file mode 100644 index 000000000..29f4c9b37 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=1 -mgp32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return (long long) x * y + z; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + return z + (long long) y * x; +} + +NOMIPS16 long long +f3 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c new file mode 100644 index 000000000..28c751b40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return (long long) x * y + z; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + return z + (long long) y * x; +} + +NOMIPS16 long long +f3 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c new file mode 100644 index 000000000..d1696a6a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c @@ -0,0 +1,9 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmadd\t" 4 } } */ +/* { dg-final { scan-assembler-not "\tmtlo\t" } } */ +/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */ + +NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3]; } +NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4]; } +NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4] * a[5]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c new file mode 100644 index 000000000..9323b8e10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c @@ -0,0 +1,7 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmadd\t" } } */ +/* { dg-final { scan-assembler "\tmul\t" } } */ +/* { dg-final { scan-assembler "\taddu\t" } } */ + +NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c new file mode 100644 index 000000000..a639aa4f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-skip-if "requires -fira-region=all or =mixed" { *-*-* } { "-Os" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +/* { dg-final { scan-assembler "\tmadd\t" } } */ + +NOMIPS16 int +f1 (int *a, int *b, int n) +{ + int x, i; + + x = 0; + for (i = 0; i < n; i++) + x += a[i] * b[i]; + return x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c new file mode 100644 index 000000000..794a6ff17 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmul\t" } } */ +/* { dg-final { scan-assembler-not "\tmadd\t" } } */ +/* { dg-final { scan-assembler-not "\tmtlo\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +NOMIPS16 int +f2 (int x, int y, int z) +{ + asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", + "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", + "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", + "$31"); + return x * y + z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c new file mode 100644 index 000000000..28681a910 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=1 -mgp32 -mtune=4kc" } */ +/* References to X within the loop need to have a higher frequency than + references to X outside the loop, otherwise there is no reason + to prefer multiply/accumulator registers over GPRs. */ +/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +/* { dg-final { scan-assembler-not "\tmthi" } } */ +/* { dg-final { scan-assembler-not "\tmtlo" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmadd\t" } } */ + +NOMIPS16 long long +f1 (int *a, int *b, int n) +{ + long long int x; + int i; + + x = 0; + for (i = 0; i < n; i++) + x += (long long) a[i] * b[i]; + return x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c new file mode 100644 index 000000000..af2b4181c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr4130 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmaccu\t\\\$1," 3 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return (ull) x * y + z; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + return z + (ull) y * x; +} + +NOMIPS16 ull +f3 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c new file mode 100644 index 000000000..ea091e4e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return (ull) x * y + z; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + return z + (ull) y * x; +} + +NOMIPS16 ull +f3 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c new file mode 100644 index 000000000..27a7350f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return (ull) x * y + z; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + return z + (ull) y * x; +} + +NOMIPS16 ull +f3 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c new file mode 100644 index 000000000..58c4a7ebe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmaddu\t\\\$ac" 3 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return (ull) x * y + z; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + return z + (ull) y * x; +} + +NOMIPS16 ull +f3 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z += t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c new file mode 100644 index 000000000..94786a737 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c @@ -0,0 +1,19 @@ +/* { dg-options "-fno-common" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tlbu\t" } } */ + +#include <string.h> + +char c[10]; + +void +f1 () +{ + memcpy (c, "123456", 6); +} + +void +f2 () +{ + memcpy (c, &"12345678"[2], 6); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c new file mode 100644 index 000000000..f11ffc5a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c @@ -0,0 +1,127 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int main () +{ + int little_endian; + v2sf a, b, c, d; + float f1, f2, f3, f4, f5, f6; + double d1, d2, d3, d4, d5, d6, d7, d8, d9; + v2sf ps1, ps2, ps3, ps4, ps5, ps6; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + /* addr.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {45, 67}; + c = __builtin_mips_addr_ps (a, b); + if (little_endian) + d = (v2sf) {112, 46}; + else + d = (v2sf) {46, 112}; + + if (!__builtin_mips_all_c_eq_ps(c, d)) + abort (); + + /* mulr.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {45, 67}; + c = __builtin_mips_mulr_ps (a, b); + if (little_endian) + d = (v2sf) {3015, 408}; + else + d = (v2sf) {408, 3015}; + + if (!__builtin_mips_all_c_eq_ps(c, d)) + abort (); + + /* cvt.pw.ps */ + a = (v2sf) {12345.34, 67890.45}; + b = __builtin_mips_cvt_pw_ps (a); + + /* cvt.ps.pw */ + c = __builtin_mips_cvt_ps_pw (b); + d = (v2sf) {12345.0, 67890.0}; + + if (!__builtin_mips_all_c_eq_ps(c, d)) + abort (); + + /* recip1.s recip2.s */ + f1 = 40; + f2 = __builtin_mips_recip1_s (f1); + f3 = __builtin_mips_recip2_s (f2, f1); + f4 = f2 + f2 * f3; + f5 = 0.025; + + if (f4 != f5) + abort (); + + /* recip1.d recip2.d */ + d1 = 80; + d2 = __builtin_mips_recip1_d (d1); + d3 = __builtin_mips_recip2_d (d2, d1); + d4 = d2 + d2 * d3; + d5 = __builtin_mips_recip2_d (d4, d1); + d6 = d4 + d4 * d5; + d7 = 0.0125; + + if (d6 != d7) + abort (); + + /* recip1.ps recip2.ps */ + ps1 = (v2sf) {100, 200}; + ps2 = __builtin_mips_recip1_ps (ps1); + ps3 = __builtin_mips_recip2_ps (ps2, ps1); + ps4 = ps2 + ps2 * ps3; + ps5 = (v2sf) {0.01, 0.005}; + + if (!__builtin_mips_all_c_eq_ps(ps4, ps5)) + abort (); + + /* rsqrt1.s rsqrt2.s */ + f1 = 400; + f2 = __builtin_mips_rsqrt1_s (f1); + f3 = f2 * f1; + f4 = __builtin_mips_rsqrt2_s (f3, f2); + f5 = f2 + f2 * f4; + f6 = 0.05; + + if (f5 != f6) + abort (); + + /* rsqrt1.d rsqrt2.d */ + d1 = 1600; + d2 = __builtin_mips_rsqrt1_d (d1); + d3 = d2 * d1; + d4 = __builtin_mips_rsqrt2_d (d3, d2); + d5 = d2 + d2 * d4; + d6 = d1 * d5; + d7 = __builtin_mips_rsqrt2_d (d6, d5); + d8 = d5 + d5 * d7; + d9 = 0.025; + + if (d8 != d9) + abort (); + + /* rsqrt1.ps rsqrt2.ps */ + ps1 = (v2sf) {400, 100}; + ps2 = __builtin_mips_rsqrt1_ps (ps1); + ps3 = ps2 * ps1; + ps4 = __builtin_mips_rsqrt2_ps (ps3, ps2); + ps5 = ps2 + ps2 * ps4; + ps6 = (v2sf) {0.05, 0.1}; + + if (!__builtin_mips_all_c_eq_ps(ps5, ps6)) + abort (); + + printf ("Test Passes\n"); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c new file mode 100644 index 000000000..b04c3bfb5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c @@ -0,0 +1,554 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D branch-if-any-two builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + v2sf a, b, c, d; + int i, j; + + /* c.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {56, 78}; + i = 0; + j = 0; + if (__builtin_mips_any_c_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_all_c_eq_ps(a, b) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {12, 78}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_all_c_eq_ps(a, b) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {56, 34}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_all_c_eq_ps(a, b) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {12, 34}; + i = 1; + j = 1; + if (__builtin_mips_any_c_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_all_c_eq_ps(a, b) != j) + abort (); + + /* Test with 16 operators */ + a = (v2sf) {10.58, 1984.0}; + b = (v2sf) {567.345, 1984.0}; + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 0) + abort (); + i = test4 (a, b); + if (i != 1) + abort (); + i = test5 (a, b); + if (i != 0) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 0) + abort (); + i = test8 (a, b); + if (i != 1) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 0) + abort (); + i = test12 (a, b); + if (i != 1) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + i = test16 (a, b); + if (i != 0) + abort (); + i = test17 (a, b); + if (i != 0) + abort (); + i = test18 (a, b); + if (i != 0) + abort (); + i = test19 (a, b); + if (i != 0) + abort (); + i = test20 (a, b); + if (i != 1) + abort (); + i = test21 (a, b); + if (i != 0) + abort (); + i = test22 (a, b); + if (i != 1) + abort (); + i = test23 (a, b); + if (i != 0) + abort (); + i = test24 (a, b); + if (i != 1) + abort (); + i = test25 (a, b); + if (i != 0) + abort (); + i = test26 (a, b); + if (i != 1) + abort (); + i = test27 (a, b); + if (i != 0) + abort (); + i = test28 (a, b); + if (i != 1) + abort (); + i = test29 (a, b); + if (i != 1) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); + + /* Reverse arguments */ + i = test0 (b, a); + if (i != 0) + abort (); + i = test1 (b, a); + if (i != 0) + abort (); + i = test2 (b, a); + if (i != 0) + abort (); + i = test3 (b, a); + if (i != 0) + abort (); + i = test4 (b, a); + if (i != 1) + abort (); + i = test5 (b, a); + if (i != 0) + abort (); + i = test6 (b, a); + if (i != 1) + abort (); + i = test7 (b, a); + if (i != 0) + abort (); + i = test8 (b, a); + if (i != 0) + abort (); + i = test9 (b, a); + if (i != 0) + abort (); + i = test10 (b, a); + if (i != 0) + abort (); + i = test11 (b, a); + if (i != 0) + abort (); + i = test12 (b, a); + if (i != 1) + abort (); + i = test13 (b, a); + if (i != 0) + abort (); + i = test14 (b, a); + if (i != 1) + abort (); + i = test15 (b, a); + if (i != 0) + abort (); + i = test16 (b, a); + if (i != 0) + abort (); + i = test17 (b, a); + if (i != 0) + abort (); + i = test18 (b, a); + if (i != 0) + abort (); + i = test19 (b, a); + if (i != 0) + abort (); + i = test20 (b, a); + if (i != 1) + abort (); + i = test21 (b, a); + if (i != 0) + abort (); + i = test22 (b, a); + if (i != 1) + abort (); + i = test23 (b, a); + if (i != 0) + abort (); + i = test24 (b, a); + if (i != 0) + abort (); + i = test25 (b, a); + if (i != 0) + abort (); + i = test26 (b, a); + if (i != 0) + abort (); + i = test27 (b, a); + if (i != 0) + abort (); + i = test28 (b, a); + if (i != 1) + abort (); + i = test29 (b, a); + if (i != 0) + abort (); + i = test30 (b, a); + if (i != 1) + abort (); + i = test31 (b, a); + if (i != 0) + abort (); + +#ifndef __FAST_MATH__ + /* Test with 16 operators */ + a = (v2sf) {qnan, qnan}; + b = (v2sf) {567.345, 1984.0}; + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 1) + abort (); + i = test3 (a, b); + if (i != 1) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 0) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 1) + abort (); + i = test12 (a, b); + if (i != 0) + abort (); + i = test13 (a, b); + if (i != 0) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + i = test16 (a, b); + if (i != 0) + abort (); + i = test17 (a, b); + if (i != 0) + abort (); + i = test18 (a, b); + if (i != 1) + abort (); + i = test19 (a, b); + if (i != 1) + abort (); + i = test20 (a, b); + if (i != 0) + abort (); + i = test21 (a, b); + if (i != 0) + abort (); + i = test22 (a, b); + if (i != 1) + abort (); + i = test23 (a, b); + if (i != 1) + abort (); + i = test24 (a, b); + if (i != 0) + abort (); + i = test25 (a, b); + if (i != 0) + abort (); + i = test26 (a, b); + if (i != 1) + abort (); + i = test27 (a, b); + if (i != 1) + abort (); + i = test28 (a, b); + if (i != 0) + abort (); + i = test29 (a, b); + if (i != 0) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_f_ps (a, b); +} + +NOMIPS16 int test1 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_f_ps (a, b); +} + +NOMIPS16 int test2 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_un_ps (a, b); +} + +NOMIPS16 int test3 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_un_ps (a, b); +} + +NOMIPS16 int test4 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_eq_ps (a, b); +} + +NOMIPS16 int test5 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_eq_ps (a, b); +} + +NOMIPS16 int test6 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ueq_ps (a, b); +} + +NOMIPS16 int test7 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ueq_ps (a, b); +} + +NOMIPS16 int test8 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_olt_ps (a, b); +} + +NOMIPS16 int test9 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_olt_ps (a, b); +} + +NOMIPS16 int test10 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ult_ps (a, b); +} + +NOMIPS16 int test11 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ult_ps (a, b); +} + +NOMIPS16 int test12 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ole_ps (a, b); +} + +NOMIPS16 int test13 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ole_ps (a, b); +} + +NOMIPS16 int test14 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ule_ps (a, b); +} + +NOMIPS16 int test15 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ule_ps (a, b); +} + +NOMIPS16 int test16 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_sf_ps (a, b); +} + +NOMIPS16 int test17 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_sf_ps (a, b); +} + +NOMIPS16 int test18 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ngle_ps (a, b); +} + +NOMIPS16 int test19 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ngle_ps (a, b); +} + +NOMIPS16 int test20 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_seq_ps (a, b); +} + +NOMIPS16 int test21 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_seq_ps (a, b); +} + +NOMIPS16 int test22 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ngl_ps (a, b); +} + +NOMIPS16 int test23 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ngl_ps (a, b); +} + +NOMIPS16 int test24 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_lt_ps (a, b); +} + +NOMIPS16 int test25 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_lt_ps (a, b); +} + +NOMIPS16 int test26 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_nge_ps (a, b); +} + +NOMIPS16 int test27 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_nge_ps (a, b); +} + +NOMIPS16 int test28 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_le_ps (a, b); +} + +NOMIPS16 int test29 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_le_ps (a, b); +} + +NOMIPS16 int test30 (v2sf a, v2sf b) +{ + return __builtin_mips_any_c_ngt_ps (a, b); +} + +NOMIPS16 int test31 (v2sf a, v2sf b) +{ + return __builtin_mips_all_c_ngt_ps (a, b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c new file mode 100644 index 000000000..e4de8fb19 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c @@ -0,0 +1,1095 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D absolute compare builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); +NOMIPS16 int test32 (v2sf a, v2sf b); +NOMIPS16 int test33 (v2sf a, v2sf b); +NOMIPS16 int test34 (v2sf a, v2sf b); +NOMIPS16 int test35 (v2sf a, v2sf b); +NOMIPS16 int test36 (v2sf a, v2sf b); +NOMIPS16 int test37 (v2sf a, v2sf b); +NOMIPS16 int test38 (v2sf a, v2sf b); +NOMIPS16 int test39 (v2sf a, v2sf b); +NOMIPS16 int test40 (v2sf a, v2sf b); +NOMIPS16 int test41 (v2sf a, v2sf b); +NOMIPS16 int test42 (v2sf a, v2sf b); +NOMIPS16 int test43 (v2sf a, v2sf b); +NOMIPS16 int test44 (v2sf a, v2sf b); +NOMIPS16 int test45 (v2sf a, v2sf b); +NOMIPS16 int test46 (v2sf a, v2sf b); +NOMIPS16 int test47 (v2sf a, v2sf b); +NOMIPS16 int test48 (v2sf a, v2sf b); +NOMIPS16 int test49 (v2sf a, v2sf b); +NOMIPS16 int test50 (v2sf a, v2sf b); +NOMIPS16 int test51 (v2sf a, v2sf b); +NOMIPS16 int test52 (v2sf a, v2sf b); +NOMIPS16 int test53 (v2sf a, v2sf b); +NOMIPS16 int test54 (v2sf a, v2sf b); +NOMIPS16 int test55 (v2sf a, v2sf b); +NOMIPS16 int test56 (v2sf a, v2sf b); +NOMIPS16 int test57 (v2sf a, v2sf b); +NOMIPS16 int test58 (v2sf a, v2sf b); +NOMIPS16 int test59 (v2sf a, v2sf b); +NOMIPS16 int test60 (v2sf a, v2sf b); +NOMIPS16 int test61 (v2sf a, v2sf b); +NOMIPS16 int test62 (v2sf a, v2sf b); +NOMIPS16 int test63 (v2sf a, v2sf b); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + int little_endian; + v2sf a, b, c, d; + int i, j, k, l; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + /* cabs.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {-56, -78}; + i = 0; + j = 0; + k = 0; + l = 0; + if (__builtin_mips_any_cabs_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_upper_cabs_eq_ps(a, b) != j) + abort (); + if (__builtin_mips_lower_cabs_eq_ps(a, b) != k) + abort (); + if (__builtin_mips_all_cabs_eq_ps(a, b) != l) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {-12, -78}; + i = 1; + if (little_endian) + { + j = 0; + k = 1; + } + else + { + j = 1; + k = 0; + } + l = 0; + if (__builtin_mips_any_cabs_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_upper_cabs_eq_ps(a, b) != j) + abort (); + if (__builtin_mips_lower_cabs_eq_ps(a, b) != k) + abort (); + if (__builtin_mips_all_cabs_eq_ps(a, b) != l) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {-56, -34}; + i = 1; + if (little_endian) + { + j = 1; + k = 0; + } + else + { + j = 0; + k = 1; + } + l = 0; + if (__builtin_mips_any_cabs_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_upper_cabs_eq_ps(a, b) != j) + abort (); + if (__builtin_mips_lower_cabs_eq_ps(a, b) != k) + abort (); + if (__builtin_mips_all_cabs_eq_ps(a, b) != l) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {12, 34}; + b = (v2sf) {-12, -34}; + i = 1; + j = 1; + k = 1; + l = 1; + if (__builtin_mips_any_cabs_eq_ps(a, b) != i) + abort (); + if (__builtin_mips_upper_cabs_eq_ps(a, b) != j) + abort (); + if (__builtin_mips_lower_cabs_eq_ps(a, b) != k) + abort (); + if (__builtin_mips_all_cabs_eq_ps(a, b) != l) + abort (); + + /* Test all comparisons */ + if (little_endian) + { + a = (v2sf) {1984.0, 10.58}; + b = (v2sf) {-1984.0, -567.345}; + } + else + { + a = (v2sf) {10.58, 1984.0}; + b = (v2sf) {-567.345, -1984.0}; + } + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 0) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 0) + abort (); + i = test6 (a, b); + if (i != 0) + abort (); + i = test7 (a, b); + if (i != 0) + abort (); + i = test8 (a, b); + if (i != 1) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 0) + abort (); + i = test12 (a, b); + if (i != 1) + abort (); + i = test13 (a, b); + if (i != 0) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 0) + abort (); + i = test16 (a, b); + if (i != 1) + abort (); + i = test17 (a, b); + if (i != 1) + abort (); + i = test18 (a, b); + if (i != 0) + abort (); + i = test19 (a, b); + if (i != 0) + abort (); + i = test20 (a, b); + if (i != 1) + abort (); + i = test21 (a, b); + if (i != 1) + abort (); + i = test22 (a, b); + if (i != 0) + abort (); + i = test23 (a, b); + if (i != 0) + abort (); + i = test24 (a, b); + if (i != 1) + abort (); + i = test25 (a, b); + if (i != 1) + abort (); + i = test26 (a, b); + if (i != 1) + abort (); + i = test27 (a, b); + if (i != 1) + abort (); + i = test28 (a, b); + if (i != 1) + abort (); + i = test29 (a, b); + if (i != 1) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); + i = test32 (a, b); + if (i != 0) + abort (); + i = test33 (a, b); + if (i != 0) + abort (); + i = test34 (a, b); + if (i != 0) + abort (); + i = test35 (a, b); + if (i != 0) + abort (); + i = test36 (a, b); + if (i != 0) + abort (); + i = test37 (a, b); + if (i != 0) + abort (); + i = test38 (a, b); + if (i != 0) + abort (); + i = test39 (a, b); + if (i != 0) + abort (); + i = test40 (a, b); + if (i != 1) + abort (); + i = test41 (a, b); + if (i != 0) + abort (); + i = test42 (a, b); + if (i != 1) + abort (); + i = test43 (a, b); + if (i != 0) + abort (); + i = test44 (a, b); + if (i != 1) + abort (); + i = test45 (a, b); + if (i != 0) + abort (); + i = test46 (a, b); + if (i != 1) + abort (); + i = test47 (a, b); + if (i != 0) + abort (); + i = test48 (a, b); + if (i != 1) + abort (); + i = test49 (a, b); + if (i != 1) + abort (); + i = test50 (a, b); + if (i != 0) + abort (); + i = test51 (a, b); + if (i != 0) + abort (); + i = test52 (a, b); + if (i != 1) + abort (); + i = test53 (a, b); + if (i != 1) + abort (); + i = test54 (a, b); + if (i != 0) + abort (); + i = test55 (a, b); + if (i != 0) + abort (); + i = test56 (a, b); + if (i != 1) + abort (); + i = test57 (a, b); + if (i != 1) + abort (); + i = test58 (a, b); + if (i != 1) + abort (); + i = test59 (a, b); + if (i != 1) + abort (); + i = test60 (a, b); + if (i != 1) + abort (); + i = test61 (a, b); + if (i != 1) + abort (); + i = test62 (a, b); + if (i != 1) + abort (); + i = test63 (a, b); + if (i != 1) + abort (); + + /* Reverse arguments */ + i = test0 (b, a); + if (i != 0) + abort (); + i = test1 (b, a); + if (i != 0) + abort (); + i = test2 (b, a); + if (i != 0) + abort (); + i = test3 (b, a); + if (i != 0) + abort (); + i = test4 (b, a); + if (i != 0) + abort (); + i = test5 (b, a); + if (i != 0) + abort (); + i = test6 (b, a); + if (i != 0) + abort (); + i = test7 (b, a); + if (i != 0) + abort (); + i = test8 (b, a); + if (i != 1) + abort (); + i = test9 (b, a); + if (i != 0) + abort (); + i = test10 (b, a); + if (i != 1) + abort (); + i = test11 (b, a); + if (i != 0) + abort (); + i = test12 (b, a); + if (i != 1) + abort (); + i = test13 (b, a); + if (i != 0) + abort (); + i = test14 (b, a); + if (i != 1) + abort (); + i = test15 (b, a); + if (i != 0) + abort (); + i = test16 (b, a); + if (i != 0) + abort (); + i = test17 (b, a); + if (i != 0) + abort (); + i = test18 (b, a); + if (i != 0) + abort (); + i = test19 (b, a); + if (i != 0) + abort (); + i = test20 (b, a); + if (i != 0) + abort (); + i = test21 (b, a); + if (i != 0) + abort (); + i = test22 (b, a); + if (i != 0) + abort (); + i = test23 (b, a); + if (i != 0) + abort (); + i = test24 (b, a); + if (i != 1) + abort (); + i = test25 (b, a); + if (i != 0) + abort (); + i = test26 (b, a); + if (i != 1) + abort (); + i = test27 (b, a); + if (i != 0) + abort (); + i = test28 (b, a); + if (i != 1) + abort (); + i = test29 (b, a); + if (i != 0) + abort (); + i = test30 (b, a); + if (i != 1) + abort (); + i = test31 (b, a); + if (i != 0) + abort (); + i = test32 (b, a); + if (i != 0) + abort (); + i = test33 (b, a); + if (i != 0) + abort (); + i = test34 (b, a); + if (i != 0) + abort (); + i = test35 (b, a); + if (i != 0) + abort (); + i = test36 (b, a); + if (i != 0) + abort (); + i = test37 (b, a); + if (i != 0) + abort (); + i = test38 (b, a); + if (i != 0) + abort (); + i = test39 (b, a); + if (i != 0) + abort (); + i = test40 (b, a); + if (i != 1) + abort (); + i = test41 (b, a); + if (i != 0) + abort (); + i = test42 (b, a); + if (i != 1) + abort (); + i = test43 (b, a); + if (i != 0) + abort (); + i = test44 (b, a); + if (i != 1) + abort (); + i = test45 (b, a); + if (i != 0) + abort (); + i = test46 (b, a); + if (i != 1) + abort (); + i = test47 (b, a); + if (i != 0) + abort (); + i = test48 (b, a); + if (i != 0) + abort (); + i = test49 (b, a); + if (i != 0) + abort (); + i = test50 (b, a); + if (i != 0) + abort (); + i = test51 (b, a); + if (i != 0) + abort (); + i = test52 (b, a); + if (i != 0) + abort (); + i = test53 (b, a); + if (i != 0) + abort (); + i = test54 (b, a); + if (i != 0) + abort (); + i = test55 (b, a); + if (i != 0) + abort (); + i = test56 (b, a); + if (i != 1) + abort (); + i = test57 (b, a); + if (i != 0) + abort (); + i = test58 (b, a); + if (i != 1) + abort (); + i = test59 (b, a); + if (i != 0) + abort (); + i = test60 (b, a); + if (i != 1) + abort (); + i = test61 (b, a); + if (i != 0) + abort (); + i = test62 (b, a); + if (i != 1) + abort (); + i = test63 (b, a); + if (i != 0) + abort (); + +#ifndef __FAST_MATH__ + /* Test all comparisons */ + if (little_endian) + { + a = (v2sf) {qnan, qnan}; + b = (v2sf) {-1984.0, -567.345}; + } + else + { + a = (v2sf) {qnan, qnan}; + b = (v2sf) {-567.345, -1984.0}; + } + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 0) + abort (); + i = test4 (a, b); + if (i != 1) + abort (); + i = test5 (a, b); + if (i != 1) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 0) + abort (); + i = test11 (a, b); + if (i != 0) + abort (); + i = test12 (a, b); + if (i != 1) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + i = test16 (a, b); + if (i != 0) + abort (); + i = test17 (a, b); + if (i != 0) + abort (); + i = test18 (a, b); + if (i != 0) + abort (); + i = test19 (a, b); + if (i != 0) + abort (); + i = test20 (a, b); + if (i != 1) + abort (); + i = test21 (a, b); + if (i != 1) + abort (); + i = test22 (a, b); + if (i != 1) + abort (); + i = test23 (a, b); + if (i != 1) + abort (); + i = test24 (a, b); + if (i != 0) + abort (); + i = test25 (a, b); + if (i != 0) + abort (); + i = test26 (a, b); + if (i != 0) + abort (); + i = test27 (a, b); + if (i != 0) + abort (); + i = test28 (a, b); + if (i != 1) + abort (); + i = test29 (a, b); + if (i != 1) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); + i = test32 (a, b); + if (i != 0) + abort (); + i = test33 (a, b); + if (i != 0) + abort (); + i = test34 (a, b); + if (i != 0) + abort (); + i = test35 (a, b); + if (i != 0) + abort (); + i = test36 (a, b); + if (i != 1) + abort (); + i = test37 (a, b); + if (i != 1) + abort (); + i = test38 (a, b); + if (i != 1) + abort (); + i = test39 (a, b); + if (i != 1) + abort (); + i = test40 (a, b); + if (i != 0) + abort (); + i = test41 (a, b); + if (i != 0) + abort (); + i = test42 (a, b); + if (i != 0) + abort (); + i = test43 (a, b); + if (i != 0) + abort (); + i = test44 (a, b); + if (i != 1) + abort (); + i = test45 (a, b); + if (i != 1) + abort (); + i = test46 (a, b); + if (i != 1) + abort (); + i = test47 (a, b); + if (i != 1) + abort (); + i = test48 (a, b); + if (i != 0) + abort (); + i = test49 (a, b); + if (i != 0) + abort (); + i = test50 (a, b); + if (i != 0) + abort (); + i = test51 (a, b); + if (i != 0) + abort (); + i = test52 (a, b); + if (i != 1) + abort (); + i = test53 (a, b); + if (i != 1) + abort (); + i = test54 (a, b); + if (i != 1) + abort (); + i = test55 (a, b); + if (i != 1) + abort (); + i = test56 (a, b); + if (i != 0) + abort (); + i = test57 (a, b); + if (i != 0) + abort (); + i = test58 (a, b); + if (i != 0) + abort (); + i = test59 (a, b); + if (i != 0) + abort (); + i = test60 (a, b); + if (i != 1) + abort (); + i = test61 (a, b); + if (i != 1) + abort (); + i = test62 (a, b); + if (i != 1) + abort (); + i = test63 (a, b); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_f_ps (a, b); +} + +NOMIPS16 int test1 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_f_ps (a, b); +} + +NOMIPS16 int test2 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_f_ps (a, b); +} + +NOMIPS16 int test3 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_f_ps (a, b); +} + +NOMIPS16 int test4 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_un_ps (a, b); +} + +NOMIPS16 int test5 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_un_ps (a, b); +} + +NOMIPS16 int test6 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_un_ps (a, b); +} + +NOMIPS16 int test7 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_un_ps (a, b); +} + +NOMIPS16 int test8 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_eq_ps (a, b); +} + +NOMIPS16 int test9 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_eq_ps (a, b); +} + +NOMIPS16 int test10 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_eq_ps (a, b); +} + +NOMIPS16 int test11 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_eq_ps (a, b); +} + +NOMIPS16 int test12 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ueq_ps (a, b); +} + +NOMIPS16 int test13 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ueq_ps (a, b); +} + +NOMIPS16 int test14 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ueq_ps (a, b); +} + +NOMIPS16 int test15 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ueq_ps (a, b); +} + +NOMIPS16 int test16 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_olt_ps (a, b); +} + +NOMIPS16 int test17 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_olt_ps (a, b); +} + +NOMIPS16 int test18 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_olt_ps (a, b); +} + +NOMIPS16 int test19 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_olt_ps (a, b); +} + +NOMIPS16 int test20 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ult_ps (a, b); +} + +NOMIPS16 int test21 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ult_ps (a, b); +} + +NOMIPS16 int test22 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ult_ps (a, b); +} + +NOMIPS16 int test23 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ult_ps (a, b); +} + +NOMIPS16 int test24 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ole_ps (a, b); +} + +NOMIPS16 int test25 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ole_ps (a, b); +} + +NOMIPS16 int test26 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ole_ps (a, b); +} + +NOMIPS16 int test27 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ole_ps (a, b); +} + +NOMIPS16 int test28 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ule_ps (a, b); +} + +NOMIPS16 int test29 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ule_ps (a, b); +} + +NOMIPS16 int test30 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ule_ps (a, b); +} + +NOMIPS16 int test31 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ule_ps (a, b); +} + +NOMIPS16 int test32 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_sf_ps (a, b); +} + +NOMIPS16 int test33 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_sf_ps (a, b); +} + +NOMIPS16 int test34 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_sf_ps (a, b); +} + +NOMIPS16 int test35 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_sf_ps (a, b); +} + +NOMIPS16 int test36 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ngle_ps (a, b); +} + +NOMIPS16 int test37 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ngle_ps (a, b); +} + +NOMIPS16 int test38 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ngle_ps (a, b); +} + +NOMIPS16 int test39 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ngle_ps (a, b); +} + +NOMIPS16 int test40 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_seq_ps (a, b); +} + +NOMIPS16 int test41 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_seq_ps (a, b); +} + +NOMIPS16 int test42 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_seq_ps (a, b); +} + +NOMIPS16 int test43 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_seq_ps (a, b); +} + +NOMIPS16 int test44 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ngl_ps (a, b); +} + +NOMIPS16 int test45 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ngl_ps (a, b); +} + +NOMIPS16 int test46 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ngl_ps (a, b); +} + +NOMIPS16 int test47 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ngl_ps (a, b); +} + +NOMIPS16 int test48 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_lt_ps (a, b); +} + +NOMIPS16 int test49 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_lt_ps (a, b); +} + +NOMIPS16 int test50 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_lt_ps (a, b); +} + +NOMIPS16 int test51 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_lt_ps (a, b); +} + +NOMIPS16 int test52 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_nge_ps (a, b); +} + +NOMIPS16 int test53 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_nge_ps (a, b); +} + +NOMIPS16 int test54 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_nge_ps (a, b); +} + +NOMIPS16 int test55 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_nge_ps (a, b); +} + +NOMIPS16 int test56 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_le_ps (a, b); +} + +NOMIPS16 int test57 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_le_ps (a, b); +} + +NOMIPS16 int test58 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_le_ps (a, b); +} + +NOMIPS16 int test59 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_le_ps (a, b); +} + +NOMIPS16 int test60 (v2sf a, v2sf b) +{ + return __builtin_mips_any_cabs_ngt_ps (a, b); +} + +NOMIPS16 int test61 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_cabs_ngt_ps (a, b); +} + +NOMIPS16 int test62 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_cabs_ngt_ps (a, b); +} + +NOMIPS16 int test63 (v2sf a, v2sf b) +{ + return __builtin_mips_all_cabs_ngt_ps (a, b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c new file mode 100644 index 000000000..3d28d7f2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c @@ -0,0 +1,590 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D branch-if-any-four builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + v2sf a, b, c, d; + int i, j; + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {33, 44}; + c = (v2sf) {55, 66}; + d = (v2sf) {77, 88}; + i = 0; + j = 0; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {11, 44}; + c = (v2sf) {55, 66}; + d = (v2sf) {77, 88}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {33, 22}; + c = (v2sf) {55, 66}; + d = (v2sf) {77, 88}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {33, 44}; + c = (v2sf) {55, 66}; + d = (v2sf) {55, 88}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {33, 44}; + c = (v2sf) {55, 66}; + d = (v2sf) {77, 66}; + i = 1; + j = 0; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* c.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {11, 22}; + c = (v2sf) {55, 66}; + d = (v2sf) {55, 66}; + i = 1; + j = 1; + if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j) + abort (); + + /* Test all comparisons */ + a = (v2sf) {11, 33}; + b = (v2sf) {33, 11}; + c = (v2sf) {55, 66}; + d = (v2sf) {55, 88}; + + i = test0 (a, b, c, d); + if (i != 0) + abort (); + i = test1 (a, b, c, d); + if (i != 0) + abort (); + i = test2 (a, b, c, d); + if (i != 0) + abort (); + i = test3 (a, b, c, d); + if (i != 0) + abort (); + i = test4 (a, b, c, d); + if (i != 1) + abort (); + i = test5 (a, b, c, d); + if (i != 0) + abort (); + i = test6 (a, b, c, d); + if (i != 1) + abort (); + i = test7 (a, b, c, d); + if (i != 0) + abort (); + i = test8 (a, b, c, d); + if (i != 1) + abort (); + i = test9 (a, b, c, d); + if (i != 0) + abort (); + i = test10 (a, b, c, d); + if (i != 1) + abort (); + i = test11 (a, b, c, d); + if (i != 0) + abort (); + i = test12 (a, b, c, d); + if (i != 1) + abort (); + i = test13 (a, b, c, d); + if (i != 0) + abort (); + i = test14 (a, b, c, d); + if (i != 1) + abort (); + i = test15 (a, b, c, d); + if (i != 0) + abort (); + i = test16 (a, b, c, d); + if (i != 0) + abort (); + i = test17 (a, b, c, d); + if (i != 0) + abort (); + i = test18 (a, b, c, d); + if (i != 0) + abort (); + i = test19 (a, b, c, d); + if (i != 0) + abort (); + i = test20 (a, b, c, d); + if (i != 1) + abort (); + i = test21 (a, b, c, d); + if (i != 0) + abort (); + i = test22 (a, b, c, d); + if (i != 1) + abort (); + i = test23 (a, b, c, d); + if (i != 0) + abort (); + i = test24 (a, b, c, d); + if (i != 1) + abort (); + i = test25 (a, b, c, d); + if (i != 0) + abort (); + i = test26 (a, b, c, d); + if (i != 1) + abort (); + i = test27 (a, b, c, d); + if (i != 0) + abort (); + i = test28 (a, b, c, d); + if (i != 1) + abort (); + i = test29 (a, b, c, d); + if (i != 0) + abort (); + i = test30 (a, b, c, d); + if (i != 1) + abort (); + i = test31 (a, b, c, d); + if (i != 0) + abort (); + + /* Reversed arguments */ + i = test0 (b, a, d, c); + if (i != 0) + abort (); + i = test1 (b, a, d, c); + if (i != 0) + abort (); + i = test2 (b, a, d, c); + if (i != 0) + abort (); + i = test3 (b, a, d, c); + if (i != 0) + abort (); + i = test4 (b, a, d, c); + if (i != 1) + abort (); + i = test5 (b, a, d, c); + if (i != 0) + abort (); + i = test6 (b, a, d, c); + if (i != 1) + abort (); + i = test7 (b, a, d, c); + if (i != 0) + abort (); + i = test8 (b, a, d, c); + if (i != 1) + abort (); + i = test9 (b, a, d, c); + if (i != 0) + abort (); + i = test10 (b, a, d, c); + if (i != 1) + abort (); + i = test11 (b, a, d, c); + if (i != 0) + abort (); + i = test12 (b, a, d, c); + if (i != 1) + abort (); + i = test13 (b, a, d, c); + if (i != 0) + abort (); + i = test14 (b, a, d, c); + if (i != 1) + abort (); + i = test15 (b, a, d, c); + if (i != 0) + abort (); + i = test16 (b, a, d, c); + if (i != 0) + abort (); + i = test17 (b, a, d, c); + if (i != 0) + abort (); + i = test18 (b, a, d, c); + if (i != 0) + abort (); + i = test19 (b, a, d, c); + if (i != 0) + abort (); + i = test20 (b, a, d, c); + if (i != 1) + abort (); + i = test21 (b, a, d, c); + if (i != 0) + abort (); + i = test22 (b, a, d, c); + if (i != 1) + abort (); + i = test23 (b, a, d, c); + if (i != 0) + abort (); + i = test24 (b, a, d, c); + if (i != 1) + abort (); + i = test25 (b, a, d, c); + if (i != 0) + abort (); + i = test26 (b, a, d, c); + if (i != 1) + abort (); + i = test27 (b, a, d, c); + if (i != 0) + abort (); + i = test28 (b, a, d, c); + if (i != 1) + abort (); + i = test29 (b, a, d, c); + if (i != 0) + abort (); + i = test30 (b, a, d, c); + if (i != 1) + abort (); + i = test31 (b, a, d, c); + if (i != 0) + abort (); + +#ifndef __FAST_MATH__ + /* Test all comparisons */ + a = (v2sf) {qnan, qnan}; + b = (v2sf) {33, 11}; + c = (v2sf) {qnan, qnan}; + d = (v2sf) {55, 88}; + + i = test0 (a, b, c, d); + if (i != 0) + abort (); + i = test1 (a, b, c, d); + if (i != 0) + abort (); + i = test2 (a, b, c, d); + if (i != 1) + abort (); + i = test3 (a, b, c, d); + if (i != 1) + abort (); + i = test4 (a, b, c, d); + if (i != 0) + abort (); + i = test5 (a, b, c, d); + if (i != 0) + abort (); + i = test6 (a, b, c, d); + if (i != 1) + abort (); + i = test7 (a, b, c, d); + if (i != 1) + abort (); + i = test8 (a, b, c, d); + if (i != 0) + abort (); + i = test9 (a, b, c, d); + if (i != 0) + abort (); + i = test10 (a, b, c, d); + if (i != 1) + abort (); + i = test11 (a, b, c, d); + if (i != 1) + abort (); + i = test12 (a, b, c, d); + if (i != 0) + abort (); + i = test13 (a, b, c, d); + if (i != 0) + abort (); + i = test14 (a, b, c, d); + if (i != 1) + abort (); + i = test15 (a, b, c, d); + if (i != 1) + abort (); + i = test16 (a, b, c, d); + if (i != 0) + abort (); + i = test17 (a, b, c, d); + if (i != 0) + abort (); + i = test18 (a, b, c, d); + if (i != 1) + abort (); + i = test19 (a, b, c, d); + if (i != 1) + abort (); + i = test20 (a, b, c, d); + if (i != 0) + abort (); + i = test21 (a, b, c, d); + if (i != 0) + abort (); + i = test22 (a, b, c, d); + if (i != 1) + abort (); + i = test23 (a, b, c, d); + if (i != 1) + abort (); + i = test24 (a, b, c, d); + if (i != 0) + abort (); + i = test25 (a, b, c, d); + if (i != 0) + abort (); + i = test26 (a, b, c, d); + if (i != 1) + abort (); + i = test27 (a, b, c, d); + if (i != 1) + abort (); + i = test28 (a, b, c, d); + if (i != 0) + abort (); + i = test29 (a, b, c, d); + if (i != 0) + abort (); + i = test30 (a, b, c, d); + if (i != 1) + abort (); + i = test31 (a, b, c, d); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_f_4s (a, b, c, d); +} + +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_f_4s (a, b, c, d); +} + +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_un_4s (a, b, c, d); +} + +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_un_4s (a, b, c, d); +} + +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_eq_4s (a, b, c, d); +} + +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_eq_4s (a, b, c, d); +} + +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ueq_4s (a, b, c, d); +} + +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ueq_4s (a, b, c, d); +} + +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_olt_4s (a, b, c, d); +} + +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_olt_4s (a, b, c, d); +} + +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ult_4s (a, b, c, d); +} + +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ult_4s (a, b, c, d); +} + +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ole_4s (a, b, c, d); +} + +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ole_4s (a, b, c, d); +} + +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ule_4s (a, b, c, d); +} + +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ule_4s (a, b, c, d); +} + +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_sf_4s (a, b, c, d); +} + +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_sf_4s (a, b, c, d); +} + +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ngle_4s (a, b, c, d); +} + +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ngle_4s (a, b, c, d); +} + +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_seq_4s (a, b, c, d); +} + +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_seq_4s (a, b, c, d); +} + +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ngl_4s (a, b, c, d); +} + +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ngl_4s (a, b, c, d); +} + +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_lt_4s (a, b, c, d); +} + +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_lt_4s (a, b, c, d); +} + +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_nge_4s (a, b, c, d); +} + +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_nge_4s (a, b, c, d); +} + +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_le_4s (a, b, c, d); +} + +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_le_4s (a, b, c, d); +} + +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_c_ngt_4s (a, b, c, d); +} + +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_c_ngt_4s (a, b, c, d); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c new file mode 100644 index 000000000..a433675ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c @@ -0,0 +1,590 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D absolute-compare & branch-if-any-four builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + v2sf a, b, c, d; + int i, j; + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-33, -44}; + c = (v2sf) {55, 66}; + d = (v2sf) {-77, -88}; + i = 0; + j = 0; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-11, -44}; + c = (v2sf) {55, 66}; + d = (v2sf) {-77, -88}; + i = 1; + j = 0; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-33, -22}; + c = (v2sf) {55, 66}; + d = (v2sf) {-77, -88}; + i = 1; + j = 0; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-33, -44}; + c = (v2sf) {55, 66}; + d = (v2sf) {-55, -88}; + i = 1; + j = 0; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-33, -44}; + c = (v2sf) {55, 66}; + d = (v2sf) {-77, -66}; + i = 1; + j = 0; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* cabs.eq.ps */ + a = (v2sf) {11, 22}; + b = (v2sf) {-11, -22}; + c = (v2sf) {55, 66}; + d = (v2sf) {-55, -66}; + i = 1; + j = 1; + if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i) + abort (); + if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j) + abort (); + + /* Test all comparisons */ + a = (v2sf) {11, 33}; + b = (v2sf) {-33, -11}; + c = (v2sf) {55, 66}; + d = (v2sf) {-55, -88}; + + i = test0 (a, b, c, d); + if (i != 0) + abort (); + i = test1 (a, b, c, d); + if (i != 0) + abort (); + i = test2 (a, b, c, d); + if (i != 0) + abort (); + i = test3 (a, b, c, d); + if (i != 0) + abort (); + i = test4 (a, b, c, d); + if (i != 1) + abort (); + i = test5 (a, b, c, d); + if (i != 0) + abort (); + i = test6 (a, b, c, d); + if (i != 1) + abort (); + i = test7 (a, b, c, d); + if (i != 0) + abort (); + i = test8 (a, b, c, d); + if (i != 1) + abort (); + i = test9 (a, b, c, d); + if (i != 0) + abort (); + i = test10 (a, b, c, d); + if (i != 1) + abort (); + i = test11 (a, b, c, d); + if (i != 0) + abort (); + i = test12 (a, b, c, d); + if (i != 1) + abort (); + i = test13 (a, b, c, d); + if (i != 0) + abort (); + i = test14 (a, b, c, d); + if (i != 1) + abort (); + i = test15 (a, b, c, d); + if (i != 0) + abort (); + i = test16 (a, b, c, d); + if (i != 0) + abort (); + i = test17 (a, b, c, d); + if (i != 0) + abort (); + i = test18 (a, b, c, d); + if (i != 0) + abort (); + i = test19 (a, b, c, d); + if (i != 0) + abort (); + i = test20 (a, b, c, d); + if (i != 1) + abort (); + i = test21 (a, b, c, d); + if (i != 0) + abort (); + i = test22 (a, b, c, d); + if (i != 1) + abort (); + i = test23 (a, b, c, d); + if (i != 0) + abort (); + i = test24 (a, b, c, d); + if (i != 1) + abort (); + i = test25 (a, b, c, d); + if (i != 0) + abort (); + i = test26 (a, b, c, d); + if (i != 1) + abort (); + i = test27 (a, b, c, d); + if (i != 0) + abort (); + i = test28 (a, b, c, d); + if (i != 1) + abort (); + i = test29 (a, b, c, d); + if (i != 0) + abort (); + i = test30 (a, b, c, d); + if (i != 1) + abort (); + i = test31 (a, b, c, d); + if (i != 0) + abort (); + + /* Reversed arguments */ + i = test0 (b, a, d, c); + if (i != 0) + abort (); + i = test1 (b, a, d, c); + if (i != 0) + abort (); + i = test2 (b, a, d, c); + if (i != 0) + abort (); + i = test3 (b, a, d, c); + if (i != 0) + abort (); + i = test4 (b, a, d, c); + if (i != 1) + abort (); + i = test5 (b, a, d, c); + if (i != 0) + abort (); + i = test6 (b, a, d, c); + if (i != 1) + abort (); + i = test7 (b, a, d, c); + if (i != 0) + abort (); + i = test8 (b, a, d, c); + if (i != 1) + abort (); + i = test9 (b, a, d, c); + if (i != 0) + abort (); + i = test10 (b, a, d, c); + if (i != 1) + abort (); + i = test11 (b, a, d, c); + if (i != 0) + abort (); + i = test12 (b, a, d, c); + if (i != 1) + abort (); + i = test13 (b, a, d, c); + if (i != 0) + abort (); + i = test14 (b, a, d, c); + if (i != 1) + abort (); + i = test15 (b, a, d, c); + if (i != 0) + abort (); + i = test16 (b, a, d, c); + if (i != 0) + abort (); + i = test17 (b, a, d, c); + if (i != 0) + abort (); + i = test18 (b, a, d, c); + if (i != 0) + abort (); + i = test19 (b, a, d, c); + if (i != 0) + abort (); + i = test20 (b, a, d, c); + if (i != 1) + abort (); + i = test21 (b, a, d, c); + if (i != 0) + abort (); + i = test22 (b, a, d, c); + if (i != 1) + abort (); + i = test23 (b, a, d, c); + if (i != 0) + abort (); + i = test24 (b, a, d, c); + if (i != 1) + abort (); + i = test25 (b, a, d, c); + if (i != 0) + abort (); + i = test26 (b, a, d, c); + if (i != 1) + abort (); + i = test27 (b, a, d, c); + if (i != 0) + abort (); + i = test28 (b, a, d, c); + if (i != 1) + abort (); + i = test29 (b, a, d, c); + if (i != 0) + abort (); + i = test30 (b, a, d, c); + if (i != 1) + abort (); + i = test31 (b, a, d, c); + if (i != 0) + abort (); + +#ifndef __FAST_MATH__ + /* Test all comparisons */ + a = (v2sf) {qnan, qnan}; + b = (v2sf) {-33, -11}; + c = (v2sf) {qnan, qnan}; + d = (v2sf) {-55, -88}; + + i = test0 (a, b, c, d); + if (i != 0) + abort (); + i = test1 (a, b, c, d); + if (i != 0) + abort (); + i = test2 (a, b, c, d); + if (i != 1) + abort (); + i = test3 (a, b, c, d); + if (i != 1) + abort (); + i = test4 (a, b, c, d); + if (i != 0) + abort (); + i = test5 (a, b, c, d); + if (i != 0) + abort (); + i = test6 (a, b, c, d); + if (i != 1) + abort (); + i = test7 (a, b, c, d); + if (i != 1) + abort (); + i = test8 (a, b, c, d); + if (i != 0) + abort (); + i = test9 (a, b, c, d); + if (i != 0) + abort (); + i = test10 (a, b, c, d); + if (i != 1) + abort (); + i = test11 (a, b, c, d); + if (i != 1) + abort (); + i = test12 (a, b, c, d); + if (i != 0) + abort (); + i = test13 (a, b, c, d); + if (i != 0) + abort (); + i = test14 (a, b, c, d); + if (i != 1) + abort (); + i = test15 (a, b, c, d); + if (i != 1) + abort (); + i = test16 (a, b, c, d); + if (i != 0) + abort (); + i = test17 (a, b, c, d); + if (i != 0) + abort (); + i = test18 (a, b, c, d); + if (i != 1) + abort (); + i = test19 (a, b, c, d); + if (i != 1) + abort (); + i = test20 (a, b, c, d); + if (i != 0) + abort (); + i = test21 (a, b, c, d); + if (i != 0) + abort (); + i = test22 (a, b, c, d); + if (i != 1) + abort (); + i = test23 (a, b, c, d); + if (i != 1) + abort (); + i = test24 (a, b, c, d); + if (i != 0) + abort (); + i = test25 (a, b, c, d); + if (i != 0) + abort (); + i = test26 (a, b, c, d); + if (i != 1) + abort (); + i = test27 (a, b, c, d); + if (i != 1) + abort (); + i = test28 (a, b, c, d); + if (i != 0) + abort (); + i = test29 (a, b, c, d); + if (i != 0) + abort (); + i = test30 (a, b, c, d); + if (i != 1) + abort (); + i = test31 (a, b, c, d); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_f_4s (a, b, c, d); +} + +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_f_4s (a, b, c, d); +} + +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_un_4s (a, b, c, d); +} + +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_un_4s (a, b, c, d); +} + +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_eq_4s (a, b, c, d); +} + +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_eq_4s (a, b, c, d); +} + +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ueq_4s (a, b, c, d); +} + +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ueq_4s (a, b, c, d); +} + +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_olt_4s (a, b, c, d); +} + +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_olt_4s (a, b, c, d); +} + +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ult_4s (a, b, c, d); +} + +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ult_4s (a, b, c, d); +} + +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ole_4s (a, b, c, d); +} + +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ole_4s (a, b, c, d); +} + +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ule_4s (a, b, c, d); +} + +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ule_4s (a, b, c, d); +} + +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_sf_4s (a, b, c, d); +} + +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_sf_4s (a, b, c, d); +} + +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ngle_4s (a, b, c, d); +} + +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ngle_4s (a, b, c, d); +} + +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_seq_4s (a, b, c, d); +} + +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_seq_4s (a, b, c, d); +} + +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ngl_4s (a, b, c, d); +} + +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ngl_4s (a, b, c, d); +} + +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_lt_4s (a, b, c, d); +} + +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_lt_4s (a, b, c, d); +} + +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_nge_4s (a, b, c, d); +} + +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_nge_4s (a, b, c, d); +} + +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_le_4s (a, b, c, d); +} + +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_le_4s (a, b, c, d); +} + +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_any_cabs_ngt_4s (a, b, c, d); +} + +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_all_cabs_ngt_4s (a, b, c, d); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c new file mode 100644 index 000000000..e6b44f075 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c @@ -0,0 +1,284 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D absolute compare (floats) builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +NOMIPS16 int test0 (float a, float b); +NOMIPS16 int test1 (float a, float b); +NOMIPS16 int test2 (float a, float b); +NOMIPS16 int test3 (float a, float b); +NOMIPS16 int test4 (float a, float b); +NOMIPS16 int test5 (float a, float b); +NOMIPS16 int test6 (float a, float b); +NOMIPS16 int test7 (float a, float b); +NOMIPS16 int test8 (float a, float b); +NOMIPS16 int test9 (float a, float b); +NOMIPS16 int test10 (float a, float b); +NOMIPS16 int test11 (float a, float b); +NOMIPS16 int test12 (float a, float b); +NOMIPS16 int test13 (float a, float b); +NOMIPS16 int test14 (float a, float b); +NOMIPS16 int test15 (float a, float b); + +NOMIPS16 int main () +{ + float a, b; + int i; + + /* cabs.eq.s */ + a = 12; + b = -56; + i = 0; + if (__builtin_mips_cabs_eq_s(a, b) != i) + abort (); + + /* cabs.eq.s */ + a = 12; + b = -12; + i = 1; + if (__builtin_mips_cabs_eq_s(a, b) != i) + abort (); + + /* Test all comparisons */ + a = 10.58; + b = 567.345; + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 0) + abort (); + i = test4 (a, b); + if (i != 1) + abort (); + i = test5 (a, b); + if (i != 1) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 0) + abort (); + i = test11 (a, b); + if (i != 0) + abort (); + i = test12 (a, b); + if (i != 1) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + + /* Reversed arguments */ + i = test0 (b, a); + if (i != 0) + abort (); + i = test1 (b, a); + if (i != 0) + abort (); + i = test2 (b, a); + if (i != 0) + abort (); + i = test3 (b, a); + if (i != 0) + abort (); + i = test4 (b, a); + if (i != 0) + abort (); + i = test5 (b, a); + if (i != 0) + abort (); + i = test6 (b, a); + if (i != 0) + abort (); + i = test7 (b, a); + if (i != 0) + abort (); + i = test8 (b, a); + if (i != 0) + abort (); + i = test9 (b, a); + if (i != 0) + abort (); + i = test10 (b, a); + if (i != 0) + abort (); + i = test11 (b, a); + if (i != 0) + abort (); + i = test12 (b, a); + if (i != 0) + abort (); + i = test13 (b, a); + if (i != 0) + abort (); + i = test14 (b, a); + if (i != 0) + abort (); + i = test15 (b, a); + if (i != 0) + abort (); + +#ifndef __FAST_MATH__ + /* Test all comparisons */ + a = 1.0f/0.0f - 1.0f/0.0f; // QNaN + b = 567.345; + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 1) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 1) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 1) + abort (); + i = test6 (a, b); + if (i != 0) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 1) + abort (); + i = test10 (a, b); + if (i != 0) + abort (); + i = test11 (a, b); + if (i != 1) + abort (); + i = test12 (a, b); + if (i != 0) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 0) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (float a, float b) +{ + return __builtin_mips_cabs_f_s (a, b); +} + +NOMIPS16 int test1 (float a, float b) +{ + return __builtin_mips_cabs_un_s (a, b); +} + +NOMIPS16 int test2 (float a, float b) +{ + return __builtin_mips_cabs_eq_s (a, b); +} + +NOMIPS16 int test3 (float a, float b) +{ + return __builtin_mips_cabs_ueq_s (a, b); +} + +NOMIPS16 int test4 (float a, float b) +{ + return __builtin_mips_cabs_olt_s (a, b); +} + +NOMIPS16 int test5 (float a, float b) +{ + return __builtin_mips_cabs_ult_s (a, b); +} + +NOMIPS16 int test6 (float a, float b) +{ + return __builtin_mips_cabs_ole_s (a, b); +} + +NOMIPS16 int test7 (float a, float b) +{ + return __builtin_mips_cabs_ule_s (a, b); +} + +NOMIPS16 int test8 (float a, float b) +{ + return __builtin_mips_cabs_sf_s (a, b); +} + +NOMIPS16 int test9 (float a, float b) +{ + return __builtin_mips_cabs_ngle_s (a, b); +} + +NOMIPS16 int test10 (float a, float b) +{ + return __builtin_mips_cabs_seq_s (a, b); +} + +NOMIPS16 int test11 (float a, float b) +{ + return __builtin_mips_cabs_ngl_s (a, b); +} + +NOMIPS16 int test12 (float a, float b) +{ + return __builtin_mips_cabs_lt_s (a, b); +} + +NOMIPS16 int test13 (float a, float b) +{ + return __builtin_mips_cabs_nge_s (a, b); +} + +NOMIPS16 int test14 (float a, float b) +{ + return __builtin_mips_cabs_le_s (a, b); +} + +NOMIPS16 int test15 (float a, float b) +{ + return __builtin_mips_cabs_ngt_s (a, b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c new file mode 100644 index 000000000..2531ddf8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c @@ -0,0 +1,284 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D absolute compare (doubles) builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +NOMIPS16 int test0 (double a, double b); +NOMIPS16 int test1 (double a, double b); +NOMIPS16 int test2 (double a, double b); +NOMIPS16 int test3 (double a, double b); +NOMIPS16 int test4 (double a, double b); +NOMIPS16 int test5 (double a, double b); +NOMIPS16 int test6 (double a, double b); +NOMIPS16 int test7 (double a, double b); +NOMIPS16 int test8 (double a, double b); +NOMIPS16 int test9 (double a, double b); +NOMIPS16 int test10 (double a, double b); +NOMIPS16 int test11 (double a, double b); +NOMIPS16 int test12 (double a, double b); +NOMIPS16 int test13 (double a, double b); +NOMIPS16 int test14 (double a, double b); +NOMIPS16 int test15 (double a, double b); + +NOMIPS16 int main () +{ + double a, b; + int i; + + /* cabs.eq.d */ + a = 12; + b = -56; + i = 0; + if (__builtin_mips_cabs_eq_d(a, b) != i) + abort (); + + /* cabs.eq.d */ + a = 12; + b = -12; + i = 1; + if (__builtin_mips_cabs_eq_d(a, b) != i) + abort (); + + /* Test all operators */ + a = 1984.0; + b = 1984.0; + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 1) + abort (); + i = test3 (a, b); + if (i != 1) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 0) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 1) + abort (); + i = test12 (a, b); + if (i != 0) + abort (); + i = test13 (a, b); + if (i != 0) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + + /* Reverse arguments */ + i = test0 (b, a); + if (i != 0) + abort (); + i = test1 (b, a); + if (i != 0) + abort (); + i = test2 (b, a); + if (i != 1) + abort (); + i = test3 (b, a); + if (i != 1) + abort (); + i = test4 (b, a); + if (i != 0) + abort (); + i = test5 (b, a); + if (i != 0) + abort (); + i = test6 (b, a); + if (i != 1) + abort (); + i = test7 (b, a); + if (i != 1) + abort (); + i = test8 (b, a); + if (i != 0) + abort (); + i = test9 (b, a); + if (i != 0) + abort (); + i = test10 (b, a); + if (i != 1) + abort (); + i = test11 (b, a); + if (i != 1) + abort (); + i = test12 (b, a); + if (i != 0) + abort (); + i = test13 (b, a); + if (i != 0) + abort (); + i = test14 (b, a); + if (i != 1) + abort (); + i = test15 (b, a); + if (i != 1) + abort (); + +#ifndef __FAST_MATH__ + /* Test all operators */ + a = 1.0/0.0 - 1.0/0.0; // QNaN + b = 1.0/0.0 - 1.0/0.0; // QNaN + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 1) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 1) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 1) + abort (); + i = test6 (a, b); + if (i != 0) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 1) + abort (); + i = test10 (a, b); + if (i != 0) + abort (); + i = test11 (a, b); + if (i != 1) + abort (); + i = test12 (a, b); + if (i != 0) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 0) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (double a, double b) +{ + return __builtin_mips_cabs_f_d (a, b); +} + +NOMIPS16 int test1 (double a, double b) +{ + return __builtin_mips_cabs_un_d (a, b); +} + +NOMIPS16 int test2 (double a, double b) +{ + return __builtin_mips_cabs_eq_d (a, b); +} + +NOMIPS16 int test3 (double a, double b) +{ + return __builtin_mips_cabs_ueq_d (a, b); +} + +NOMIPS16 int test4 (double a, double b) +{ + return __builtin_mips_cabs_olt_d (a, b); +} + +NOMIPS16 int test5 (double a, double b) +{ + return __builtin_mips_cabs_ult_d (a, b); +} + +NOMIPS16 int test6 (double a, double b) +{ + return __builtin_mips_cabs_ole_d (a, b); +} + +NOMIPS16 int test7 (double a, double b) +{ + return __builtin_mips_cabs_ule_d (a, b); +} + +NOMIPS16 int test8 (double a, double b) +{ + return __builtin_mips_cabs_sf_d (a, b); +} + +NOMIPS16 int test9 (double a, double b) +{ + return __builtin_mips_cabs_ngle_d (a, b); +} + +NOMIPS16 int test10 (double a, double b) +{ + return __builtin_mips_cabs_seq_d (a, b); +} + +NOMIPS16 int test11 (double a, double b) +{ + return __builtin_mips_cabs_ngl_d (a, b); +} + +NOMIPS16 int test12 (double a, double b) +{ + return __builtin_mips_cabs_lt_d (a, b); +} + +NOMIPS16 int test13 (double a, double b) +{ + return __builtin_mips_cabs_nge_d (a, b); +} + +NOMIPS16 int test14 (double a, double b) +{ + return __builtin_mips_cabs_le_d (a, b); +} + +NOMIPS16 int test15 (double a, double b) +{ + return __builtin_mips_cabs_ngt_d (a, b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c new file mode 100644 index 000000000..1d199d7d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c @@ -0,0 +1,630 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Test MIPS-3D absolute compare and conditional move builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__((vector_size(8))); + +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + v2sf a, b, c, d, e, f; + + /* Case 1 {diff, diff} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {-7, -6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d); + f = (v2sf) {33, 123}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d); + f = (v2sf) {8, 78}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* Case 2 {same, diff} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {-5, -6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d); + f = (v2sf) {8, 123}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d); + f = (v2sf) {33, 78}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* Case 3 {diff, same} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {-9, -12}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d); + f = (v2sf) {33, 78}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d); + f = (v2sf) {8, 123}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* Case 4 {same, same} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {-5, -12}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d); + f = (v2sf) {8, 78}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d); + f = (v2sf) {33, 123}; + if (!__builtin_mips_all_c_eq_ps (e, f)) + abort (); + + /* Test all 16 operators */ + a = (v2sf) {-123, 123}; + b = (v2sf) {1000, -1000}; + c = (v2sf) {-33, 123}; + d = (v2sf) {8, -78}; + + e = test0 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test1 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test2 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test3 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test4 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test5 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test6 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test7 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test8 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test9 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test10 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test11 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test12 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test13 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test14 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test15 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test16 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test17 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test18 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test19 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test20 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test21 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test22 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test23 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test24 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test25 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test26 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test27 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test28 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test29 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test30 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test31 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + /* Reversed arguments */ + e = test0 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test1 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test2 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test3 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test4 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test5 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test6 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test7 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test8 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test9 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test10 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test11 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test12 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test13 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test14 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test15 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test16 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test17 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test18 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test19 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test20 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test21 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test22 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test23 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test24 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test25 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test26 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test27 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test28 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test29 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test30 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test31 (b, a, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + +#ifndef __FAST_MATH__ + /* Test all 16 operators */ + a = (v2sf) {qnan, qnan}; + b = (v2sf) {1000, -1000}; + c = (v2sf) {8, -78}; + d = (v2sf) {-33, 123}; + + e = test0 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test1 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test2 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test3 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test4 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test5 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test6 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test7 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test8 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test9 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test10 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test11 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test12 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test13 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test14 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test15 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test16 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test17 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test18 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test19 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test20 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test21 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test22 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test23 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test24 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test25 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test26 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test27 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + + e = test28 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); + e = test29 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + + e = test30 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, d)) + abort (); + e = test31 (a, b, c, d); + if (!__builtin_mips_all_c_eq_ps (e, c)) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_f_ps (a, b, c, d); +} + +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_f_ps (a, b, c, d); +} + +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_un_ps (a, b, c, d); +} + +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_un_ps (a, b, c, d); +} + +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_eq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_eq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ueq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ueq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_olt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_olt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ult_ps (a, b, c, d); +} + +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ult_ps (a, b, c, d); +} + +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ole_ps (a, b, c, d); +} + +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ole_ps (a, b, c, d); +} + +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ule_ps (a, b, c, d); +} + +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ule_ps (a, b, c, d); +} + +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_sf_ps (a, b, c, d); +} + +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_sf_ps (a, b, c, d); +} + +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ngle_ps (a, b, c, d); +} + +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ngle_ps (a, b, c, d); +} + +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_seq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_seq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ngl_ps (a, b, c, d); +} + +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ngl_ps (a, b, c, d); +} + +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_lt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_lt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_nge_ps (a, b, c, d); +} + +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_nge_ps (a, b, c, d); +} + +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_le_ps (a, b, c, d); +} + +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_le_ps (a, b, c, d); +} + +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_cabs_ngt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_cabs_ngt_ps (a, b, c, d); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c new file mode 100644 index 000000000..d697efded --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c @@ -0,0 +1,158 @@ +/* { dg-do run } */ +/* { dg-options "-mips3d" } */ + +/* Matrix Multiplications */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__((vector_size(8))); + +float a[4] = {1.1, 2.2, 3.3, 4.4}; +float b[4][4] = {{1, 2, 3, 4}, + {5, 6, 7, 8}, + {9, 10, 11, 12}, + {13, 14, 15, 16}}; + +float c[4]; /* Result for matrix_multiply1() */ +float d[4]; /* Result for matrix_multiply2() */ +float e[4]; /* Result for matrix_multiply3() */ +float f[4]; /* Result for matrix_multiply4() */ + +void matrix_multiply1(); +NOMIPS16 void matrix_multiply2(); +NOMIPS16 void matrix_multiply3(); +NOMIPS16 void matrix_multiply4(); + +int main () +{ + int i; + + /* Version 1. Use float calculations */ + matrix_multiply1(); + + /* Version 2. Use paired-single instructions inside the inner loop*/ + matrix_multiply2(); + for (i = 0; i < 4; i++) + if (d[i] != c[i]) + abort(); + + /* Version 3. Use paired-single instructions and unroll the inner loop */ + matrix_multiply3(); + for (i = 0; i < 4; i++) + if (e[i] != c[i]) + abort(); + + /* Version 4. Use paired-single instructions and unroll all loops */ + matrix_multiply4(); + for (i = 0; i < 4; i++) + if (f[i] != c[i]) + abort(); + + printf ("Test Passes\n"); + exit (0); +} + +void matrix_multiply1() +{ + int i, j; + + for (i = 0; i < 4; i++) + { + c[i] = 0.0; + + for (j = 0; j < 4; j ++) + c[i] += a[j] * b[j][i]; + } +} + +NOMIPS16 void matrix_multiply2() +{ + int i, j; + v2sf m1, m2; + v2sf result, temp; + + for (i = 0; i < 4; i++) + { + result = (v2sf) {0.0, 0.0}; + + for (j = 0; j < 4; j+=2) + { + /* Load two float values into m1 */ + m1 = (v2sf) {a[j], a[j+1]}; + m2 = (v2sf) {b[j][i], b[j+1][i]}; + + /* Multiply and add */ + result += m1 * m2; + } + + /* Reduction add at the end */ + temp = __builtin_mips_addr_ps (result, result); + d[i] = __builtin_mips_cvt_s_pl (temp); + } +} + +NOMIPS16 void matrix_multiply3() +{ + int i; + v2sf m1, m2, n1, n2; + v2sf result, temp; + + m1 = (v2sf) {a[0], a[1]}; + m2 = (v2sf) {a[2], a[3]}; + + for (i = 0; i < 4; i++) + { + n1 = (v2sf) {b[0][i], b[1][i]}; + n2 = (v2sf) {b[2][i], b[3][i]}; + + /* Multiply and add */ + result = m1 * n1 + m2 * n2; + + /* Reduction add at the end */ + temp = __builtin_mips_addr_ps (result, result); + e[i] = __builtin_mips_cvt_s_pl (temp); + } +} + +NOMIPS16 void matrix_multiply4() +{ + v2sf m1, m2; + v2sf n1, n2, n3, n4, n5, n6, n7, n8; + v2sf temp1, temp2, temp3, temp4; + v2sf result1, result2; + + /* Load a[0] a[1] values into m1 + Load a[2] a[3] values into m2 */ + m1 = (v2sf) {a[0], a[1]}; + m2 = (v2sf) {a[2], a[3]}; + + /* Load b[0][0] b[1][0] values into n1 + Load b[2][0] b[3][0] values into n2 + Load b[0][1] b[1][1] values into n3 + Load b[2][1] b[3][1] values into n4 + Load b[0][2] b[1][2] values into n5 + Load b[2][2] b[3][2] values into n6 + Load b[0][3] b[1][3] values into n7 + Load b[2][3] b[3][3] values into n8 */ + n1 = (v2sf) {b[0][0], b[1][0]}; + n2 = (v2sf) {b[2][0], b[3][0]}; + n3 = (v2sf) {b[0][1], b[1][1]}; + n4 = (v2sf) {b[2][1], b[3][1]}; + n5 = (v2sf) {b[0][2], b[1][2]}; + n6 = (v2sf) {b[2][2], b[3][2]}; + n7 = (v2sf) {b[0][3], b[1][3]}; + n8 = (v2sf) {b[2][3], b[3][3]}; + + temp1 = m1 * n1 + m2 * n2; + temp2 = m1 * n3 + m2 * n4; + temp3 = m1 * n5 + m2 * n6; + temp4 = m1 * n7 + m2 * n8; + + result1 = __builtin_mips_addr_ps (temp1, temp2); + result2 = __builtin_mips_addr_ps (temp3, temp4); + + f[0] = __builtin_mips_cvt_s_pu (result1); + f[1] = __builtin_mips_cvt_s_pl (result1); + f[2] = __builtin_mips_cvt_s_pu (result2); + f[3] = __builtin_mips_cvt_s_pl (result2); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README new file mode 100644 index 000000000..b7a46e4b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README @@ -0,0 +1,27 @@ +These tests are meant to test the interoperability of PIC and nonpic objects for mips. +This table shows the various combinations and each case is tested by one of the nonpic tests. +Test Case The PIC code The non-PIC code The result (stub and/or PLT) + +main-1.c nothing nothing Neither (trivial) +main-2.c nothing call only PLT entry +main-3.c nothing address taken only Neither (* But creating a PLT entry is valid) +main-4.c nothing address and call PLT entry +main-5.c call only nothing .MIPS.stubs entry +main-6.c call only call only .MIPS.stubs and PLT +main-7.c call only address taken only .MIPS.stubs (* Also creating a PLT entry is valid) +main-8.c call only address and call .MIPS.stubs and PLT entry +main-9.c address taken only nothing Neither +main-10.c address taken only call only PLT entry +main-11.c address taken only address taken only Neither (* But creating a PLT entry is valid) +main-12.c address taken only address and call PLT entry +main-13.c address and call nothing Neither +main-14.c address and call call only PLT entry +main-15.c address and call address taken only Neither (* But creating a PLT entry is valid) +main-16.c address and call address and call PLT entry + + +Copyright (C) 2008-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c new file mode 100644 index 000000000..2f428717a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-nothing.o nonpic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_nothing (); + pic_nothing (); + + if (hit_nonpic_nothing != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c new file mode 100644 index 000000000..6c3601861 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c @@ -0,0 +1,18 @@ +/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_call (); + pic_addr (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_addr != 2) + abort (); + + exit (0); + +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c new file mode 100644 index 000000000..1d8a6d20c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr (); + pic_addr (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_addr != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c new file mode 100644 index 000000000..f57b5ce17 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-addr-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr_call (); + pic_addr (); + + if (hit_nonpic_addr_call != 1) + abort (); + + if (hit_pic_addr != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c new file mode 100644 index 000000000..d2b88e1f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_nothing (); + pic_addr_call (); + + if (hit_nonpic_nothing != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c new file mode 100644 index 000000000..6318a2240 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_call (); + pic_addr_call (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c new file mode 100644 index 000000000..1c165043a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr (); + pic_addr_call (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c new file mode 100644 index 000000000..3119979d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-addr-call.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o pic-nothing.o nonpic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr_call (); + pic_addr_call (); + + if (hit_nonpic_addr_call != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c new file mode 100644 index 000000000..8a66e7a7a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-addr.o nonpic-call.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_call (); + pic_nothing (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_nothing != 2) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c new file mode 100644 index 000000000..c9c8dac70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c @@ -0,0 +1,17 @@ +/* { dg-options "nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr (); + pic_nothing (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c new file mode 100644 index 000000000..c10c213ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-addr-call.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_addr_call (); + pic_nothing (); + + if (hit_nonpic_addr_call != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c new file mode 100644 index 000000000..9b6dd8aff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-addr.o pic-call.o nonpic-addr.o pic-receive-fn-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + nonpic_nothing (); + pic_call (); + + if (hit_nonpic_nothing != 2) + abort (); + + if (hit_pic_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c new file mode 100644 index 000000000..90b220f0f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-call.o nonpic-call.o nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + pic_call (); + nonpic_call (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c new file mode 100644 index 000000000..8cef63f3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-call.o nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + pic_call (); + nonpic_addr (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_addr != 2) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c new file mode 100644 index 000000000..0200bf2dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c @@ -0,0 +1,17 @@ +/* { dg-options "pic-call.o nonpic-addr-call.o nonpic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + pic_call (); + nonpic_addr_call (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_addr_call != 1) + abort (); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c new file mode 100644 index 000000000..4144172cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c @@ -0,0 +1,10 @@ +/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +#include "mips-nonpic.h" + +main () +{ + pic_addr (); + nonpic_nothing (); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp new file mode 100644 index 000000000..d99b3d183 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp @@ -0,0 +1,54 @@ +# Copyright (C) 2008-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. +load_lib gcc-dg.exp +load_lib target-supports.exp + +# Exit immediately if this isn't a MIPS target. +if ![istarget mips*-*-*] { + return +} + +# Pic and nonpic are not link-compatible for VXWorks targets. +if [istarget mips*-*-vxworks] { + return +} + +if { ![check_effective_target_fpic] } { + return +} + +dg-init + +set old-dg-do-what-default "${dg-do-what-default}" +set dg-do-what-default "assemble" + +foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/pic-*.c]] { + verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]" + dg-test -keep-output $testcase "-fpic" "" +} + +foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/nonpic-*.c]] { + verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]" + dg-test -keep-output $testcase "-fno-pic" "" +} + +set dg-do-what-default "run" +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/main-*.c]] "-fno-pic" "" + +set dg-do-what-default "${old-dg-do-what-default}" +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h new file mode 100644 index 000000000..e9fe99218 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h @@ -0,0 +1,20 @@ +extern int hit_pic_addr; +extern int hit_pic_addr_call; +extern int hit_pic_nothing; +extern int hit_pic_call; + +extern int hit_nonpic_addr; +extern int hit_nonpic_addr_call; +extern int hit_nonpic_call; +extern int hit_nonpic_nothing; + +extern void nonpic_addr (void); +extern void nonpic_nothing (void); +extern void nonpic_receive_fn_addr (void *); + +extern void pic_addr (void); +extern void pic_receive_fn_addr (void *); +extern void pic_nothing (void); + +extern void abort (void); +extern void exit (int); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c new file mode 100644 index 000000000..19d0e4349 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c @@ -0,0 +1,8 @@ +#include "mips-nonpic.h" +int hit_nonpic_addr_call = 0; +void +nonpic_addr_call (void) +{ + hit_nonpic_addr_call++; + pic_receive_fn_addr (&pic_nothing); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c new file mode 100644 index 000000000..c919e83b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c @@ -0,0 +1,8 @@ +#include "mips-nonpic.h" +int hit_nonpic_addr = 0; +void +nonpic_addr () +{ + nonpic_receive_fn_addr (&nonpic_nothing); + hit_nonpic_addr++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c new file mode 100644 index 000000000..8d368b42e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c @@ -0,0 +1,9 @@ +#include "mips-nonpic.h" +int hit_nonpic_call = 0; +void +nonpic_call () +{ + pic_nothing (); + pic_addr (); + hit_nonpic_call++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c new file mode 100644 index 000000000..90356fb24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c @@ -0,0 +1,7 @@ +#include "mips-nonpic.h" +int hit_nonpic_nothing = 0; +void +nonpic_nothing () +{ + hit_nonpic_nothing++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c new file mode 100644 index 000000000..8b548c9ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c @@ -0,0 +1,7 @@ +#include "mips-nonpic.h" +void +nonpic_receive_fn_addr (void *x) +{ + if (x != &nonpic_nothing) + abort (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c new file mode 100644 index 000000000..2db729392 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c @@ -0,0 +1,8 @@ +#include "mips-nonpic.h" +int hit_pic_addr_call = 0; +void +pic_addr_call (void) +{ + hit_pic_addr_call++; + nonpic_receive_fn_addr (&nonpic_nothing); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c new file mode 100644 index 000000000..a90739235 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c @@ -0,0 +1,8 @@ +#include "mips-nonpic.h" +int hit_pic_addr = 0; +void +pic_addr () +{ + pic_receive_fn_addr (&pic_nothing); + hit_pic_addr++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c new file mode 100644 index 000000000..0c73b9333 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c @@ -0,0 +1,9 @@ +#include "mips-nonpic.h" +int hit_pic_call = 0; +void +pic_call () +{ + nonpic_nothing (); + nonpic_addr (); + hit_pic_call++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c new file mode 100644 index 000000000..3e4539081 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c @@ -0,0 +1,7 @@ +#include "mips-nonpic.h" +int hit_pic_nothing = 0; +void +pic_nothing () +{ + hit_pic_nothing++; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c new file mode 100644 index 000000000..4a40e0a18 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c @@ -0,0 +1,7 @@ +#include "mips-nonpic.h" +void +pic_receive_fn_addr (void *x) +{ + if (x != &pic_nothing) + abort (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c new file mode 100644 index 000000000..126dbebcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c @@ -0,0 +1,8 @@ +/* { dg-options "-mdspr2" } */ +/* { dg-final { scan-assembler "prepend\[^\n\]*,10" } } */ + +NOMIPS16 int +foo (int x, int y) +{ + return __builtin_mips_prepend (x, y, 42); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c new file mode 100644 index 000000000..73598a840 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c @@ -0,0 +1,271 @@ +/* { dg-do run } */ +/* { dg-options "-mpaired-single" } */ + +/* Test v2sf calculations */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size (8))); + +v2sf A = {100, 200}; + +/* Init from float */ +v2sf init (float a, float b) +{ + return (v2sf) {a, b}; +} + +/* Move between registers */ +v2sf move (v2sf a) +{ + return a; +} + +/* Load from memory */ +v2sf load () +{ + return A; +} + +/* Store to memory */ +void store (v2sf a) +{ + A = a; +} + +/* Add */ +v2sf add (v2sf a, v2sf b) +{ + return a + b; +} + +/* Subtract */ +v2sf sub (v2sf a, v2sf b) +{ + return a - b; +} + +/* Negate */ +v2sf neg (v2sf a) +{ + return - a; +} + +/* Multiply */ +v2sf mul (v2sf a, v2sf b) +{ + return a * b; +} + +/* Multiply and add */ +v2sf madd (v2sf a, v2sf b, v2sf c) +{ + return a * b + c; +} + +/* Multiply and subtract */ +v2sf msub (v2sf a, v2sf b, v2sf c) +{ + return a * b - c; +} + +/* Negate Multiply and add */ +v2sf nmadd (v2sf a, v2sf b, v2sf c) +{ + return - (a * b + c); +} + +/* Negate Multiply and subtract */ +v2sf nmsub (v2sf a, v2sf b, v2sf c) +{ + return - (a * b - c); +} + +/* Conditional Move */ +v2sf cond_move1 (v2sf a, v2sf b, long i) +{ + if (i > 0) + return a; + else + return b; +} + +/* Conditional Move */ +v2sf cond_move2 (v2sf a, v2sf b, int i) +{ + if (i > 0) + return a; + else + return b; +} + +/* Conditional Move */ +v2sf cond_move3 (v2sf a, v2sf b, float i) +{ + if (i > 0.0) + return a; + else + return b; +} + +/* Conditional Move */ +v2sf cond_move4 (v2sf a, v2sf b, double i) +{ + if (i > 0.0) + return a; + else + return b; +} + +NOMIPS16 int main() +{ + v2sf a, b, c, d, e, f; + float f1, f2; + + f1 = 1.2; + f2 = 3.4; + a = init (f1, f2); + b = (v2sf) {1.2, 3.4}; + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + a = (v2sf) {1.2, 2.3}; + b = (v2sf) {5.3, 6.1}; + b = move (a); + + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + a = (v2sf) {1.2, 2.3}; + b = (v2sf) {5.3, 6.1}; + c = add (a, b); + d = (v2sf) {6.5, 8.4}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = sub (a, b); + d = (v2sf) {-4, 6}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = mul (a, b); + d = (v2sf) {5, 72}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {5, 6}; + d = madd (a, b, c); + e = (v2sf) {10, 78}; + if (!__builtin_mips_upper_c_eq_ps (d, e) || + !__builtin_mips_lower_c_eq_ps (d, e)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {5, 6}; + d = msub (a, b, c); + e = (v2sf) {0, 66}; + if (!__builtin_mips_upper_c_eq_ps (d, e) || + !__builtin_mips_lower_c_eq_ps (d, e)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {5, 6}; + d = nmadd (a, b, c); + e = (v2sf) {-10, -78}; + if (!__builtin_mips_upper_c_eq_ps (d, e) || + !__builtin_mips_lower_c_eq_ps (d, e)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {5, 6}; + d = nmsub (a, b, c); + e = (v2sf) {0, -66}; + if (!__builtin_mips_upper_c_eq_ps (d, e) || + !__builtin_mips_lower_c_eq_ps (d, e)) + abort (); + + a = (v2sf) {98, 12}; + b = neg (a); + c = (v2sf) {-98, -12}; + if (!__builtin_mips_upper_c_eq_ps (b, c) || + !__builtin_mips_lower_c_eq_ps (b, c)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = cond_move1 (a, b, 1000); + if (!__builtin_mips_upper_c_eq_ps (c, a) || + !__builtin_mips_lower_c_eq_ps (c, a)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = cond_move2 (a, b, -1000); + if (!__builtin_mips_upper_c_eq_ps (c, b) || + !__builtin_mips_lower_c_eq_ps (c, b)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = cond_move3 (a, b, 9.0); + if (!__builtin_mips_upper_c_eq_ps (c, a) || + !__builtin_mips_lower_c_eq_ps (c, a)) + abort (); + + a = (v2sf) {1, 12}; + b = (v2sf) {5, 6}; + c = cond_move4 (a, b, -10.0); + if (!__builtin_mips_upper_c_eq_ps (c, b) || + !__builtin_mips_lower_c_eq_ps (c, b)) + abort (); + + a = (v2sf) {5, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_c_eq_ps (a, b, c, d); + f = (v2sf) {8, 123}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + a = (v2sf) {5, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movf_c_eq_ps (a, b, c, d); + f = (v2sf) {33, 78}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + a = load(); + b = (v2sf) {100, 200}; + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + a = (v2sf) {123, 321}; + store (a); + b = load(); + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + printf ("Test Passes\n"); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c new file mode 100644 index 000000000..526425586 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c @@ -0,0 +1,134 @@ +/* { dg-do run } */ +/* { dg-options "-mpaired-single" } */ + +/* Test MIPS paired-single builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int main () +{ + int little_endian; + v2sf a, b, c, d; + float e,f; + int i; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + /* pll.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_pll_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {3, 1}; + else // big endian + d = (v2sf) {2, 4}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* pul.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_pul_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {3, 2}; + else // big endian + d = (v2sf) {1, 4}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* plu.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_plu_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {4, 1}; + else // big endian + d = (v2sf) {2, 3}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* puu.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_puu_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {4, 2}; + else // big endian + d = (v2sf) {1, 3}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* cvt.ps.s */ + e = 3.4; + f = 4.5; + a = __builtin_mips_cvt_ps_s (e, f); + if (little_endian) // little endian + b = (v2sf) {4.5, 3.4}; + else // big endian + b = (v2sf) {3.4, 4.5}; + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + /* cvt.s.pl */ + a = (v2sf) {35.1, 120.2}; + e = __builtin_mips_cvt_s_pl (a); + if (little_endian) // little endian + f = 35.1; + else // big endian + f = 120.2; + if (e != f) + abort (); + + /* cvt.s.pu */ + a = (v2sf) {30.0, 100.0}; + e = __builtin_mips_cvt_s_pu (a); + if (little_endian) // little endian + f = 100.0; + else // big endian + f = 30.0; + if (e != f) + abort (); + + /* abs.ps */ + a = (v2sf) {-3.4, -5.8}; + b = __builtin_mips_abs_ps (a); + c = (v2sf) {3.4, 5.8}; + if (!__builtin_mips_upper_c_eq_ps (b, c) || + !__builtin_mips_lower_c_eq_ps (b, c)) + abort (); + + /* alnv.ps with rs = 4*/ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + i = 4; + c = __builtin_mips_alnv_ps (a, b, i); + d = (v2sf) {2, 3}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* alnv.ps with rs = 0 */ + a = (v2sf) {5, 6}; + b = (v2sf) {7, 8}; + i = 0; + c = __builtin_mips_alnv_ps (a, b, i); + d = (v2sf) {5, 6}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + printf ("Test Passes\n"); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c new file mode 100644 index 000000000..7e6ffd066 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c @@ -0,0 +1,737 @@ +/* { dg-do run } */ +/* { dg-options "-mpaired-single" } */ + +/* Test MIPS paired-single conditional move */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__((vector_size(8))); + +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main () +{ + float f1; + v2sf a, b, c, d, e, f; + + /* Case 1 {diff, diff} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {9, 6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_c_eq_ps (a, b, c, d); + f = (v2sf) {33, 123}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_c_eq_ps (a, b, c, d); + f = (v2sf) {8, 78}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* Case 2 {same, diff} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {5, 6}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_c_eq_ps (a, b, c, d); + f = (v2sf) {8, 123}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_c_eq_ps (a, b, c, d); + f = (v2sf) {33, 78}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* Case 3 {diff, same} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {9, 12}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_c_eq_ps (a, b, c, d); + f = (v2sf) {33, 78}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_c_eq_ps (a, b, c, d); + f = (v2sf) {8, 123}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* Case 4 {same, same} */ + /* movt.ps */ + a = (v2sf) {5, 12}; + b = (v2sf) {5, 12}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = __builtin_mips_movt_c_eq_ps (a, b, c, d); + f = (v2sf) {8, 78}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* movf.ps */ + e = __builtin_mips_movf_c_eq_ps (a, b, c, d); + f = (v2sf) {33, 123}; + if (!__builtin_mips_upper_c_eq_ps (e, f) || + !__builtin_mips_lower_c_eq_ps (e, f)) + abort (); + + /* Test all 16 operators */ + a = (v2sf) {123, 123}; + b = (v2sf) {1000, 1000}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = test0 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test1 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test2 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test3 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test4 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test5 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test6 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test7 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test8 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test9 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test10 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test11 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test12 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test13 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test14 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test15 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test16 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test17 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test18 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test19 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test20 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test21 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test22 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test23 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test24 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test25 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test26 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test27 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test28 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test29 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test30 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test31 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + /* Test all 16 operators with (b, a) */ + a = (v2sf) {123, 123}; + b = (v2sf) {1000, 1000}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = test0 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test1 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test2 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test3 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test4 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test5 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test6 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test7 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test8 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test9 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test10 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test11 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test12 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test13 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test14 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test15 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test16 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test17 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test18 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test19 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test20 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test21 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test22 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test23 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test24 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test25 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test26 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test27 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test28 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test29 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test30 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test31 (b, a, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + +#ifndef __FAST_MATH__ + /* Test with NaN */ + a = (v2sf) {qnan, qnan}; + b = (v2sf) {1000, 1000}; + c = (v2sf) {33, 123}; + d = (v2sf) {8, 78}; + e = test0 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test1 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test2 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test3 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test4 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test5 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test6 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test7 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test8 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test9 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test10 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test11 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test12 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test13 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test14 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test15 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test16 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test17 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test18 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test19 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test20 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test21 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test22 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test23 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test24 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test25 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test26 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test27 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + + e = test28 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); + e = test29 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + + e = test30 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, d) || + !__builtin_mips_lower_c_eq_ps (e, d)) + abort (); + e = test31 (a, b, c, d); + if (!__builtin_mips_upper_c_eq_ps (e, c) || + !__builtin_mips_lower_c_eq_ps (e, c)) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_f_ps (a, b, c, d); +} + +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_f_ps (a, b, c, d); +} + +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_un_ps (a, b, c, d); +} + +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_un_ps (a, b, c, d); +} + +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_eq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_eq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ueq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ueq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_olt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_olt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ult_ps (a, b, c, d); +} + +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ult_ps (a, b, c, d); +} + +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ole_ps (a, b, c, d); +} + +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ole_ps (a, b, c, d); +} + +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ule_ps (a, b, c, d); +} + +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ule_ps (a, b, c, d); +} + +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_sf_ps (a, b, c, d); +} + +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_sf_ps (a, b, c, d); +} + +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ngle_ps (a, b, c, d); +} + +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ngle_ps (a, b, c, d); +} + +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_seq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_seq_ps (a, b, c, d); +} + +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ngl_ps (a, b, c, d); +} + +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ngl_ps (a, b, c, d); +} + +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_lt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_lt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_nge_ps (a, b, c, d); +} + +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_nge_ps (a, b, c, d); +} + +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_le_ps (a, b, c, d); +} + +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_le_ps (a, b, c, d); +} + +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movt_c_ngt_ps (a, b, c, d); +} + +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) +{ + return __builtin_mips_movf_c_ngt_ps (a, b, c, d); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c new file mode 100644 index 000000000..06850adb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c @@ -0,0 +1,583 @@ +/* { dg-do run } */ +/* { dg-options "-mpaired-single" } */ + +/* Test MIPS paired-single comparisons */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__((vector_size(8))); + +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); + +float qnan = 1.0f/0.0f - 1.0f/0.0f; + +NOMIPS16 int main() +{ + union { long long ll; int i[2]; } endianness_test; + int little_endian; + v2sf a, b; + int i, j; + + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + /* Case 1 {diff, diff} */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + i = __builtin_mips_upper_c_eq_ps (a, b); + j = __builtin_mips_lower_c_eq_ps (a, b); + if (i != 0 || j != 0) + abort (); + + /* Case 2 {same, diff} */ + a = (v2sf) {1.0, 2.0}; + b = (v2sf) {1.0, 4.0}; + i = __builtin_mips_upper_c_eq_ps (a, b); + j = __builtin_mips_lower_c_eq_ps (a, b); + if (little_endian) + { + if (i != 0 || j != 1) + abort (); + } + else + { + if (i != 1 || j != 0) + abort (); + } + + /* Case 3 {diff, same} */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 2}; + i = __builtin_mips_upper_c_eq_ps (a, b); + j = __builtin_mips_lower_c_eq_ps (a, b); + if (little_endian) + { + if (i != 1 || j != 0) + abort (); + } + else + { + if (i != 0 || j != 1) + abort (); + } + + /* Case 4 {same, same} */ + a = (v2sf) {1, 2}; + b = (v2sf) {1, 2}; + i = __builtin_mips_upper_c_eq_ps (a, b); + j = __builtin_mips_lower_c_eq_ps (a, b); + if (i != 1 || j != 1) + abort (); + + /* Test upper/lower with 16 operators */ + if (little_endian) + { + a = (v2sf) {1984.0, 10.58}; + b = (v2sf) {1984.0, 567.345}; + } + else + { + a = (v2sf) {10.58, 1984.0}; + b = (v2sf) {567.345, 1984.0}; + } + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 0) + abort (); + i = test3 (a, b); + if (i != 0) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 1) + abort (); + i = test6 (a, b); + if (i != 0) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 1) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 0) + abort (); + i = test12 (a, b); + if (i != 1) + abort (); + i = test13 (a, b); + if (i != 1) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + i = test16 (a, b); + if (i != 0) + abort (); + i = test17 (a, b); + if (i != 0) + abort (); + i = test18 (a, b); + if (i != 0) + abort (); + i = test19 (a, b); + if (i != 0) + abort (); + i = test20 (a, b); + if (i != 0) + abort (); + i = test21 (a, b); + if (i != 1) + abort (); + i = test22 (a, b); + if (i != 0) + abort (); + i = test23 (a, b); + if (i != 1) + abort (); + i = test24 (a, b); + if (i != 1) + abort (); + i = test25 (a, b); + if (i != 0) + abort (); + i = test26 (a, b); + if (i != 1) + abort (); + i = test27 (a, b); + if (i != 0) + abort (); + i = test28 (a, b); + if (i != 1) + abort (); + i = test29 (a, b); + if (i != 1) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); + + /* Reverse arguments */ + i = test0 (b, a); + if (i != 0) + abort (); + i = test1 (b, a); + if (i != 0) + abort (); + i = test2 (b, a); + if (i != 0) + abort (); + i = test3 (b, a); + if (i != 0) + abort (); + i = test4 (b, a); + if (i != 0) + abort (); + i = test5 (b, a); + if (i != 1) + abort (); + i = test6 (b, a); + if (i != 0) + abort (); + i = test7 (b, a); + if (i != 1) + abort (); + i = test8 (b, a); + if (i != 0) + abort (); + i = test9 (b, a); + if (i != 0) + abort (); + i = test10 (b, a); + if (i != 0) + abort (); + i = test11 (b, a); + if (i != 0) + abort (); + i = test12 (b, a); + if (i != 0) + abort (); + i = test13 (b, a); + if (i != 1) + abort (); + i = test14 (b, a); + if (i != 0) + abort (); + i = test15 (b, a); + if (i != 1) + abort (); + i = test16 (b, a); + if (i != 0) + abort (); + i = test17 (b, a); + if (i != 0) + abort (); + i = test18 (b, a); + if (i != 0) + abort (); + i = test19 (b, a); + if (i != 0) + abort (); + i = test20 (b, a); + if (i != 0) + abort (); + i = test21 (b, a); + if (i != 1) + abort (); + i = test22 (b, a); + if (i != 0) + abort (); + i = test23 (b, a); + if (i != 1) + abort (); + i = test24 (b, a); + if (i != 0) + abort (); + i = test25 (b, a); + if (i != 0) + abort (); + i = test26 (b, a); + if (i != 0) + abort (); + i = test27 (b, a); + if (i != 0) + abort (); + i = test28 (b, a); + if (i != 0) + abort (); + i = test29 (b, a); + if (i != 1) + abort (); + i = test30 (b, a); + if (i != 0) + abort (); + i = test31 (b, a); + if (i != 1) + abort (); + +#ifndef __FAST_MATH__ + /* Test upper/lower with 16 operators */ + if (little_endian) + { + a = (v2sf) {qnan, qnan}; + b = (v2sf) {1984.0, 567.345}; + } + else + { + a = (v2sf) {qnan, qnan}; + b = (v2sf) {567.345, 1984.0}; + } + + i = test0 (a, b); + if (i != 0) + abort (); + i = test1 (a, b); + if (i != 0) + abort (); + i = test2 (a, b); + if (i != 1) + abort (); + i = test3 (a, b); + if (i != 1) + abort (); + i = test4 (a, b); + if (i != 0) + abort (); + i = test5 (a, b); + if (i != 0) + abort (); + i = test6 (a, b); + if (i != 1) + abort (); + i = test7 (a, b); + if (i != 1) + abort (); + i = test8 (a, b); + if (i != 0) + abort (); + i = test9 (a, b); + if (i != 0) + abort (); + i = test10 (a, b); + if (i != 1) + abort (); + i = test11 (a, b); + if (i != 1) + abort (); + i = test12 (a, b); + if (i != 0) + abort (); + i = test13 (a, b); + if (i != 0) + abort (); + i = test14 (a, b); + if (i != 1) + abort (); + i = test15 (a, b); + if (i != 1) + abort (); + i = test16 (a, b); + if (i != 0) + abort (); + i = test17 (a, b); + if (i != 0) + abort (); + i = test18 (a, b); + if (i != 1) + abort (); + i = test19 (a, b); + if (i != 1) + abort (); + i = test20 (a, b); + if (i != 0) + abort (); + i = test21 (a, b); + if (i != 0) + abort (); + i = test22 (a, b); + if (i != 1) + abort (); + i = test23 (a, b); + if (i != 1) + abort (); + i = test24 (a, b); + if (i != 0) + abort (); + i = test25 (a, b); + if (i != 0) + abort (); + i = test26 (a, b); + if (i != 1) + abort (); + i = test27 (a, b); + if (i != 1) + abort (); + i = test28 (a, b); + if (i != 0) + abort (); + i = test29 (a, b); + if (i != 0) + abort (); + i = test30 (a, b); + if (i != 1) + abort (); + i = test31 (a, b); + if (i != 1) + abort (); +#endif + + printf ("Test Passes\n"); + exit (0); +} + +NOMIPS16 int test0 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_f_ps (a, b); +} + +NOMIPS16 int test1 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_f_ps (a, b); +} + +NOMIPS16 int test2 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_un_ps (a, b); +} + +NOMIPS16 int test3 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_un_ps (a, b); +} + +NOMIPS16 int test4 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_eq_ps (a, b); +} + +NOMIPS16 int test5 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_eq_ps (a, b); +} + +NOMIPS16 int test6 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ueq_ps (a, b); +} + +NOMIPS16 int test7 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ueq_ps (a, b); +} + +NOMIPS16 int test8 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_olt_ps (a, b); +} + +NOMIPS16 int test9 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_olt_ps (a, b); +} + +NOMIPS16 int test10 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ult_ps (a, b); +} + +NOMIPS16 int test11 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ult_ps (a, b); +} + +NOMIPS16 int test12 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ole_ps (a, b); +} + +NOMIPS16 int test13 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ole_ps (a, b); +} + +NOMIPS16 int test14 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ule_ps (a, b); +} + +NOMIPS16 int test15 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ule_ps (a, b); +} + +NOMIPS16 int test16 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_sf_ps (a, b); +} + +NOMIPS16 int test17 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_sf_ps (a, b); +} + +NOMIPS16 int test18 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ngle_ps (a, b); +} + +NOMIPS16 int test19 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ngle_ps (a, b); +} + +NOMIPS16 int test20 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_seq_ps (a, b); +} + +NOMIPS16 int test21 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_seq_ps (a, b); +} + +NOMIPS16 int test22 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ngl_ps (a, b); +} + +NOMIPS16 int test23 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ngl_ps (a, b); +} + +NOMIPS16 int test24 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_lt_ps (a, b); +} + +NOMIPS16 int test25 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_lt_ps (a, b); +} + +NOMIPS16 int test26 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_nge_ps (a, b); +} + +NOMIPS16 int test27 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_nge_ps (a, b); +} + +NOMIPS16 int test28 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_le_ps (a, b); +} + +NOMIPS16 int test29 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_le_ps (a, b); +} + +NOMIPS16 int test30 (v2sf a, v2sf b) +{ + return __builtin_mips_upper_c_ngt_ps (a, b); +} + +NOMIPS16 int test31 (v2sf a, v2sf b) +{ + return __builtin_mips_lower_c_ngt_ps (a, b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c new file mode 100644 index 000000000..077076f47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mpaired-single -mgp64 -ftree-vectorize" } */ +/* { dg-skip-if "requires vectorization" { *-*-* } { "-O0" "-Os" } { "" } } */ + +extern float a[] __attribute__ ((aligned (8))); +extern float b[] __attribute__ ((aligned (8))); +extern float c[] __attribute__ ((aligned (8))); + +NOMIPS16 void +foo (void) +{ + int i; + for (i = 0; i < 16; i++) + a[i] = b[i] == c[i] + 1 ? b[i] : c[i]; +} + +/* { dg-final { scan-assembler "\tadd\\.ps\t" } } */ +/* { dg-final { scan-assembler "\tc\\.eq\\.ps\t" } } */ +/* { dg-final { scan-assembler "\tmov\[tf\]\\.ps\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c new file mode 100644 index 000000000..5bdfe436f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c @@ -0,0 +1,136 @@ +/* mips-ps-2.c with an extra -ffinite-math-only option. This option + changes the way that abs.ps is handled. */ +/* { dg-do run } */ +/* { dg-options "-mpaired-single -ffinite-math-only" } */ + +/* Test MIPS paired-single builtin functions */ +#include <stdlib.h> +#include <stdio.h> + +typedef float v2sf __attribute__ ((vector_size(8))); + +NOMIPS16 int main () +{ + int little_endian; + v2sf a, b, c, d; + float e,f; + int i; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + /* pll.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_pll_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {3, 1}; + else // big endian + d = (v2sf) {2, 4}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* pul.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_pul_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {3, 2}; + else // big endian + d = (v2sf) {1, 4}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* plu.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_plu_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {4, 1}; + else // big endian + d = (v2sf) {2, 3}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* puu.ps */ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + c = __builtin_mips_puu_ps (a, b); + if (little_endian) // little endian + d = (v2sf) {4, 2}; + else // big endian + d = (v2sf) {1, 3}; + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* cvt.ps.s */ + e = 3.4; + f = 4.5; + a = __builtin_mips_cvt_ps_s (e, f); + if (little_endian) // little endian + b = (v2sf) {4.5, 3.4}; + else // big endian + b = (v2sf) {3.4, 4.5}; + if (!__builtin_mips_upper_c_eq_ps (a, b) || + !__builtin_mips_lower_c_eq_ps (a, b)) + abort (); + + /* cvt.s.pl */ + a = (v2sf) {35.1, 120.2}; + e = __builtin_mips_cvt_s_pl (a); + if (little_endian) // little endian + f = 35.1; + else // big endian + f = 120.2; + if (e != f) + abort (); + + /* cvt.s.pu */ + a = (v2sf) {30.0, 100.0}; + e = __builtin_mips_cvt_s_pu (a); + if (little_endian) // little endian + f = 100.0; + else // big endian + f = 30.0; + if (e != f) + abort (); + + /* abs.ps */ + a = (v2sf) {-3.4, -5.8}; + b = __builtin_mips_abs_ps (a); + c = (v2sf) {3.4, 5.8}; + if (!__builtin_mips_upper_c_eq_ps (b, c) || + !__builtin_mips_lower_c_eq_ps (b, c)) + abort (); + + /* alnv.ps with rs = 4*/ + a = (v2sf) {1, 2}; + b = (v2sf) {3, 4}; + i = 4; + c = __builtin_mips_alnv_ps (a, b, i); + d = (v2sf) {2, 3}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + /* alnv.ps with rs = 0 */ + a = (v2sf) {5, 6}; + b = (v2sf) {7, 8}; + i = 0; + c = __builtin_mips_alnv_ps (a, b, i); + d = (v2sf) {5, 6}; + + if (!__builtin_mips_upper_c_eq_ps (c, d) || + !__builtin_mips_lower_c_eq_ps (c, d)) + abort (); + + printf ("Test Passes\n"); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c new file mode 100644 index 000000000..3b4e53085 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c @@ -0,0 +1,20 @@ +/* mips-ps-5.c with -mgp32 instead of -mgp64. */ +/* { dg-do compile } */ +/* { dg-options "-mgp32 -mpaired-single -ftree-vectorize" } */ +/* { dg-skip-if "requires vectorization" { *-*-* } { "-O0" "-Os" } { "" } } */ + +extern float a[] __attribute__ ((aligned (8))); +extern float b[] __attribute__ ((aligned (8))); +extern float c[] __attribute__ ((aligned (8))); + +NOMIPS16 void +foo (void) +{ + int i; + for (i = 0; i < 16; i++) + a[i] = b[i] == c[i] + 1 ? b[i] : c[i]; +} + +/* { dg-final { scan-assembler "\tadd\\.ps\t" } } */ +/* { dg-final { scan-assembler "\tc\\.eq\\.ps\t" } } */ +/* { dg-final { scan-assembler "\tmov\[tf\]\\.ps\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c new file mode 100644 index 000000000..f52cf91e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c @@ -0,0 +1,112 @@ +/* Test v2sf calculations. The nmadd and nmsub patterns need + -ffinite-math-only. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mgp32 -mpaired-single -ffinite-math-only" } */ +/* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */ +/* { dg-final { scan-assembler "\tmov.ps\t" } } */ +/* { dg-final { scan-assembler "\tldc1\t" } } */ +/* { dg-final { scan-assembler "\tsdc1\t" } } */ +/* { dg-final { scan-assembler "\tadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tneg.ps\t" } } */ +/* { dg-final { scan-assembler "\tmul.ps\t" } } */ +/* { dg-final { scan-assembler "\tmadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tmsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tnmadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tmovn.ps\t" } } */ +/* { dg-final { scan-assembler "\tmovz.ps\t" } } */ + +typedef float v2sf __attribute__ ((vector_size(8))); +void gobble (v2sf); + +v2sf A = {100, 200}; + +/* Init from floats */ +NOMIPS16 v2sf init (float a, float b) +{ + return (v2sf) {a, b}; +} + +/* Move between registers */ +NOMIPS16 v2sf move (v2sf a) +{ + return a; +} + +/* Load from memory */ +NOMIPS16 v2sf load () +{ + return A; +} + +/* Store to memory */ +NOMIPS16 void store (v2sf a) +{ + A = a; +} + +/* Add */ +NOMIPS16 v2sf add (v2sf a, v2sf b) +{ + return a + b; +} + +/* Subtract */ +NOMIPS16 v2sf sub (v2sf a, v2sf b) +{ + return a - b; +} + +/* Negate */ +NOMIPS16 v2sf neg (v2sf a) +{ + return - a; +} + +/* Multiply */ +NOMIPS16 v2sf mul (v2sf a, v2sf b) +{ + return a * b; +} + +/* Multiply and add */ +NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c) +{ + return a * b + c; +} + +/* Multiply and subtract */ +NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c) +{ + return a * b - c; +} + +/* Negate Multiply and add */ +NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c) +{ + return - (a * b + c); +} + +/* Negate Multiply and subtract */ +NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c) +{ + return - (a * b - c); +} + +/* Conditional Move */ +NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, int i) +{ + if (i == 0) + a = b; + gobble (a); +} + +/* Conditional Move */ +NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i) +{ + if (i != 0) + a = b; + gobble (a); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c new file mode 100644 index 000000000..c36dc25c9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c @@ -0,0 +1,112 @@ +/* Test v2sf calculations. The nmadd and nmsub patterns need + -ffinite-math-only. */ +/* { dg-do compile } */ +/* { dg-options "-mpaired-single -mgp64 -ffinite-math-only" } */ +/* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */ +/* { dg-final { scan-assembler "\tmov.ps\t" } } */ +/* { dg-final { scan-assembler "\tldc1\t" } } */ +/* { dg-final { scan-assembler "\tsdc1\t" } } */ +/* { dg-final { scan-assembler "\tadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tneg.ps\t" } } */ +/* { dg-final { scan-assembler "\tmul.ps\t" } } */ +/* { dg-final { scan-assembler "\tmadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tmsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tnmadd.ps\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.ps\t" } } */ +/* { dg-final { scan-assembler "\tmov(n|z).ps\t" } } */ + +typedef float v2sf __attribute__ ((vector_size(8))); + +v2sf A = {100, 200}; + +/* Init from floats */ +NOMIPS16 v2sf init (float a, float b) +{ + return (v2sf) {a, b}; +} + +/* Move between registers */ +NOMIPS16 v2sf move (v2sf a) +{ + return a; +} + +/* Load from memory */ +NOMIPS16 v2sf load () +{ + return A; +} + +/* Store to memory */ +NOMIPS16 void store (v2sf a) +{ + A = a; +} + +/* Add */ +NOMIPS16 v2sf add (v2sf a, v2sf b) +{ + return a + b; +} + +/* Subtract */ +NOMIPS16 v2sf sub (v2sf a, v2sf b) +{ + return a - b; +} + +/* Negate */ +NOMIPS16 v2sf neg (v2sf a) +{ + return - a; +} + +/* Multiply */ +NOMIPS16 v2sf mul (v2sf a, v2sf b) +{ + return a * b; +} + +/* Multiply and add */ +NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c) +{ + return a * b + c; +} + +/* Multiply and subtract */ +NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c) +{ + return a * b - c; +} + +/* Negate Multiply and add */ +NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c) +{ + return - (a * b + c); +} + +/* Negate Multiply and subtract */ +NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c) +{ + return - (a * b - c); +} + +/* Conditional Move */ +NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, long i) +{ + if (i > 0) + return a; + else + return b; +} + +/* Conditional Move */ +NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i) +{ + if (i > 0) + return a; + else + return b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c new file mode 100644 index 000000000..1db1550fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c @@ -0,0 +1,20 @@ +/* Test for case where another independent multiply insn may interfere + with a macc chain. */ +/* { dg-do compile } */ +/* { dg-options "-march=24kf" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 int foo (int a, int b, int c, int d, int e, int f, int g) +{ + int temp; + int acc; + + acc = a * b; + temp = a * c; + acc = d * e + acc; + acc = f * g + acc; + return acc > temp ? acc : temp; +} + +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmadd\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp new file mode 100644 index 000000000..8c72cff72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp @@ -0,0 +1,1308 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# A MIPS version of the GCC dg.exp driver. +# +# There are many MIPS features that we want to test, and many of those +# features are specific to certain architectures, certain ABIs and so on. +# There are therefore many cases in which we want to test something that +# is incompatible with the user's chosen test options. +# +# In most dg testsuites, the options added by dg-options have a lower +# priority than the options chosen by the user. For example, if a test +# specifies: +# +# { dg-options "-mips1" } +# +# and the user passes the following option to runtest: +# +# --target_board unix/-mips3 +# +# the test would be compiled as MIPS III rather than MIPS I. If the +# test really wouldn't work with -mips3, normal practice would be to +# have something like: +# +# { dg-do compile { target can_force_mips1 } } +# +# so that the test is skipped when an option like -mips3 is passed. +# +# Sticking to the same approach here would cause us to skip many tests, +# even though the toolchain can generate the required code. For example, +# there are 6 MIPS ABIs, plus variants. Some configurations support +# more than one ABI, so it is natural to use something like: +# +# --target_board unix{-mabi=n32,-mabi=32,-mabi=64} +# +# when testing them. But these -mabi=* options would normally prevent any +# EABI and o64 tests from running. +# +# This testsuite therefore defines a local version of dg-options that +# overrides any user options that are incompatible with the test options. +# It tries to keep the other user options intact. +# +# +# Most of the tests in this testsuite are scan-assembler tests, but +# sometimes we need a link test instead. In these cases, we must not +# try to link code with options that are incompatible with the current +# multilib, because xgcc is passed -L and -B options that are specific +# to that multilib. +# +# Normal GCC practice would be to skip incompatible link tests as +# unsupported, but in this particular case, it seems better to downgrade +# them to an assemble test instead. At least that way we get some +# test-for-ICE and code-sanity coverage. +# +# The same problem applies to run tests. If a test requires runtime +# support for a particular feature, and if the current target does not +# provide that support, normal practice would be to skip the test. +# But in this case it seems better to downgrade it to a link test instead. +# (We might then have to downgrade it to an assembler test according to +# the constraints just mentioned.) +# +# The local dg-options therefore checks whether the new options are +# link-compatiable with the user's options. If not, it automatically +# downgrades link tests to assemble tests. It does the same for run +# tests, but in addition, it downgrades run tests to link tests if the +# target does not provide runtime support for a required feature or ASE. +# +# +# Another problem is that many of the options we want to test require +# certain other features. For example, -mips3d requires both 64-bit +# FPRs and a MIPS32 or MIPS64 target; -mfix-r10000 requires branch- +# likely instructions; and so on. We could handle this by specifying +# a set of options that are guaranteed to give us what we want, such as: +# +# dg-options "-mips3d -mpaired-single -mhard-float -mgp64 -mfp64 -mabi=n32 -march=mips64 -mips64" +# +# With the new dg-options semantics, this would override any troublesome +# user options like -mips3, -march=vr4100, -mfp32, -mgp32, -msoft-float, +# -mno-paired-single and so on. But there are three major problems with +# this: +# +# - It is easy to forget options. +# +# - If a new option is added, all tests that are incompatible with that +# option must be updated. +# +# - We want to be able to test MIPS-3D with things like -march=mips32, +# -march=mips64r2, -march=sb1, and so on. +# +# The local version of dg-options therefore works out the requirements +# of each test option. As with the test options themselves, the local +# dg-options overrides any user options that incompatible with these +# requirements, but it keeps the other user options the same. +# +# For example, if the user passes -mips3, a MIPS-3D test will choose +# a different architecture like -mips64 instead. But if the user +# passes -march=sb1, MIPS-3D tests will be run with that option. +# +# +# Sometimes it is useful to say "I want an environment that is compatible +# with option X, but I don't want to pass option X itself". The main example +# of this is -mips16: we want to be able to test __attribute__((mips16)) +# without requiring the test itself to be compiled as -mips16. The local +# version of dg-options lets you do this by putting X in parentheses. +# For example: +# +# { dg-options "(-mips16)" } +# +# selects a MIPS16-compatible target without passing -mips16 itself. +# +# It is also useful to say "any architecture within this ISA range is fine". +# This can be done using special pseudo-options of the form: +# +# PROP=VALUE PROP<=VALUE PROP>=VALUE +# +# where PROP can be: +# +# isa: +# the value of the __mips macro. +# +# isa_rev: +# the value of the __mips_isa_rev macro, or 0 if it isn't defined. +# +# For example, "isa_rev>=1" selects a MIPS32 or MIPS64 processor, +# "isa=4" selects a MIPS IV processor, and so on. +# +# There are also the following special pseudo-options: +# +# isa=loongson +# select a Loongson processor +# +# addressing=absolute +# force absolute addresses to be used +# +# forbid_cpu=REGEXP +# forbid processors that match the given regexp; choose a +# generic ISA instead. +# +# +# In summary: +# +# (1) Try to avoid { target ... } requirements wherever possible. +# Specify the requirements as dg-options instead. +# +# (2) Don't worry about the consequences of (1) for link and run tests. +# If the test uses { dg-do link } or { dg-do run }, and its +# dg-options are incompatible with the current target, the +# testsuite will downgrade them where necessary. +# +# (3) Try to use the bare minimum of options and leave dg-options +# to work out the dependencies. For example, if you want +# a MIPS-3D test, you should generally just specify -mips3d. +# Don't specify an architecture option like -mips64 unless +# the test really doesn't work with -mips32r2, -mips64r2, +# -march=sb1, etc. +# +# (4) If you want something compatible with a particular option, +# but don't want to pass the option itself, wrap that option +# in parentheses. In particular, pass '(-mips16)' if you +# want to use "mips16" attributes. +# +# (5) When testing a feature of a generic ISA (as opposed to a +# processor-specific extension), try to use the "isa" and +# "isa_rev" pseudo-options instead of specific architecture +# options. For example, if the feature is present on revision 2 +# processors and above, try to use "isa_rev>=2" instead of +# "-mips32r2" or "-mips64r2". +# +# (6) If you need to disable processor-specific extensions use +# forbid_cpu=REGEXP instead of forcing a generic ISA. +# +# +# Terminology +# +# Option group or just group: +# See comment before mips_option_groups. +# +# Test options: +# The options specified in dg-options. +# +# Explicit options: +# The options that were either passed to runtest as "multilib" options +# (e.g. -mips4 in --target_board=mips-sim-idt/-mips4) or specified as +# test options. Note that options in parenthesis (i.e. (-mips16)) are +# not explicit and can be omitted depending on the base options. +# +# Base options: +# Options that are on by default without being specified in dg-options, +# e.g. -march=mips64r2 for mipsisa64r2-elf or because they've been +# passed to runtest as "multilib" options. +# +# Option array: +# Many functions in this file work with option arrays. These are +# two-dimensional Tcl arrays where the first dimension can have three +# values: option, explicit_p or test_option_p. The second dimension is +# the name of the option group. "option" contains the name of the +# option that is in effect from this group. If no option is active it +# contains the empty string. The flags "explicit_p" and "test_option_p" +# are set for explicit and test options. + +# Exit immediately if this isn't a MIPS target. +if ![istarget mips*-*-*] { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# A list of GROUP REGEXP pairs. Each GROUP represents a logical group of +# options from which only one option should be chosen. REGEXP matches all +# the options in that group; it is implicitly wrapped in "^(...)$". +# +# Note that -O* is deliberately omitted from this list. Tests in this +# directory are run at various optimisation levels and should use +# dg-skip-if to skip any incompatible levels. +set mips_option_groups { + abi "-mabi=.*" + addressing "addressing=.*" + arch "-mips([1-5]|32.*|64.*)|-march=.*|isa(|_rev)(=|<=|>=).*" + debug "-g.*" + dump_pattern "-dp" + endianness "-E(L|B)|-me(l|b)" + float "-m(hard|soft)-float" + forbid_cpu "forbid_cpu=.*" + fp "-mfp(32|64)" + gp "-mgp(32|64)" + long "-mlong(32|64)" + micromips "-mmicromips|-mno-micromips" + mips16 "-mips16|-mno-mips16|-mflip-mips16" + mips3d "-mips3d|-mno-mips3d" + pic "-f(no-|)(pic|PIC)" + profiling "-pg" + small-data "-G[0-9]+" + warnings "-w" + dump "-fdump-.*" +} + +# Add -mfoo/-mno-foo options to mips_option_groups. +foreach option { + abicalls + branch-likely + dsp + dspr2 + explicit-relocs + extern-sdata + fix-r4000 + fix-r10000 + fix-vr4130 + gpopt + local-sdata + long-calls + paired-single + plt + shared + smartmips + sym32 + synci + relax-pic-calls + mcount-ra-address +} { + lappend mips_option_groups $option "-m(no-|)$option" +} + +# Add -mfoo= options to mips_option_groups. +foreach option { + abs + branch-cost + code-readable + nan + r10k-cache-barrier + tune +} { + lappend mips_option_groups $option "-m$option=.*" +} + +# Add -ffoo/-fno-foo options to mips_option_groups. +foreach option { + common + delayed-branch + expensive-optimizations + fast-math + fat-lto-objects + finite-math-only + fixed-hi + fixed-lo + lax-vector-conversions + omit-frame-pointer + optimize-sibling-calls + peephole2 + schedule-insns2 + split-wide-types + tree-vectorize + unroll-all-loops + unroll-loops +} { + lappend mips_option_groups $option "-f(no-|)$option" +} + +# A list of option groups that have an impact on the ABI. +set mips_abi_groups { + abi + abicalls + arch + endianness + float + fp + gp + gpopt + long + pic + small-data +} + +# mips_option_tests(OPTION) is some assembly code that will run to completion +# on a target that supports OPTION. +set mips_option_tests(-mips16) { + move $2,$31 + bal 1f + .set mips16 + jr $31 + .set nomips16 + .align 2 +1: + ori $3,$31,1 + jalr $3 + move $31,$2 +} +set mips_option_tests(-mpaired-single) { + .set mips64 + lui $2,0x3f80 + mtc1 $2,$f0 + cvt.ps.s $f2,$f0,$f0 +} +set mips_option_tests(-mips3d) { + .set mips64 + .set mips3d + lui $2,0x3f80 + mtc1 $2,$f0 + cvt.ps.s $f2,$f0,$f0 + mulr.ps $f2,$f2,$f2 + rsqrt1.s $f2,$f0 + mul.s $f4,$f2,$f0 + rsqrt2.s $f4,$f4,$f2 + madd.s $f4,$f2,$f2,$f4 +} +set mips_option_tests(-mdsp) { + .set mips64r2 + .set dsp + addsc $2,$2,$2 +} +set mips_option_tests(-mdspr2) { + .set mips64r2 + .set dspr2 + prepend $2,$3,11 +} + +# Canonicalize command-line option OPTION. +proc mips_canonicalize_option { option } { + regsub {^-mips([1-5]|32*|64*)$} $option {-march=mips\1} option + + regsub {^-mel$} $option {-EL} option + regsub {^-meb$} $option {-EB} option + + regsub {^-O$} $option {-O1} option + + # MIPS doesn't use -fpic and -fPIC to distinguish between code models. + regsub {^-f(no-|)PIC} $option {-f\1pic} option + + return $option +} + +# Return true if OPTION1 and OPTION2 represent the same command-line option. +proc mips_same_option_p { option1 option2 } { + return [string equal \ + [mips_canonicalize_option $option1] \ + [mips_canonicalize_option $option2]] +} + +# Preprocess CODE using target_compile options OPTIONS. Return the +# compiler output. +proc mips_preprocess { options code } { + global tool + + set src dummy[pid].c + set f [open $src "w"] + puts $f $code + close $f + set output [${tool}_target_compile $src "" preprocess $options] + file delete $src + + return $output +} + +# Set the target board's command-line options to NEW_OPTIONS, storing the +# old values in UPVAR. +proc mips_push_test_options { upvar new_options } { + upvar $upvar var + global board_info + + array unset var + set var(name) board_info([target_info name],multilib_flags) + if { [info exists $var(name)] } { + set var(old_options) [set $var(name)] + set $var(name) [join $new_options " "] + } +} + +# Undo the effects of [mips_push_test_options UPVAR ...] +proc mips_pop_test_options { upvar } { + upvar $upvar var + global board_info + + if { [info exists var(old_options)] } { + set $var(name) $var(old_options) + } +} + +# Return property PROP for architecture option ARCH (which belongs to +# the "arch" group in mips_option_groups). See the comment at the +# top of the file for the valid property names. +# +# Cache the results in mips_arch_info (which can be reused between test +# variants). +proc mips_arch_info { arch prop } { + global mips_arch_info + global board_info + + set arch [mips_canonicalize_option $arch] + if { ![info exists mips_arch_info($arch,$prop)] } { + mips_push_test_options saved_options {} + set output [mips_preprocess [list "additional_flags=$arch -mabi=32"] { + int isa = __mips; + #ifdef __mips_isa_rev + int isa_rev = __mips_isa_rev; + #else + int isa_rev = 0; + #endif + }] + foreach lhs { isa isa_rev } { + regsub ".*$lhs = (\[^;\]*).*" $output {\1} rhs + verbose -log "Architecture $arch has $lhs $rhs" + set mips_arch_info($arch,$lhs) $rhs + } + mips_pop_test_options saved_options + } + return $mips_arch_info($arch,$prop) +} + +# Return the option group associated with OPTION, or "" if none. +proc mips_option_maybe_group { option } { + global mips_option_groups + + foreach { group regexp } $mips_option_groups { + if { [regexp -- "^($regexp)\$" $option] } { + return $group + } + } + return "" +} + +# Return the option group associated with OPTION. Raise an error if +# there is none. +proc mips_option_group { option } { + set group [mips_option_maybe_group $option] + if { [string equal $group ""] } { + error "Unrecognised option: $option" + } + return $group +} + +# Return the option for option group GROUP, or "" if no option in that +# group has been chosen. UPSTATUS describes the option status. +proc mips_option { upstatus group } { + upvar $upstatus status + + return $status(option,$group) +} + +# If the base options for this test run include an option in group GROUP, +# return that option, otherwise return "". +proc mips_original_option { group } { + global mips_base_options + + return [mips_option mips_base_options $group] +} + +# Return true if the test described by UPSTATUS requires a specific +# option in group GROUP. UPSTATUS describes the option status. +proc mips_test_option_p { upstatus group } { + upvar $upstatus status + + return $status(test_option_p,$group) +} + +# If the test described by UPSTATUS requires a particular option in group +# GROUP, return that option, otherwise return "". +proc mips_test_option { upstatus group } { + upvar $upstatus status + + if { [mips_test_option_p status $group] } { + return [mips_option status $group] + } else { + return "" + } +} + +# Return true if the options described by UPSTATUS include OPTION. +proc mips_have_option_p { upstatus option } { + upvar $upstatus status + + return [mips_same_option_p \ + [mips_option status [mips_option_group $option]] \ + $option] +} + +# Return true if the options described by UPSTATUS require MIPS16 support. +proc mips_using_mips16_p { upstatus } { + upvar $upstatus status + + return [expr { [mips_have_option_p status "-mips16"] + || [mips_have_option_p status "-mflip-mips16"] }] +} + +# Return true if the test described by UPSTATUS requires option OPTION. +proc mips_have_test_option_p { upstatus option } { + upvar $upstatus status + + set group [mips_option_group $option] + return [mips_same_option_p [mips_test_option status $group] $option] +} + +# If the test described by UPSTATUS does not specify an option in +# OPTION's group, act as though it had specified OPTION. +# +# The first optional argument indicates whether the option should be +# treated as though it were wrapped in parentheses; see the comment at +# the top of the file for details about this convention. The default is 0. +proc mips_make_test_option { upstatus option args } { + upvar $upstatus status + + set group [mips_option_group $option] + if { ![mips_test_option_p status $group] } { + set status(option,$group) $option + set status(test_option_p,$group) 1 + if { [llength $args] == 0 || ![lindex $args 0] } { + set status(explicit_p,$group) 1 + } + } +} + +# If the test described by UPSTATUS requires option FROM, assume that +# it implicitly requires option TO. +proc mips_option_dependency { upstatus from to } { + upvar $upstatus status + + if { [mips_have_test_option_p status $from] } { + mips_make_test_option status $to + } +} + +# Return true if the given arch-group option specifies a 32-bit ISA. +proc mips_32bit_arch_p { option } { + set isa [mips_arch_info $option isa] + return [expr { $isa < 3 || $isa == 32 }] +} + +# Return true if the given arch-group option specifies a 64-bit ISA. +proc mips_64bit_arch_p { option } { + return [expr { ![mips_32bit_arch_p $option] }] +} + +# Return true if the given abi-group option implicitly requires -mgp32. +proc mips_32bit_abi_p { option } { + switch -glob -- $option { + -mabi=32 { + return 1 + } + } + return 0 +} + +# Return true if the given abi-group option implicitly requires -mgp64. +proc mips_64bit_abi_p { option } { + switch -glob -- $option { + -mabi=o64 - + -mabi=n32 - + -mabi=64 { + return 1 + } + } + return 0 +} + +# Return true if the given abi-group option implicitly requires -mlong32. +# o64 requires this for -mabicalls, but not otherwise; pick the conservative +# case for simplicity. +proc mips_long32_abi_p { option } { + switch -glob -- $option { + -mabi=o64 - + -mabi=n32 - + -mabi=32 { + return 1 + } + } + return 0 +} + +# Return true if the given abi-group option implicitly requires -mlong64. +proc mips_long64_abi_p { option } { + switch -glob -- $option { + -mabi=64 { + return 1 + } + } + return 0 +} + +# Check whether the current target supports all the options that the +# current test requires. Return "" if so, otherwise return one of +# the incompatible options. UPSTATUS describes the option status. +proc mips_first_unsupported_option { upstatus } { + global mips_option_tests + upvar $upstatus status + + foreach { option code } [array get mips_option_tests] { + if { [mips_have_test_option_p status $option] } { + regsub -all "\n" $code "\\n\\\n" asm + # Use check_runtime from target-supports.exp, which caches + # the result for us. + if { ![check_runtime mips_option_$option [subst { + __attribute__((nomips16)) int + main (void) + { + asm (".set push\ + $asm\ + .set pop"); + return 0; + } + }]] } { + return $option + } + } + } + return "" +} + +# Initialize this testsuite for a new test variant. +proc mips-dg-init {} { + # Invariant information. + global mips_option_groups + + # Internally-generated information about this run. + global mips_base_options + global mips_extra_options + + # Override dg-options with our mips-dg-options routine. + rename dg-options mips-old-dg-options + rename mips-dg-options dg-options + + # Start with a fresh option status. + array unset mips_base_options + foreach { group regexp } $mips_option_groups { + set mips_base_options(option,$group) "" + set mips_base_options(explicit_p,$group) 0 + set mips_base_options(test_option_p,$group) 0 + } + + # Use preprocessor macros to work out as many implicit options as we can. + set output [mips_preprocess "" { + const char *options[] = { + #if !defined _MIPS_SIM + "-mabi=eabi", + #elif _MIPS_SIM==_ABIO32 + "-mabi=32", + #elif _MIPS_SIM==_ABIO64 + "-mabi=o64", + #elif _MIPS_SIM==_ABIN32 + "-mabi=n32", + #else + "-mabi=64", + #endif + + "-march=" _MIPS_ARCH, + + #ifdef _MIPSEB + "-EB", + #else + "-EL", + #endif + + #ifdef __mips_hard_float + "-mhard-float", + #else + "-msoft-float", + #endif + + #ifdef __mips_abs2008 + "-mabs=2008", + #else + "-mabs=legacy", + #endif + + #ifdef __mips_nan2008 + "-mnan=2008", + #else + "-mnan=legacy", + #endif + + #if __mips_fpr == 64 + "-mfp64", + #else + "-mfp32", + #endif + + #ifdef __mips64 + "-mgp64", + #else + "-mgp32", + #endif + + #if _MIPS_SZLONG == 64 + "-mlong64", + #else + "-mlong32", + #endif + + #ifdef __mips16 + "-mips16", + #else + "-mno-mips16", + #endif + + #ifdef __mips3d + "-mips3d", + #else + "-mno-mips3d", + #endif + + #ifdef __mips_paired_single_float + "-mpaired-single", + #else + "-mno-paired-single", + #endif + + #if __mips_abicalls + "-mabicalls", + #else + "-mno-abicalls", + #endif + + #if __mips_dsp_rev >= 2 + "-mdspr2", + #else + "-mno-dspr2", + #endif + + #if __mips_dsp_rev >= 1 + "-mdsp", + #else + "-mno-dsp", + #endif + + #ifndef __PIC__ + "addressing=absolute", + #endif + + #ifdef __mips_smartmips + "-msmartmips", + #else + "-mno-smartmips", + #endif + + #ifdef __mips_synci + "-msynci", + #else + "-mno-synci", + #endif + + 0 + }; + }] + foreach line [split $output "\r\n"] { + # Poor man's string concatenation. + regsub -all {" "} $line "" line + if { [regexp {"(.*)",} $line dummy option] } { + set group [mips_option_group $option] + set mips_base_options(option,$group) $option + } + } + + # Process the target's multilib options, saving any unrecognized + # ones in mips_extra_options. + set mips_extra_options {} + foreach option [split [board_info target multilib_flags]] { + set group [mips_option_maybe_group $option] + if { ![string equal $group ""] } { + set mips_base_options(option,$group) $option + set mips_base_options(explicit_p,$group) 1 + } else { + lappend mips_extra_options $option + } + } +} + +# Finish a test run started by mips-dg-init. +proc mips-dg-finish {} { + rename dg-options mips-dg-options + rename mips-old-dg-options dg-options +} + +# Override dg-options so that we can do some MIPS-specific processing. +# All options used in this testsuite must appear in mips_option_groups. +# +# Test options override multilib options. Certain test options can +# also imply other test options, which also override multilib options. +# These dependencies are ordered as follows: +# +# START END +# | | +# -mips16/-mflip-mips16 -mno-mips16 +# | | +# -micromips -mno-micromips +# | | +# -mips3d -mno-mips3d +# | | +# -mpaired-single -mno-paired-single +# | | +# -mfp64 -mfp32 +# | | +# -mabs=2008/-mabs=legacy <no option> +# | | +# -mhard-float -msoft-float +# | | +# -mno-sym32 -msym32 +# | | +# -mrelax-pic-calls -mno-relax-pic-calls +# | | +# -fpic -fno-pic +# | | +# -mshared -mno-shared +# | | +# -mno-plt -mplt +# | | +# addressing=unknown addressing=absolute +# | | +# -mabicalls -mno-abicalls +# | | +# -G0 <other value> +# | | +# <other value> -mr10k-cache-barrier=none +# | | +# -mfix-r10000 -mno-fix-r10000 +# | | +# -mbranch-likely -mno-branch-likely +# | | +# -msmartmips -mno-smartmips +# | | +# -mno-gpopt -mgpopt +# | | +# -mexplicit-relocs -mno-explicit-relocs +# | | +# -mdspr2 -mno-dspr2 +# | | +# -mdsp -mno-dsp +# | | +# -msynci -mno-synci +# | | +# +-- gp, abi & arch ---------+ +# +# For these purposes, the "gp", "abi" & "arch" option groups are treated +# as a single node. +proc mips-dg-options { args } { + # dg.exp variables. + upvar dg-extra-tool-flags extra_tool_flags + upvar dg-do-what do_what + + # Invariant information. + global mips_option_groups + global mips_abi_groups + + # Information about this run. + global mips_base_options + + if { [llength $args] >= 3 } { + switch { [dg-process-target [lindex $args 2]] } { + "S" { } + "N" { return } + "F" { error "[lindex $args 0]: `xfail' not allowed here" } + "P" { error "[lindex $args 0]: `xfail' not allowed here" } + } + } + + # Start out with the default option state. + array set options [array get mips_base_options] + + # Record the options that this test explicitly needs. + foreach option [lindex $args 1] { + set all_but_p [regexp {^\((.*)\)$} $option dummy option] + set group [mips_option_group $option] + if { [mips_test_option_p options $group] } { + set old [mips_option options $group] + error "Inconsistent $group option: $old vs. $option" + } else { + mips_make_test_option options $option $all_but_p + } + } + + # Handle dependencies between the test options and the optimization ones. + mips_option_dependency options "-fno-unroll-loops" "-fno-unroll-all-loops" + mips_option_dependency options "-pg" "-fno-omit-frame-pointer" + + # Handle dependencies between options on the left of the + # dependency diagram. + mips_option_dependency options "-mips16" "-mno-micromips" + mips_option_dependency options "-mmicromips" "-mno-mips16" + mips_option_dependency options "-mips3d" "-mpaired-single" + mips_option_dependency options "-mpaired-single" "-mfp64" + mips_option_dependency options "-mfp64" "-mhard-float" + mips_option_dependency options "-mabs=2008" "-mhard-float" + mips_option_dependency options "-mabs=legacy" "-mhard-float" + mips_option_dependency options "-mrelax-pic-calls" "-mno-plt" + mips_option_dependency options "-mrelax-pic-calls" "-mabicalls" + mips_option_dependency options "-mrelax-pic-calls" "-mexplicit-relocs" + mips_option_dependency options "-fpic" "-mshared" + mips_option_dependency options "-mshared" "-mno-plt" + mips_option_dependency options "-mshared" "-mabicalls" + mips_option_dependency options "-mno-plt" "addressing=unknown" + mips_option_dependency options "-mabicalls" "-G0" + mips_option_dependency options "-mno-gpopt" "-mexplicit-relocs" + + # Work out information about the current ABI. + set abi_test_option_p [mips_test_option_p options abi] + set abi [mips_option options abi] + set eabi_p [mips_same_option_p $abi "-mabi=eabi"] + + # If the test forces a particular ABI, set the register size + # accordingly. + if { $abi_test_option_p } { + if { [mips_32bit_abi_p $abi] } { + mips_make_test_option options "-mgp32" + } elseif { [mips_64bit_abi_p $abi] } { + mips_make_test_option options "-mgp64" + } + } + + # See whether forbid_cpu forces us to choose a new architecture. + set arch [mips_option mips_base_options arch] + set force_generic_isa_p [expr { + [regexp "forbid_cpu=(.*)" [mips_option options forbid_cpu] dummy spec] + && [regexp -- "^-march=$spec\$" $arch] + }] + + # Interpret the special "isa" and "isa_rev" options. If we have + # a choice of a 32-bit or a 64-bit architecture, prefer to keep + # the -mgp setting the same. + set spec [mips_option options arch] + if { [regexp {^[^-]} $spec] } { + if { [string equal $spec "isa=loongson"] } { + if { ![regexp {^-march=loongson} $arch] } { + set arch "-march=loongson2f" + } + } else { + if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)$} \ + $spec dummy prop relation value nocpus] } { + error "Unrecognized isa specification: $spec" + } + set current [mips_arch_info $arch $prop] + if { $force_generic_isa_p + || ($current < $value && ![string equal $relation "<="]) + || ($current > $value && ![string equal $relation ">="]) + || ([mips_have_test_option_p options "-mgp64"] + && [mips_32bit_arch_p $arch]) } { + # The current setting is out of range; it cannot + # possibly be used. Find a replacement that can. + if { [string equal $prop "isa"] } { + set arch "-mips$value" + } elseif { $value == 0 } { + set arch "-mips4" + } else { + if { [mips_have_option_p options "-mgp32"] } { + set arch "-mips32" + } else { + set arch "-mips64" + } + if { $value > 1 } { + append arch "r$value" + } + } + } + } + set options(option,arch) $arch + } + + # Work out information about the current architecture. + set arch_test_option_p [mips_test_option_p options arch] + set arch [mips_option options arch] + set isa [mips_arch_info $arch isa] + set isa_rev [mips_arch_info $arch isa_rev] + + # If the test forces a 32-bit architecture, force -mgp32. + # Force the current -mgp setting otherwise; if we don't, + # some configurations would make a 64-bit architecture + # imply -mgp64. + if { $arch_test_option_p } { + if { [mips_32bit_arch_p $arch] } { + mips_make_test_option options "-mgp32" + } else { + mips_make_test_option options [mips_option options gp] + } + } + + # We've now fixed the GP register size. Make it easily available. + set gp_size [expr { [mips_have_option_p options "-mgp32"] ? 32 : 64 }] + + # Handle dependencies between the pre-arch options and the arch option. + # This should mirror the arch and post-arch code below. + if { !$arch_test_option_p } { + # We need a revision 2 or better ISA for: + # + # - the combination of -mgp32 -mfp64 + # - the DSP ASE + if { $isa_rev < 2 + && (($gp_size == 32 && [mips_have_test_option_p options "-mfp64"]) + || [mips_have_test_option_p options "-msynci"] + || [mips_have_test_option_p options "-mdsp"] + || [mips_have_test_option_p options "-mdspr2"]) } { + if { $gp_size == 32 } { + mips_make_test_option options "-mips32r2" + } else { + mips_make_test_option options "-mips64r2" + } + # We need a MIPS32 or MIPS64 ISA for: + # + # - paired-single instructions(*) + # + # (*) Note that we don't support MIPS V at the moment. + } elseif { $isa_rev < 1 + && [mips_have_test_option_p options "-mpaired-single"] } { + if { $gp_size == 32 } { + mips_make_test_option options "-mips32" + } else { + mips_make_test_option options "-mips64" + } + # We need MIPS III or higher for: + # + # - the "cache" instruction + } elseif { $isa < 3 + && ([mips_have_test_option_p options \ + "-mr10k-cache-barrier=load-store"] + || [mips_have_test_option_p options \ + "-mr10k-cache-barrier=store"]) } { + mips_make_test_option options "-mips3" + # We need MIPS II or higher for: + # + # - branch-likely instructions(*) + # + # (*) needed by both -mbranch-likely and -mfix-r10000 + } elseif { $isa < 2 + && ([mips_have_test_option_p options "-mbranch-likely"] + || [mips_have_test_option_p options "-mfix-r10000"]) } { + mips_make_test_option options "-mips2" + # Check whether we need to switch from a 32-bit processor to the + # "nearest" 64-bit processor. + } elseif { $gp_size == 64 && [mips_32bit_arch_p $arch] } { + if { $isa_rev == 0 } { + mips_make_test_option options "-mips3" + } elseif { $isa_rev == 1 } { + mips_make_test_option options "-mips64" + } else { + mips_make_test_option options "-mips64r$isa_rev" + } + # Otherwise, if the current choice of architecture is unacceptable, + # choose the equivalent generic architecture. + } elseif { $force_generic_isa_p } { + set arch "-mips[mips_arch_info $arch isa]" + if { $isa_rev > 1 } { + append arch "r$isa_rev" + } + mips_make_test_option options $arch + } + unset arch + unset isa + unset isa_rev + } + + # Set an appropriate ABI, handling dependencies between the pre-abi + # options and the abi options. This should mirror the abi and post-abi + # code below. + if { !$abi_test_option_p } { + if { ($eabi_p + && ([mips_have_option_p options "-mabicalls"] + || ($gp_size == 32 + && [mips_have_option_p options "-mfp64"]))) } { + # EABI doesn't support -mabicalls. + # EABI doesn't support the combination -mgp32 -mfp64. + set force_abi 1 + } elseif { [mips_using_mips16_p options] + && ![mips_same_option_p $abi "-mabi=32"] + && ![mips_same_option_p $abi "-mabi=o64"] + && (![mips_have_option_p options "addressing=absolute"] + || [mips_have_option_p options "-mhard-float"]) } { + # -mips16 -mhard-float requires o32 or o64. + # -mips16 PIC requires o32 or o64. + set force_abi 1 + } elseif { [mips_have_test_option_p options "-mlong32"] + && [mips_long64_abi_p $abi] } { + set force_abi 1 + } elseif { [mips_have_test_option_p options "-mlong64"] + && [mips_long32_abi_p $abi] } { + set force_abi 1 + } else { + set force_abi 0 + } + if { $gp_size == 32 } { + if { $force_abi || [mips_64bit_abi_p $abi] } { + if { [mips_have_test_option_p options "-mlong64"] } { + mips_make_test_option options "-mabi=eabi" + mips_make_test_option options "-mgp32" + } else { + mips_make_test_option options "-mabi=32" + } + } + } else { + if { $force_abi || [mips_32bit_abi_p $abi] } { + if { [mips_have_test_option_p options "-mlong64"] } { + mips_make_test_option options "-mabi=eabi" + mips_make_test_option options "-mgp64" + } else { + # All configurations should have an assembler that + # supports o64, since it requires the same BFD target + # vector as o32. In contrast, many assembler + # configurations do not have n32 or n64 support. + mips_make_test_option options "-mabi=o64" + } + } + } + set abi_test_option_p [mips_test_option_p options abi] + set abi [mips_option options abi] + set eabi_p [mips_same_option_p $abi "-mabi=eabi"] + } + + # Handle dependencies between the abi options and the post-abi options. + # This should mirror the abi and pre-abi code above. + if { $abi_test_option_p } { + if { $eabi_p } { + mips_make_test_option options "-mno-abicalls" + if { $gp_size == 32 } { + mips_make_test_option options "-mfp32" + } + } + if { [mips_using_mips16_p options] + && ![mips_same_option_p $abi "-mabi=32"] + && ![mips_same_option_p $abi "-mabi=o64"] + && ([mips_have_option_p options "-mabicalls"] + || [mips_have_option_p options "-mhard-float"]) } { + if { [mips_test_option_p options mips16] } { + mips_make_test_option options "addressing=absolute" + mips_make_test_option options "-msoft-float" + } else { + mips_make_test_option options "-mno-mips16" + } + } + if { [mips_long32_abi_p $abi] } { + mips_make_test_option options "-mlong32" + } elseif { [mips_long64_abi_p $abi] } { + mips_make_test_option options "-mlong64" + } + } + + # Handle dependencies between the arch option and the post-arch options. + # This should mirror the arch and pre-arch code above. + if { $arch_test_option_p } { + if { $isa < 2 } { + mips_make_test_option options "-mno-branch-likely" + mips_make_test_option options "-mno-fix-r10000" + } + if { $isa < 3 } { + mips_make_test_option options "-mr10k-cache-barrier=none" + } + if { $isa_rev < 1 } { + mips_make_test_option options "-mno-paired-single" + } + if { $isa_rev < 2 } { + if { $gp_size == 32 } { + mips_make_test_option options "-mfp32" + } + mips_make_test_option options "-mno-dsp" + mips_make_test_option options "-mno-synci" + } + unset arch + unset isa + unset isa_rev + } + + # Handle dependencies between options on the right of the diagram. + mips_option_dependency options "-mno-dsp" "-mno-dspr2" + mips_option_dependency options "-mno-explicit-relocs" "-mgpopt" + switch -- [mips_test_option options small-data] { + "" - + -G0 {} + default { + mips_make_test_option options "-mno-abicalls" + } + } + if { [mips_have_option_p options "-mabicalls"] } { + mips_option_dependency options "addressing=absolute" "-mplt" + } + mips_option_dependency options "-mplt" "-msym32" + mips_option_dependency options "-mplt" "-mno-shared" + mips_option_dependency options "-mno-shared" "-fno-pic" + mips_option_dependency options "-mfp32" "-mno-paired-single" + mips_option_dependency options "-msoft-float" "-mno-paired-single" + mips_option_dependency options "-mno-paired-single" "-mno-mips3d" + + # If the test requires an unsupported option, change run tests + # to link tests. + + switch -- [lindex $do_what 0] { + run { + set option [mips_first_unsupported_option options] + if { ![string equal $option ""] } { + set do_what [lreplace $do_what 0 0 link] + verbose -log "Downgraded to a 'link' test due to unsupported option '$option'" + } + } + } + + # If the test has overridden a option that changes the ABI, + # downgrade a link or execution test to an assembler test. + foreach group $mips_abi_groups { + set old_option [mips_original_option $group] + set new_option [mips_option options $group] + if { ![mips_same_option_p $old_option $new_option] } { + switch -- [lindex $do_what 0] { + link - + run { + set do_what [lreplace $do_what 0 0 assemble] + verbose -log "Downgraded to an 'assemble' test due to incompatible $group option ($old_option changed to $new_option)" + } + } + break + } + } + + # Add all options to the dg variable. + set options(explicit_p,addressing) 0 + set options(explicit_p,forbid_cpu) 0 + foreach { group regexp } $mips_option_groups { + if { $options(explicit_p,$group) } { + append extra_tool_flags " " $options(option,$group) + } + } + + # If the test is MIPS16-compatible, provide a counterpart to the + # NOMIPS16 convenience macro. + if { [mips_have_test_option_p options "-mips16"] } { + append extra_tool_flags " -DMIPS16=__attribute__((mips16))" + } + + if { [mips_have_test_option_p options "-mmicromips"] } { + append extra_tool_flags " -DMICROMIPS=__attribute__((micromips))" + } + + # Use our version of gcc-dg-test for this test. + if { ![string equal [info procs "mips-gcc-dg-test"] ""] } { + rename gcc-dg-test mips-old-gcc-dg-test + rename mips-gcc-dg-test gcc-dg-test + } +} + +# A version of gcc-dg-test that is used by dg-options tests. +proc mips-gcc-dg-test { prog do_what extra_tool_flags } { + global board_info + global mips_extra_options + + # Override the user's chosen test options with the combined test/user + # version. + mips_push_test_options saved_options $mips_extra_options + set result [gcc-dg-test-1 gcc_target_compile $prog \ + $do_what $extra_tool_flags] + mips_pop_test_options saved_options + + # Restore the usual gcc-dg-test. + rename gcc-dg-test mips-gcc-dg-test + rename mips-old-gcc-dg-test gcc-dg-test + + return $result +} + +dg-init +mips-dg-init +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \ + "-DNOMIPS16=__attribute__((nomips16)) -DNOMICROMIPS=__attribute__((nomicromips)) -DNOCOMPRESSION=__attribute__((nocompression))" +mips-dg-finish +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c new file mode 100644 index 000000000..bc81cfa7e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c @@ -0,0 +1,16 @@ +/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */ +/* { dg-options "(-mips16)" } */ + +void f1 (void); +void __attribute__((mips16)) f1 (void) {} /* { dg-error "conflicting" } */ + +void __attribute__((mips16)) f2 (void); +void f2 (void) {} /* { dg-error "conflicting" } */ + +void f3 (void); +void __attribute__((nomips16)) f3 (void) {} /* { dg-error "conflicting" } */ + +void __attribute__((nomips16)) f4 (void); +void f4 (void) {} /* { dg-error "conflicting" } */ + +void __attribute__((mips16, nomips16)) f5 (void) {} /* { dg-error "cannot have both" } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c new file mode 100644 index 000000000..747450390 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c @@ -0,0 +1,7 @@ +/* { dg-options "(-mips16)" } */ +/* We should be able to assign mips16 and nomips16 functions to a pointer. */ +void __attribute__((mips16)) f1 (void); +void (*ptr1) (void) = f1; + +void __attribute__((nomips16)) f2 (void); +void (*ptr2) (void) = f2; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c new file mode 100644 index 000000000..de7cb4349 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-options "(-mips16)" } */ + +extern void abort (void); + +__complex float f = { -1.0 + -1.0i }; +__complex float __attribute__((nomips16)) foo (void) { return f; } +__complex float (*volatile foop) (void) = foo; +__complex float __attribute__((mips16, noinline)) bar (void) { return foop (); } + +int +main (void) +{ + if (bar () != f) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c new file mode 100644 index 000000000..b84fa8862 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "(-mips16) addressing=absolute" } */ +/* { dg-skip-if "requires inlining" { *-*-* } { "-O0" } { "" } } */ + +static inline MIPS16 int i1 (void) { return 1; } +static inline NOMIPS16 int i2 (void) { return 2; } +static inline MIPS16 int i3 (void) { return 3; } +static inline NOMIPS16 int i4 (void) { return 4; } + +int NOMIPS16 f1 (void) { return i1 (); } +int MIPS16 f2 (void) { return i2 (); } +int MIPS16 f3 (void) { return i3 (); } +int NOMIPS16 f4 (void) { return i4 (); } + +/* { dg-final { scan-assembler "i1:" } } */ +/* { dg-final { scan-assembler "i2:" } } */ +/* { dg-final { scan-assembler-not "i3:" } } */ +/* { dg-final { scan-assembler-not "i4:" } } */ +/* { dg-final { scan-assembler "\tjal\ti1" } } */ +/* { dg-final { scan-assembler "\tjal\ti2" } } */ +/* { dg-final { scan-assembler-not "\tjal\ti3" } } */ +/* { dg-final { scan-assembler-not "\tjal\ti4" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c new file mode 100644 index 000000000..99bdf8c3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mips16 addressing=absolute -mips3d" } */ + +static inline NOMIPS16 float +i1 (float f) +{ + return __builtin_mips_recip1_s (f); +} + +float f1 (float f) { return i1 (f); } + +/* { dg-final { scan-assembler "\trecip1.s\t" } } */ +/* { dg-final { scan-assembler "\tjal\ti1" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c new file mode 100644 index 000000000..28bb9aae7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c @@ -0,0 +1,83 @@ +/* Verify that mips16 and nomips16 attributes work, checking all combinations + of calling a nomips16/mips16/default function from a nomips16/mips16/default + function. */ +/* { dg-do run } */ +/* { dg-options "(-mips16)" } */ + +#include <stdlib.h> + +#define ATTR1 __attribute__ ((nomips16)) +#define ATTR2 __attribute__ ((mips16)) +#define ATTR3 + +double ATTR1 +f1 (int i, float f, double d) +{ + return i + f + d; +} + +double ATTR2 +f2 (int i, float f, double d) +{ + return i + f + d; +} + +double ATTR3 +f3 (int i, float f, double d) +{ + return i + f + d; +} + +void ATTR1 +g1 (int i, float f, double d) +{ + double r = i + f + d; + + if (f1 (i, f, d) != r) + abort (); + if (f2 (i+1, f+1, d+1) != r + 3) + abort (); + if (f3 (i+2, f+2, d+2) != r + 6) + abort (); +} + +void ATTR2 +g2 (int i, float f, double d) +{ + double r = i + f + d; + + if (f1 (i, f, d) != r) + abort (); + if (f2 (i+1, f+1, d+1) != r + 3) + abort (); + if (f3 (i+2, f+2, d+2) != r + 6) + abort (); +} + +void ATTR3 +g3 (int i, float f, double d) +{ + double r = i + f + d; + + if (f1 (i, f, d) != r) + abort (); + if (f2 (i+1, f+1, d+1) != r + 3) + abort (); + if (f3 (i+2, f+2, d+2) != r + 6) + abort (); +} + +int ATTR3 +main (void) +{ + int i = 1; + float f = -2.0; + double d = 3.0; + + g1 (i, f, d); + g2 (i, f, d); + g3 (i, f, d); + + exit (0); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c new file mode 100644 index 000000000..d8946c979 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c @@ -0,0 +1,22 @@ +/* -mlong32 added because of PR target/38595. */ +/* { dg-options "(-mips16) isa_rev>=1 -mlong32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MIPS16 short cksum16 (unsigned long n) +{ + unsigned long l; + l = validate (n, (n >> 16) + (n & 0xffff)); + return l; +} + +MIPS16 signed char cksum8 (unsigned long n) +{ + unsigned long l; + l = validate (n, (n >> 8) + (n & 0xff)); + return l; +} + +/* { dg-final { scan-assembler "\tzeh\t" } } */ +/* { dg-final { scan-assembler "\tseh\t" } } */ +/* { dg-final { scan-assembler "\tzeb\t" } } */ +/* { dg-final { scan-assembler "\tseb\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c new file mode 100644 index 000000000..d26f99840 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c @@ -0,0 +1,22 @@ +/* { dg-options "-mdspr2 -mgp32 -mtune=74kc" } */ +/* References to RESULT within the loop need to have a higher frequency than + references to RESULT outside the loop, otherwise there is no reason + to prefer multiply/accumulator registers over GPRs. */ +/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */ + +/* Check that the zero-initialization of the accumulator feeding into + the madd is done by means of a mult instruction instead of mthi/mtlo. */ + +NOMIPS16 long long f (int n, int *v, int m) +{ + long long result = 0; + int i; + + for (i = 0; i < n; i++) + result = __builtin_mips_madd (result, v[i], m); + return result; +} + +/* { dg-final { scan-assembler "\tmult\t\\\$ac.,\\\$0,\\\$0" } } */ +/* { dg-final { scan-assembler-not "mthi\t" } } */ +/* { dg-final { scan-assembler-not "mtlo\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c new file mode 100644 index 000000000..74608d943 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c @@ -0,0 +1,23 @@ +/* { dg-options "-mdspr2 -mgp32 -mtune=4kp" } */ +/* References to RESULT within the loop need to have a higher frequency than + references to RESULT outside the loop, otherwise there is no reason + to prefer multiply/accumulator registers over GPRs. */ +/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */ + +/* Check that the zero-initialization of the accumulator feeding into + the madd is done by means of an mthi & mtlo pair instead of a + "mult $0,$0" instruction. */ + +NOMIPS16 long long f (int n, int *v, int m) +{ + long long result = 0; + int i; + + for (i = 0; i < n; i++) + result = __builtin_mips_madd (result, v[i], m); + return result; +} + +/* { dg-final { scan-assembler-not "mult\t\[^\n\]*\\\$0" } } */ +/* { dg-final { scan-assembler "\tmthi\t" } } */ +/* { dg-final { scan-assembler "\tmtlo\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c new file mode 100644 index 000000000..ccd9d380f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c @@ -0,0 +1,1063 @@ +/* Test MIPS32 DSP instructions */ +/* { dg-do run } */ +/* { dg-options "-mdsp" } */ + +#include <stdlib.h> +#include <stdio.h> + +typedef signed char v4i8 __attribute__ ((vector_size(4))); +typedef short v2q15 __attribute__ ((vector_size(4))); + +typedef int q31; +typedef int i32; +typedef unsigned int ui32; +typedef long long a64; + +NOMIPS16 void test_MIPS_DSP (void); + +char array[100]; +int little_endian; + +int main () +{ + int i; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + for (i = 0; i < 100; i++) + array[i] = i; + + test_MIPS_DSP (); + + exit (0); +} + +NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b) +{ + return __builtin_mips_addq_ph (a, b); +} + +NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b) +{ + return __builtin_mips_addu_qb (a, b); +} + +NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b) +{ + return __builtin_mips_subq_ph (a, b); +} + +NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b) +{ + return __builtin_mips_subu_qb (a, b); +} + +NOMIPS16 void test_MIPS_DSP () +{ + v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s; + v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s; + q31 q31_a,q31_b,q31_c,q31_r,q31_s; + /* To protect the multiplication-related tests from being optimized + at compile time. */ + volatile i32 i32_a,i32_b,i32_c,i32_r,i32_s; + volatile ui32 ui32_a,ui32_b,ui32_c; + a64 a64_a,a64_b,a64_c,a64_r,a64_s; + + void *ptr_a; + int r,s; + long long lr,ls; + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x81bd, 0x6789}; + v2q15_r = add_v2q15 (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x7fff, 0x6789}; + v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_b = 0x71234567; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_addq_s_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89}; + v4i8_r = add_v4i8 (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89}; + v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0xa2ab, 0x4567}; + v2q15_r = sub_v2q15 (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x8000, 0x4567}; + v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_b = 0x71234567; + q31_s = 0xfedcba99; + q31_r = __builtin_mips_subq_s_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67}; + v4i8_r = sub_v4i8 (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67}; + v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0xf5678900; + i32_b = 0x7abcdef0; + i32_s = 0x702467f0; + i32_r = __builtin_mips_addsc (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x75678900; + i32_b = 0x7abcdef0; + i32_s = 0xf02467f1; + i32_r = __builtin_mips_addwc (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0; + i32_b = 0x00000901; + i32_s = 9; + i32_r = __builtin_mips_modsub (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_s = 0x1f4; + i32_r = __builtin_mips_raddu_w_qb (v4i8_a); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8134}; + v2q15_s = (v2q15) {0x7fff, 0x7ecc}; + v2q15_r = __builtin_mips_absq_s_ph (v2q15_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = (q31) 0x80000000; + q31_s = (q31) 0x7fffffff; + q31_r = __builtin_mips_absq_s_w (q31_a); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x9999, 0x5612}; + v2q15_b = (v2q15) {0x5612, 0x3333}; + if (little_endian) + v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56}; + else + v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33}; + v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + q31_a = 0x12348678; + q31_b = 0x44445555; + if (little_endian) + v2q15_s = (v2q15) {0x4444, 0x1234}; + else + v2q15_s = (v2q15) {0x1234, 0x4444}; + v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x12348678; + q31_b = 0x44445555; + if (little_endian) + v2q15_s = (v2q15) {0x4444, 0x1235}; + else + v2q15_s = (v2q15) {0x1235, 0x4444}; + v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x9999, 0x5612}; + v2q15_b = (v2q15) {0x5612, 0x3333}; + if (little_endian) + v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac}; + else + v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66}; + v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x3589, 0x4444}; + if (little_endian) + q31_s = 0x44440000; + else + q31_s = 0x35890000; + q31_r = __builtin_mips_preceq_w_phl (v2q15_a); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x3589, 0x4444}; + if (little_endian) + q31_s = 0x35890000; + else + q31_s = 0x44440000; + q31_r = __builtin_mips_preceq_w_phr (v2q15_a); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x2b00, 0x1980}; + else + v2q15_s = (v2q15) {0x0900, 0x2b00}; + v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x0900, 0x2b00}; + else + v2q15_s = (v2q15) {0x2b00, 0x1980}; + v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x2b00, 0x1980}; + else + v2q15_s = (v2q15) {0x0900, 0x2b00}; + v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x0900, 0x2b00}; + else + v2q15_s = (v2q15) {0x2b00, 0x1980}; + v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x56, 0x33}; + else + v2q15_s = (v2q15) {0x12, 0x56}; + v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x12, 0x56}; + else + v2q15_s = (v2q15) {0x56, 0x33}; + v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x99, 0x33}; + else + v2q15_s = (v2q15) {0x12, 0x56}; + v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x12, 0x56}; + else + v2q15_s = (v2q15) {0x99, 0x33}; + v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0}; + v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_b = 1; + v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0}; + v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d0, 0x59e0}; + v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x2468, 0xacf0}; + v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d0, 0x7fff}; + v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x2468, 0x7fff}; + v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_shll_s_w (q31_a, 2); + if (q31_r != q31_s) + abort (); + + q31_a = 0x70000000; + i32_b = 1; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_shll_s_w (q31_a, i32_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e}; + v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_b = 1; + v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c}; + v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d, 0x159e}; + v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x91a, 0x2b3c}; + v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d, 0x159e}; + v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 3; + v2q15_s = (v2q15) {0x247, 0xacf}; + v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_s = 0x1c000000; + q31_r = __builtin_mips_shra_r_w (q31_a, 2); + if (q31_r != q31_s) + abort (); + + q31_a = 0x70000004; + i32_b = 3; + q31_s = 0x0e000001; + q31_r = __builtin_mips_shra_r_w (q31_a, i32_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + if (little_endian) + v2q15_s = (v2q15) {0xffff, 0x4444}; + else + v2q15_s = (v2q15) {0x6f89, 0x2222}; + v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + if (little_endian) + v2q15_s = (v2q15) {0x6f89, 0x2222}; + else + v2q15_s = (v2q15) {0xffff, 0x4444}; + v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x0fdd, 0x0b87}; + v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8000}; + v2q15_b = (v2q15) {0x8000, 0x8000}; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8000}; + v2q15_b = (v2q15) {0x8000, 0x8000}; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b); + if (q31_r != q31_s) + abort (); + +#ifndef __mips64 + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x22222f27; + else + a64_s = 0x222238d9; + a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x222238d9; + else + a64_s = 0x22222f27; + a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x2221f2fb; + else + a64_s = 0x2221e949; + a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x2221e949; + else + a64_s = 0x2221f2fb; + a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + a64_s = 0x8b877d00; + a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + a64_s = 0xffffffff7478a522LL; + a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + if (little_endian) + a64_s = 0xffffffff8b877d02LL; + else + a64_s = 0x7478a520; + a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + q31_b = 0x80000000; + q31_c = 0x80000000; + a64_s = 0x7fffffffffffffffLL; + a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + q31_b = 0x80000000; + q31_c = 0x80000000; + a64_s = 0x8000000000001112LL; + a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x1115; + else + a64_s = 0x80001110; + a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x80001110; + else + a64_s = 0x1115; + a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x1115; + else + a64_s = 0x7fffffff; + a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x7fffffff; + else + a64_s = 0x1115; + a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif + + i32_a = 0x12345678; + i32_s = 0x00001e6a; + i32_r = __builtin_mips_bitrev (i32_a); + if (i32_r != i32_s) + abort (); + + i32_a = 0x00000208; // pos is 8, size is 4 + __builtin_mips_wrdsp (i32_a, 31); + i32_a = 0x12345678; + i32_b = 0x87654321; + i32_s = 0x12345178; + i32_r = __builtin_mips_insv (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + v4i8_s = (v4i8) {1, 1, 1, 1}; + v4i8_r = __builtin_mips_repl_qb (1); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 99; + v4i8_s = (v4i8) {99, 99, 99, 99}; + v4i8_r = __builtin_mips_repl_qb (i32_a); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_s = (v2q15) {30, 30}; + v2q15_r = __builtin_mips_repl_ph (30); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + i32_a = 0x5612; + v2q15_s = (v2q15) {0x5612, 0x5612}; + v2q15_r = __builtin_mips_repl_ph (i32_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x03000000; + else + i32_s = 0x0c000000; + __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x04000000; + else + i32_s = 0x02000000; + __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x07000000; + else + i32_s = 0x0e000000; + __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x3; + else + i32_s = 0xc; + i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x4; + else + i32_s = 0x2; + i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x7; + else + i32_s = 0xe; + i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + __builtin_mips_wrdsp (0,31); // Clear all condition code bits. + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + i32_s = 0x01000000; + else + i32_s = 0x02000000; + __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + i32_s = 0x02000000; + else + i32_s = 0x01000000; + __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + i32_s = 0x03000000; + __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0a000000; // cc: 0000 1010 + __builtin_mips_wrdsp (i32_a, 31); + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87}; + if (little_endian) + v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78}; + else + v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87}; + v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0x02000000; // cc: 0000 0010 + __builtin_mips_wrdsp (i32_a, 31); + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x2143, 0x6587}; + if (little_endian) + v2q15_s = (v2q15) {0x2143, 0x5678}; + else + v2q15_s = (v2q15) {0x1234, 0x6587}; + v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + v2q15_s = (v2q15) {0x7856, 0x1234}; + else + v2q15_s = (v2q15) {0x5678, 0x1234}; + v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + +#ifndef __mips64 + a64_a = 0x1234567887654321LL; + i32_s = 0x88765432; + i32_r = __builtin_mips_extr_w (a64_a, 4); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_s = 0x56788766; + i32_r = __builtin_mips_extr_r_w (a64_a, 16); + if (i32_r != i32_s) + abort (); + + a64_a = 0x12345677fffffff8LL; + i32_s = 0x7fffffff; + i32_r = __builtin_mips_extr_rs_w (a64_a, 4); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_s = 0x7fff; + i32_r = __builtin_mips_extr_s_h (a64_a, 16); + if (i32_r != i32_s) + abort (); + + a64_a = 0x0000007887658321LL; + i32_b = 24; + i32_s = 0x7887; + i32_r = __builtin_mips_extr_s_h (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887654321LL; + i32_b = 4; + i32_s = 0x88765432; + i32_r = __builtin_mips_extr_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_b = 16; + i32_s = 0x56788766; + i32_r = __builtin_mips_extr_r_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x12345677fffffff8LL; + i32_b = 4; + i32_s = 0x7fffffff; + i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_s = 8; + i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 7; // size is 8. NOTE!! we should use 7 + i32_s = 0x87; + i32_r = __builtin_mips_extp (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_s = 8; + i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits + if (i32_r != i32_s) + abort (); + + i32_s = 0x0000021b; // pos is 27 + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 11; // size is 12. NOTE!!! We should use 11 + i32_s = 0x876; + i32_r = __builtin_mips_extpdp (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_s = 0x00000213; // pos is 19 + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887654321LL; + a64_s = 0x0012345678876543LL; + a64_r = __builtin_mips_shilo (a64_a, 8); + if (a64_r != a64_s) + abort (); + + a64_a = 0x1234567887654321LL; + i32_b = -16; + a64_s = 0x5678876543210000LL; + a64_r = __builtin_mips_shilo (a64_a, i32_b); + if (a64_r != a64_s) + abort (); + + i32_a = 0x0; + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 0x11112222; + a64_s = 0x8765432111112222LL; + a64_r = __builtin_mips_mthlip (a64_a, i32_b); + if (a64_r != a64_s) + abort (); + i32_s = 32; + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); +#endif + + i32_a = 0x1357a468; + __builtin_mips_wrdsp (i32_a, 63); + i32_s = 0x03572428; + i32_r = __builtin_mips_rddsp (63); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 37; + i32_s = 37; + i32_r = __builtin_mips_lbux (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 38; + if (little_endian) + i32_s = 0x2726; + else + i32_s = 0x2627; + i32_r = __builtin_mips_lhx (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 40; + if (little_endian) + i32_s = 0x2b2a2928; + else + i32_s = 0x28292a2b; + i32_r = __builtin_mips_lwx (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x00000220; // pos is 32, size is 4 + __builtin_mips_wrdsp (i32_a, 63); + i32_s = 1; + i32_r = __builtin_mips_bposge32 (); + if (i32_r != i32_s) + abort (); + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + i32_a = 0x80000000; + i32_b = 0x11112222; + a64_s = 0xF7776EEF00000000LL; + a64_r = __builtin_mips_mult (i32_a, i32_b); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + ui32_a = 0x80000000; + ui32_b = 0x11112222; + a64_s = 0x888911100000000LL; + a64_r = __builtin_mips_multu (ui32_a, ui32_b); + if (a64_r != a64_s) + abort (); +#endif +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c new file mode 100644 index 000000000..2a901bbf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c @@ -0,0 +1,30 @@ +/* Test MIPS32 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mdsp" } */ +/* { dg-final { scan-assembler "\taddq.ph\t" } } */ +/* { dg-final { scan-assembler "\taddu.qb\t" } } */ +/* { dg-final { scan-assembler "\tsubq.ph\t" } } */ +/* { dg-final { scan-assembler "\tsubu.qb\t" } } */ + +typedef char v4qi __attribute__ ((vector_size(4))); +typedef short v2hi __attribute__ ((vector_size(4))); + +NOMIPS16 v2hi add_v2hi (v2hi a, v2hi b) +{ + return a + b; +} + +NOMIPS16 v4qi add_v4qi (v4qi a, v4qi b) +{ + return a + b; +} + +NOMIPS16 v2hi sub_v2hi (v2hi a, v2hi b) +{ + return a - b; +} + +NOMIPS16 v4qi sub_v4qi (v4qi a, v4qi b) +{ + return a - b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c new file mode 100644 index 000000000..9aaf12018 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c @@ -0,0 +1,1160 @@ +/* Test MIPS32 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mgp32 -mdsp" } */ +/* { dg-final { scan-assembler "\taddq.ph\t" } } */ +/* { dg-final { scan-assembler "\taddq_s.ph\t" } } */ +/* { dg-final { scan-assembler "\taddq_s.w\t" } } */ +/* { dg-final { scan-assembler "\taddu.qb\t" } } */ +/* { dg-final { scan-assembler "\taddu_s.qb\t" } } */ +/* { dg-final { scan-assembler "\tsubq.ph\t" } } */ +/* { dg-final { scan-assembler "\tsubq_s.ph\t" } } */ +/* { dg-final { scan-assembler "\tsubq_s.w\t" } } */ +/* { dg-final { scan-assembler "\tsubu.qb\t" } } */ +/* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */ +/* { dg-final { scan-assembler "\taddsc\t" } } */ +/* { dg-final { scan-assembler "\taddwc\t" } } */ +/* { dg-final { scan-assembler "\tmodsub\t" } } */ +/* { dg-final { scan-assembler "\traddu.w.qb\t" } } */ +/* { dg-final { scan-assembler "\tabsq_s.ph\t" } } */ +/* { dg-final { scan-assembler "\tabsq_s.w\t" } } */ +/* { dg-final { scan-assembler "\tprecrq.qb.ph\t" } } */ +/* { dg-final { scan-assembler "\tprecrq.ph.w\t" } } */ +/* { dg-final { scan-assembler "\tprecrq_rs.ph.w\t" } } */ +/* { dg-final { scan-assembler "\tprecrqu_s.qb.ph\t" } } */ +/* { dg-final { scan-assembler "\tpreceq.w.phl\t" } } */ +/* { dg-final { scan-assembler "\tpreceq.w.phr\t" } } */ +/* { dg-final { scan-assembler "\tprecequ.ph.qbl\t" } } */ +/* { dg-final { scan-assembler "\tprecequ.ph.qbr\t" } } */ +/* { dg-final { scan-assembler "\tprecequ.ph.qbla\t" } } */ +/* { dg-final { scan-assembler "\tprecequ.ph.qbra\t" } } */ +/* { dg-final { scan-assembler "\tpreceu.ph.qbl\t" } } */ +/* { dg-final { scan-assembler "\tpreceu.ph.qbr\t" } } */ +/* { dg-final { scan-assembler "\tpreceu.ph.qbla\t" } } */ +/* { dg-final { scan-assembler "\tpreceu.ph.qbra\t" } } */ +/* { dg-final { scan-assembler "\tshllv?.qb\t" } } */ +/* { dg-final { scan-assembler "\tshllv?.ph\t" } } */ +/* { dg-final { scan-assembler "\tshllv?_s.ph\t" } } */ +/* { dg-final { scan-assembler "\tshllv?_s.w\t" } } */ +/* { dg-final { scan-assembler "\tshrlv?.qb\t" } } */ +/* { dg-final { scan-assembler "\tshrav?.ph\t" } } */ +/* { dg-final { scan-assembler "\tshrav?_r.ph\t" } } */ +/* { dg-final { scan-assembler "\tshrav?_r.w\t" } } */ +/* { dg-final { scan-assembler "\tmuleu_s.ph.qbl\t" } } */ +/* { dg-final { scan-assembler "\tmuleu_s.ph.qbr\t" } } */ +/* { dg-final { scan-assembler "\tmulq_rs.ph\t" } } */ +/* { dg-final { scan-assembler "\tmuleq_s.w.phl\t" } } */ +/* { dg-final { scan-assembler "\tmuleq_s.w.phr\t" } } */ +/* { dg-final { scan-assembler "\tdpau.h.qbl\t" } } */ +/* { dg-final { scan-assembler "\tdpau.h.qbr\t" } } */ +/* { dg-final { scan-assembler "\tdpsu.h.qbl\t" } } */ +/* { dg-final { scan-assembler "\tdpsu.h.qbr\t" } } */ +/* { dg-final { scan-assembler "\tdpaq_s.w.ph\t" } } */ +/* { dg-final { scan-assembler "\tdpsq_s.w.ph\t" } } */ +/* { dg-final { scan-assembler "\tmulsaq_s.w.ph\t" } } */ +/* { dg-final { scan-assembler "\tdpaq_sa.l.w\t" } } */ +/* { dg-final { scan-assembler "\tdpsq_sa.l.w\t" } } */ +/* { dg-final { scan-assembler "\tmaq_s.w.phl\t" } } */ +/* { dg-final { scan-assembler "\tmaq_s.w.phr\t" } } */ +/* { dg-final { scan-assembler "\tmaq_sa.w.phl\t" } } */ +/* { dg-final { scan-assembler "\tmaq_sa.w.phr\t" } } */ +/* { dg-final { scan-assembler "\tbitrev\t" } } */ +/* { dg-final { scan-assembler "\tinsv\t" } } */ +/* { dg-final { scan-assembler "\treplv?.qb\t" } } */ +/* { dg-final { scan-assembler "\trepl.ph\t" } } */ +/* { dg-final { scan-assembler "\treplv.ph\t" } } */ +/* { dg-final { scan-assembler "\tcmpu.eq.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmpu.lt.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmpu.le.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmpgu.eq.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmpgu.lt.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmpgu.le.qb\t" } } */ +/* { dg-final { scan-assembler "\tcmp.eq.ph\t" } } */ +/* { dg-final { scan-assembler "\tcmp.lt.ph\t" } } */ +/* { dg-final { scan-assembler "\tcmp.le.ph\t" } } */ +/* { dg-final { scan-assembler "\tpick.qb\t" } } */ +/* { dg-final { scan-assembler "\tpick.ph\t" } } */ +/* { dg-final { scan-assembler "\tpackrl.ph\t" } } */ +/* { dg-final { scan-assembler "\textrv?.w\t" } } */ +/* { dg-final { scan-assembler "\textrv?_s.h\t" } } */ +/* { dg-final { scan-assembler "\textrv?_r.w\t" } } */ +/* { dg-final { scan-assembler "\textrv?_rs.w\t" } } */ +/* { dg-final { scan-assembler "\textpv?\t" } } */ +/* { dg-final { scan-assembler "\textpdpv?\t" } } */ +/* { dg-final { scan-assembler "\tshilov?\t" } } */ +/* { dg-final { scan-assembler "\tmthlip\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmthi\t" } } */ +/* { dg-final { scan-assembler "\tmtlo\t" } } */ +/* { dg-final { scan-assembler "\twrdsp\t" } } */ +/* { dg-final { scan-assembler "\trddsp\t" } } */ +/* { dg-final { scan-assembler "\tlbux?\t" } } */ +/* { dg-final { scan-assembler "\tlhx?\t" } } */ +/* { dg-final { scan-assembler "\tlwx?\t" } } */ +/* { dg-final { scan-assembler "\tbposge32\t" } } */ +/* { dg-final { scan-assembler "\tmadd\t" } } */ +/* { dg-final { scan-assembler "\tmaddu\t" } } */ +/* { dg-final { scan-assembler "\tmsub\t" } } */ +/* { dg-final { scan-assembler "\tmsubu\t" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ + +#include <stdlib.h> +#include <stdio.h> + +typedef signed char v4i8 __attribute__ ((vector_size(4))); +typedef short v2q15 __attribute__ ((vector_size(4))); + +typedef int q31; +typedef int i32; +typedef unsigned int ui32; +typedef long long a64; + +NOMIPS16 void test_MIPS_DSP (void); + +char array[100]; +int little_endian; + +int main () +{ + int i; + + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + for (i = 0; i < 100; i++) + array[i] = i; + + test_MIPS_DSP (); + + exit (0); +} + +NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b) +{ + return __builtin_mips_addq_ph (a, b); +} + +NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b) +{ + return __builtin_mips_addu_qb (a, b); +} + +NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b) +{ + return __builtin_mips_subq_ph (a, b); +} + +NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b) +{ + return __builtin_mips_subu_qb (a, b); +} + +NOMIPS16 void test_MIPS_DSP () +{ + v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s; + v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s; + q31 q31_a,q31_b,q31_c,q31_r,q31_s; + /* To protect the multiplication-related tests from being optimized + at compile time. */ + volatile i32 i32_a,i32_b,i32_c,i32_r,i32_s; + volatile ui32 ui32_a,ui32_b,ui32_c; + a64 a64_a,a64_b,a64_c,a64_r,a64_s; + + void *ptr_a; + int r,s; + long long lr,ls; + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x81bd, 0x6789}; + v2q15_r = add_v2q15 (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x7fff, 0x6789}; + v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_b = 0x71234567; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_addq_s_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89}; + v4i8_r = add_v4i8 (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89}; + v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0xa2ab, 0x4567}; + v2q15_r = sub_v2q15 (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x8000, 0x4567}; + v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_b = 0x71234567; + q31_s = 0xfedcba99; + q31_r = __builtin_mips_subq_s_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67}; + v4i8_r = sub_v4i8 (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11}; + v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67}; + v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0xf5678900; + i32_b = 0x7abcdef0; + i32_s = 0x702467f0; + i32_r = __builtin_mips_addsc (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x75678900; + i32_b = 0x7abcdef0; + i32_s = 0xf02467f1; + i32_r = __builtin_mips_addwc (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0; + i32_b = 0x00000901; + i32_s = 9; + i32_r = __builtin_mips_modsub (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_s = 0x1f4; + i32_r = __builtin_mips_raddu_w_qb (v4i8_a); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8134}; + v2q15_s = (v2q15) {0x7fff, 0x7ecc}; + v2q15_r = __builtin_mips_absq_s_ph (v2q15_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = (q31) 0x80000000; + q31_s = (q31) 0x7fffffff; + q31_r = __builtin_mips_absq_s_w (q31_a); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x9999, 0x5612}; + v2q15_b = (v2q15) {0x5612, 0x3333}; + if (little_endian) + v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56}; + else + v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33}; + v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + q31_a = 0x12348678; + q31_b = 0x44445555; + if (little_endian) + v2q15_s = (v2q15) {0x4444, 0x1234}; + else + v2q15_s = (v2q15) {0x1234, 0x4444}; + v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x12348678; + q31_b = 0x44445555; + if (little_endian) + v2q15_s = (v2q15) {0x4444, 0x1235}; + else + v2q15_s = (v2q15) {0x1235, 0x4444}; + v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x9999, 0x5612}; + v2q15_b = (v2q15) {0x5612, 0x3333}; + if (little_endian) + v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac}; + else + v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66}; + v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x3589, 0x4444}; + if (little_endian) + q31_s = 0x44440000; + else + q31_s = 0x35890000; + q31_r = __builtin_mips_preceq_w_phl (v2q15_a); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x3589, 0x4444}; + if (little_endian) + q31_s = 0x35890000; + else + q31_s = 0x44440000; + q31_r = __builtin_mips_preceq_w_phr (v2q15_a); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x2b00, 0x1980}; + else + v2q15_s = (v2q15) {0x0900, 0x2b00}; + v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x0900, 0x2b00}; + else + v2q15_s = (v2q15) {0x2b00, 0x1980}; + v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x2b00, 0x1980}; + else + v2q15_s = (v2q15) {0x0900, 0x2b00}; + v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x0900, 0x2b00}; + else + v2q15_s = (v2q15) {0x2b00, 0x1980}; + v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x56, 0x33}; + else + v2q15_s = (v2q15) {0x12, 0x56}; + v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x12, 0x56}; + else + v2q15_s = (v2q15) {0x56, 0x33}; + v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x99, 0x33}; + else + v2q15_s = (v2q15) {0x12, 0x56}; + v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33}; + if (little_endian) + v2q15_s = (v2q15) {0x12, 0x56}; + else + v2q15_s = (v2q15) {0x99, 0x33}; + v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0}; + v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_b = 1; + v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0}; + v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d0, 0x59e0}; + v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x2468, 0xacf0}; + v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d0, 0x7fff}; + v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x2468, 0x7fff}; + v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_shll_s_w (q31_a, 2); + if (q31_r != q31_s) + abort (); + + q31_a = 0x70000000; + i32_b = 1; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_shll_s_w (q31_a, i32_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e}; + v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78}; + i32_b = 1; + v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c}; + v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d, 0x159e}; + v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 1; + v2q15_s = (v2q15) {0x91a, 0x2b3c}; + v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_s = (v2q15) {0x48d, 0x159e}; + v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + i32_b = 3; + v2q15_s = (v2q15) {0x247, 0xacf}; + v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x70000000; + q31_s = 0x1c000000; + q31_r = __builtin_mips_shra_r_w (q31_a, 2); + if (q31_r != q31_s) + abort (); + + q31_a = 0x70000004; + i32_b = 3; + q31_s = 0x0e000001; + q31_r = __builtin_mips_shra_r_w (q31_a, i32_b); + if (q31_r != q31_s) + abort (); + + v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + if (little_endian) + v2q15_s = (v2q15) {0xffff, 0x4444}; + else + v2q15_s = (v2q15) {0x6f89, 0x2222}; + v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + if (little_endian) + v2q15_s = (v2q15) {0x6f89, 0x2222}; + else + v2q15_s = (v2q15) {0xffff, 0x4444}; + v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x6f89, 0x1111}; + v2q15_s = (v2q15) {0x0fdd, 0x0b87}; + v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8000}; + v2q15_b = (v2q15) {0x8000, 0x8000}; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x8000, 0x8000}; + v2q15_b = (v2q15) {0x8000, 0x8000}; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b); + if (q31_r != q31_s) + abort (); + +#ifndef __mips64 + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x22222f27; + else + a64_s = 0x222238d9; + a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x222238d9; + else + a64_s = 0x22222f27; + a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x2221f2fb; + else + a64_s = 0x2221e949; + a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x22221111; + v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34}; + if (little_endian) + a64_s = 0x2221e949; + else + a64_s = 0x2221f2fb; + a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + a64_s = 0x8b877d00; + a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + a64_s = 0xffffffff7478a522LL; + a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x5678}; + v2q15_c = (v2q15) {0x8000, 0x1111}; + if (little_endian) + a64_s = 0xffffffff8b877d02LL; + else + a64_s = 0x7478a520; + a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + q31_b = 0x80000000; + q31_c = 0x80000000; + a64_s = 0x7fffffffffffffffLL; + a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + q31_b = 0x80000000; + q31_c = 0x80000000; + a64_s = 0x8000000000001112LL; + a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x1115; + else + a64_s = 0x80001110; + a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x80001110; + else + a64_s = 0x1115; + a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x1115; + else + a64_s = 0x7fffffff; + a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); + + a64_a = 0x00001111; + v2q15_b = (v2q15) {0x8000, 0x1}; + v2q15_c = (v2q15) {0x8000, 0x2}; + if (little_endian) + a64_s = 0x7fffffff; + else + a64_s = 0x1115; + a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif + + i32_a = 0x12345678; + i32_s = 0x00001e6a; + i32_r = __builtin_mips_bitrev (i32_a); + if (i32_r != i32_s) + abort (); + + i32_a = 0x00000208; // pos is 8, size is 4 + __builtin_mips_wrdsp (i32_a, 31); + i32_a = 0x12345678; + i32_b = 0x87654321; + i32_s = 0x12345178; + i32_r = __builtin_mips_insv (i32_a, i32_b); + if (i32_r != i32_s) + abort (); + + v4i8_s = (v4i8) {1, 1, 1, 1}; + v4i8_r = __builtin_mips_repl_qb (1); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 99; + v4i8_s = (v4i8) {99, 99, 99, 99}; + v4i8_r = __builtin_mips_repl_qb (i32_a); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_s = (v2q15) {30, 30}; + v2q15_r = __builtin_mips_repl_ph (30); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + i32_a = 0x5612; + v2q15_s = (v2q15) {0x5612, 0x5612}; + v2q15_r = __builtin_mips_repl_ph (i32_a); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x03000000; + else + i32_s = 0x0c000000; + __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x04000000; + else + i32_s = 0x02000000; + __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x07000000; + else + i32_s = 0x0e000000; + __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x3; + else + i32_s = 0xc; + i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x4; + else + i32_s = 0x2; + i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56}; + if (little_endian) + i32_s = 0x7; + else + i32_s = 0xe; + i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + + __builtin_mips_wrdsp (0,31); // Clear all condition code bits. + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + i32_s = 0x01000000; + else + i32_s = 0x02000000; + __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + i32_s = 0x02000000; + else + i32_s = 0x01000000; + __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + i32_s = 0x03000000; + __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b); + i32_r = __builtin_mips_rddsp (16); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0a000000; // cc: 0000 1010 + __builtin_mips_wrdsp (i32_a, 31); + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87}; + if (little_endian) + v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78}; + else + v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87}; + v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0x02000000; // cc: 0000 0010 + __builtin_mips_wrdsp (i32_a, 31); + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x2143, 0x6587}; + if (little_endian) + v2q15_s = (v2q15) {0x2143, 0x5678}; + else + v2q15_s = (v2q15) {0x1234, 0x6587}; + v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1234, 0x7856}; + if (little_endian) + v2q15_s = (v2q15) {0x7856, 0x1234}; + else + v2q15_s = (v2q15) {0x5678, 0x1234}; + v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + +#ifndef __mips64 + a64_a = 0x1234567887654321LL; + i32_s = 0x88765432; + i32_r = __builtin_mips_extr_w (a64_a, 4); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_s = 0x56788766; + i32_r = __builtin_mips_extr_r_w (a64_a, 16); + if (i32_r != i32_s) + abort (); + + a64_a = 0x12345677fffffff8LL; + i32_s = 0x7fffffff; + i32_r = __builtin_mips_extr_rs_w (a64_a, 4); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_s = 0x7fff; + i32_r = __builtin_mips_extr_s_h (a64_a, 16); + if (i32_r != i32_s) + abort (); + + a64_a = 0x0000007887658321LL; + i32_b = 24; + i32_s = 0x7887; + i32_r = __builtin_mips_extr_s_h (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887654321LL; + i32_b = 4; + i32_s = 0x88765432; + i32_r = __builtin_mips_extr_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887658321LL; + i32_b = 16; + i32_s = 0x56788766; + i32_r = __builtin_mips_extr_r_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + a64_a = 0x12345677fffffff8LL; + i32_b = 4; + i32_s = 0x7fffffff; + i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_s = 8; + i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 7; // size is 8. NOTE!! we should use 7 + i32_s = 0x87; + i32_r = __builtin_mips_extp (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_s = 8; + i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits + if (i32_r != i32_s) + abort (); + + i32_s = 0x0000021b; // pos is 27 + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); + + i32_a = 0x0000021f; // pos is 31 + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 11; // size is 12. NOTE!!! We should use 11 + i32_s = 0x876; + i32_r = __builtin_mips_extpdp (a64_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_s = 0x00000213; // pos is 19 + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); + + a64_a = 0x1234567887654321LL; + a64_s = 0x0012345678876543LL; + a64_r = __builtin_mips_shilo (a64_a, 8); + if (a64_r != a64_s) + abort (); + + a64_a = 0x1234567887654321LL; + i32_b = -16; + a64_s = 0x5678876543210000LL; + a64_r = __builtin_mips_shilo (a64_a, i32_b); + if (a64_r != a64_s) + abort (); + + i32_a = 0x0; + __builtin_mips_wrdsp (i32_a, 31); + a64_a = 0x1234567887654321LL; + i32_b = 0x11112222; + a64_s = 0x8765432111112222LL; + a64_r = __builtin_mips_mthlip (a64_a, i32_b); + if (a64_r != a64_s) + abort (); + i32_s = 32; + i32_r = __builtin_mips_rddsp (31); + if (i32_r != i32_s) + abort (); +#endif + + i32_a = 0x1357a468; + __builtin_mips_wrdsp (i32_a, 63); + i32_s = 0x03572428; + i32_r = __builtin_mips_rddsp (63); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 37; + i32_s = 37; + i32_r = __builtin_mips_lbux (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 38; + if (little_endian) + i32_s = 0x2726; + else + i32_s = 0x2627; + i32_r = __builtin_mips_lhx (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + ptr_a = &array; + i32_b = 40; + if (little_endian) + i32_s = 0x2b2a2928; + else + i32_s = 0x28292a2b; + i32_r = __builtin_mips_lwx (ptr_a, i32_b); + if (i32_r != i32_s) + abort (); + + i32_a = 0x00000220; // pos is 32, size is 4 + __builtin_mips_wrdsp (i32_a, 63); + i32_s = 1; + i32_r = __builtin_mips_bposge32 (); + if (i32_r != i32_s) + abort (); + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + i32_a = 0x80000000; + i32_b = 0x11112222; + a64_s = 0xF7776EEF00000000LL; + a64_r = __builtin_mips_mult (i32_a, i32_b); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + ui32_a = 0x80000000; + ui32_b = 0x11112222; + a64_s = 0x888911100000000LL; + a64_r = __builtin_mips_multu (ui32_a, ui32_b); + if (a64_r != a64_s) + abort (); +#endif +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c new file mode 100644 index 000000000..9501e9cbe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c @@ -0,0 +1,12 @@ +/* Test MIPS32 DSP REV 2 instructions */ +/* { dg-do compile } */ +/* { dg-options "-mdspr2" } */ +/* { dg-final { scan-assembler "\tmul.ph\t" } } */ + +typedef short v2hi __attribute__ ((vector_size(4))); + +NOMIPS16 v2hi mul_v2hi (v2hi a, v2hi b) +{ + return a * b; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c new file mode 100644 index 000000000..1f7e92873 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c @@ -0,0 +1,541 @@ +/* Test MIPS32 DSP REV 2 instructions */ +/* { dg-do run } */ +/* { dg-options "-mdspr2" } */ + +typedef signed char v4q7 __attribute__ ((vector_size(4))); +typedef signed char v4i8 __attribute__ ((vector_size(4))); +typedef short v2q15 __attribute__ ((vector_size(4))); +typedef short v2i16 __attribute__ ((vector_size(4))); +typedef int q31; +typedef int i32; +typedef unsigned int ui32; +typedef long long a64; + +void abort (void); + +NOMIPS16 void test_MIPS_DSPR2 (void); + +int little_endian; + +int main () +{ + union { long long ll; int i[2]; } endianness_test; + endianness_test.ll = 1; + little_endian = endianness_test.i[0]; + + test_MIPS_DSPR2 (); + + return 0; +} + +NOMIPS16 void test_MIPS_DSPR2 () +{ + v4q7 v4q7_a,v4q7_b,v4q7_c,v4q7_r,v4q7_s; + v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s; + v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s; + v2i16 v2i16_a,v2i16_b,v2i16_c,v2i16_r,v2i16_s; + q31 q31_a,q31_b,q31_c,q31_r,q31_s; + i32 i32_a,i32_b,i32_c,i32_r,i32_s; + ui32 ui32_a,ui32_b,ui32_c,ui32_r,ui32_s; + a64 a64_a,a64_b,a64_c,a64_r,a64_s; + + int r,s; + + v4q7_a = (v4i8) {0x81, 0xff, 0x80, 0x23}; + v4q7_s = (v4i8) {0x7f, 0x01, 0x7f, 0x23}; + v4q7_r = __builtin_mips_absq_s_qb (v4q7_a); + r = (int) v4q7_r; + s = (int) v4q7_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0xffff, 0x2468}; + v2i16_b = (v2i16) {0x1234, 0x1111}; + v2i16_s = (v2i16) {0x1233, 0x3579}; + v2i16_r = __builtin_mips_addu_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0xffff, 0x2468}; + v2i16_b = (v2i16) {0x1234, 0x1111}; + v2i16_s = (v2i16) {0xffff, 0x3579}; + v2i16_r = __builtin_mips_addu_s_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff}; + v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff}; + v4i8_s = (v4i8) {0x11, 0x2a, 0x66, 0xff}; + v4i8_r = __builtin_mips_adduh_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff}; + v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff}; + v4i8_s = (v4i8) {0x11, 0x2b, 0x66, 0xff}; + v4i8_r = __builtin_mips_adduh_r_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0x12345678; + i32_b = 0x87654321; + i32_s = 0x56784321; + i32_r = __builtin_mips_append (i32_a, i32_b, 16); + if (i32_r != i32_s) + abort (); + + i32_a = 0x12345678; + i32_b = 0x87654321; + i32_s = 0x78876543; + i32_r = __builtin_mips_balign (i32_a, i32_b, 3); + if (i32_r != i32_s) + abort (); + + __builtin_mips_wrdsp (0, 63); + v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44}; + v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44}; + if (little_endian) + i32_s = 0xd; + else + i32_s = 0xb; + i32_r = __builtin_mips_cmpgdu_eq_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + i32_r = __builtin_mips_rddsp (16); + if (little_endian) + i32_s = 0x0d000000; + else + i32_s = 0x0b000000; + if (i32_r != i32_s) + abort (); + + __builtin_mips_wrdsp (0, 63); + v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44}; + v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44}; + if (little_endian) + i32_s = 0x2; + else + i32_s = 0x4; + i32_r = __builtin_mips_cmpgdu_lt_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + i32_r = __builtin_mips_rddsp (16); + if (little_endian) + i32_s = 0x02000000; + else + i32_s = 0x04000000; + if (i32_r != i32_s) + abort (); + + __builtin_mips_wrdsp (0, 63); + v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54}; + v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44}; + if (little_endian) + i32_s = 0x7; + else + i32_s = 0xe; + i32_r = __builtin_mips_cmpgdu_le_qb (v4i8_a, v4i8_b); + if (i32_r != i32_s) + abort (); + i32_r = __builtin_mips_rddsp (16); + if (little_endian) + i32_s = 0x07000000; + else + i32_s = 0x0e000000; + if (i32_r != i32_s) + abort (); + +#ifndef __mips64 + a64_a = 0x12345678; + v2i16_b = (v2i16) {0xffff, 0x1555}; + v2i16_c = (v2i16) {0x1234, 0x3322}; + a64_s = 0x1677088e; + a64_r = __builtin_mips_dpa_w_ph (a64_a, v2i16_b, v2i16_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + v2i16_b = (v2i16) {0xffff, 0x1555}; + v2i16_c = (v2i16) {0x1234, 0x3322}; + a64_s = 0x0df1a462; + a64_r = __builtin_mips_dps_w_ph (a64_a, v2i16_b, v2i16_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_s = 0x0888911112345678LL; + a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_s = 0xF7776EEF12345678LL; + a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c); + if (a64_r != a64_s) + abort (); +#endif + + v2i16_a = (v2i16) {0xffff, 0x2468}; + v2i16_b = (v2i16) {0x1234, 0x1111}; + v2i16_s = (v2i16) {0xedcc, 0x52e8}; + v2i16_r = __builtin_mips_mul_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0x8000, 0x7fff}; + v2i16_b = (v2i16) {0x1234, 0x1111}; + v2i16_s = (v2i16) {0x8000, 0x7fff}; + v2i16_r = __builtin_mips_mul_s_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + q31_a = 0x80000000; + q31_b = 0x80000000; + q31_s = 0x7fffffff; + q31_r = __builtin_mips_mulq_rs_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0xffff, 0x8000}; + v2q15_b = (v2q15) {0x1111, 0x8000}; + v2q15_s = (v2q15) {0xffff, 0x7fff}; + v2q15_r = __builtin_mips_mulq_s_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x00000002; + q31_b = 0x80000000; + q31_s = 0xfffffffe; + q31_r = __builtin_mips_mulq_s_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + +#ifndef __mips64 + a64_a = 0x19848419; + v2i16_b = (v2i16) {0xffff, 0x8000}; + v2i16_c = (v2i16) {0x1111, 0x8000}; + if (little_endian) + a64_s = 0x5984952a; + else + a64_s = 0xffffffffd9847308LL; + a64_r = __builtin_mips_mulsa_w_ph (a64_a, v2i16_b, v2i16_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + i32_a = 0x80000000; + i32_b = 0x11112222; + a64_s = 0xF7776EEF00000000LL; + a64_r = __builtin_mips_mult (i32_a, i32_b); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + ui32_a = 0x80000000; + ui32_b = 0x11112222; + a64_s = 0x888911100000000LL; + a64_r = __builtin_mips_multu (ui32_a, ui32_b); + if (a64_r != a64_s) + abort (); +#endif + + v2i16_a = (v2i16) {0x1234, 0x5678}; + v2i16_b = (v2i16) {0x2233, 0x5566}; + if (little_endian) + v4i8_s = (v4i8) {0x33, 0x66, 0x34, 0x78}; + else + v4i8_s = (v4i8) {0x34, 0x78, 0x33, 0x66}; + v4i8_r = __builtin_mips_precr_qb_ph (v2i16_a, v2i16_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_a = 0x12345678; + i32_b = 0x33334444; + if (little_endian) + v2i16_s = (v2i16) {0x3444, 0x4567}; + else + v2i16_s = (v2i16) {0x4567, 0x3444}; + v2i16_r = __builtin_mips_precr_sra_ph_w (i32_a, i32_b, 4); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + i32_a = 0x12345678; + i32_b = 0x33334444; + if (little_endian) + v2i16_s = (v2i16) {0x3444, 0x4568}; + else + v2i16_s = (v2i16) {0x4568, 0x3444}; + v2i16_r = __builtin_mips_precr_sra_r_ph_w (i32_a, i32_b, 4); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + i32_a = 0x12345678; + i32_b = 0x87654321; + i32_s = 0x43211234; + i32_r = __builtin_mips_prepend (i32_a, i32_b, 16); + if (i32_r != i32_s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99}; + v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc}; + v4i8_r = __builtin_mips_shra_qb (v4i8_a, 1); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99}; + v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd}; + v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, 1); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_b = 1; + v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99}; + v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc}; + v4i8_r = __builtin_mips_shra_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + i32_b = 1; + v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99}; + v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd}; + v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, i32_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0x1357, 0x2468}; + v2i16_s = (v2i16) {0x0135, 0x0246}; + v2i16_r = __builtin_mips_shrl_ph (v2i16_a, 4); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + i32_b = 8; + v2i16_a = (v2i16) {0x1357, 0x2468}; + v2i16_s = (v2i16) {0x0013, 0x0024}; + v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0x1357, 0x4455}; + v2i16_b = (v2i16) {0x3333, 0x4444}; + v2i16_s = (v2i16) {0xe024, 0x0011}; + v2i16_r = __builtin_mips_subu_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v2i16_a = (v2i16) {0x1357, 0x4455}; + v2i16_b = (v2i16) {0x3333, 0x4444}; + v2i16_s = (v2i16) {0x0000, 0x0011}; + v2i16_r = __builtin_mips_subu_s_ph (v2i16_a, v2i16_b); + r = (int) v2i16_r; + s = (int) v2i16_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66}; + v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff}; + v4i8_s = (v4i8) {0xcd ,0x17, 0xe8, 0xb3}; + v4i8_r = __builtin_mips_subuh_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66}; + v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff}; + v4i8_s = (v4i8) {0xcd ,0x18, 0xe8, 0xb4}; + v4i8_r = __builtin_mips_subuh_r_qb (v4i8_a, v4i8_b); + r = (int) v4i8_r; + s = (int) v4i8_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x3334, 0x4444}; + v2q15_b = (v2q15) {0x1111, 0x2222}; + v2q15_s = (v2q15) {0x2222, 0x3333}; + v2q15_r = __builtin_mips_addqh_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x3334, 0x4444}; + v2q15_b = (v2q15) {0x1111, 0x2222}; + v2q15_s = (v2q15) {0x2223, 0x3333}; + v2q15_r = __builtin_mips_addqh_r_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x11111112; + q31_b = 0x99999999; + q31_s = 0xd5555555; + q31_r = __builtin_mips_addqh_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + q31_a = 0x11111112; + q31_b = 0x99999999; + q31_s = 0xd5555556; + q31_r = __builtin_mips_addqh_r_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + v2q15_a = (v2q15) {0x3334, 0x4444}; + v2q15_b = (v2q15) {0x1111, 0x2222}; + v2q15_s = (v2q15) {0x1111, 0x1111}; + v2q15_r = __builtin_mips_subqh_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + v2q15_a = (v2q15) {0x3334, 0x4444}; + v2q15_b = (v2q15) {0x1111, 0x2222}; + v2q15_s = (v2q15) {0x1112, 0x1111}; + v2q15_r = __builtin_mips_subqh_r_ph (v2q15_a, v2q15_b); + r = (int) v2q15_r; + s = (int) v2q15_s; + if (r != s) + abort (); + + q31_a = 0x11111112; + q31_b = 0x99999999; + q31_s = 0x3bbbbbbc; + q31_r = __builtin_mips_subqh_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + + q31_a = 0x11111112; + q31_b = 0x99999999; + q31_s = 0x3bbbbbbd; + q31_r = __builtin_mips_subqh_r_w (q31_a, q31_b); + if (q31_r != q31_s) + abort (); + +#ifndef __mips64 + a64_a = 0x1111222212345678LL; + v2i16_b = (v2i16) {0x1, 0x2}; + v2i16_c = (v2i16) {0x3, 0x4}; + a64_s = 0x1111222212345682LL; + a64_r = __builtin_mips_dpax_w_ph (a64_a, v2i16_b, v2i16_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x9999111112345678LL; + v2i16_b = (v2i16) {0x1, 0x2}; + v2i16_c = (v2i16) {0x3, 0x4}; + a64_s = 0x999911111234566eLL; + a64_r = __builtin_mips_dpsx_w_ph (a64_a, v2i16_b, v2i16_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x70000000; + v2q15_b = (v2q15) {0x4000, 0x2000}; + v2q15_c = (v2q15) {0x2000, 0x4000}; + a64_s = 0x98000000; + a64_r = __builtin_mips_dpaqx_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x70000000; + v2q15_b = (v2q15) {0x4000, 0x2000}; + v2q15_c = (v2q15) {0x2000, 0x4000}; + a64_s = 0x7fffffff; + a64_r = __builtin_mips_dpaqx_sa_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0x70000000; + v2q15_b = (v2q15) {0x4000, 0x2000}; + v2q15_c = (v2q15) {0x2000, 0x4000}; + a64_s = 0x48000000; + a64_r = __builtin_mips_dpsqx_s_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif + +#ifndef __mips64 + a64_a = 0xFFFFFFFF80000000LL; + v2q15_b = (v2q15) {0x4000, 0x2000}; + v2q15_c = (v2q15) {0x2000, 0x4000}; + a64_s = 0xFFFFFFFF80000000LL; + a64_r = __builtin_mips_dpsqx_sa_w_ph (a64_a, v2q15_b, v2q15_c); + if (a64_r != a64_s) + abort (); +#endif +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c new file mode 100644 index 000000000..899ac0100 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=32 -mfp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmthc1\t" } } */ +/* { dg-final { scan-assembler "\tmfhc1\t" } } */ + +NOMIPS16 double func1 (long long a) +{ + return a; +} + +NOMIPS16 long long func2 (double b) +{ + return b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c new file mode 100644 index 000000000..02e616657 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c @@ -0,0 +1,11 @@ +/* Test MIPS64 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mgp64 -mdsp" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler "\tldx\t" } } */ + +NOMIPS16 signed long long test (signed long long *a, int index) +{ + return a[index]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c new file mode 100644 index 000000000..b7f3bc8f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c @@ -0,0 +1,10 @@ +/* Test MIPS64 DSP instructions */ +/* { dg-do compile } */ +/* { dg-options "-mgp64 -mdsp" } */ + +/* { dg-final { scan-assembler "\tldx\t" } } */ + +NOMIPS16 signed long long test (signed long long *a, int index) +{ + return __builtin_mips_ldx (a, index); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c new file mode 100644 index 000000000..3d07939ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-pg -mmcount-ra-address -mabi=64" } */ +/* { dg-final { scan-assembler "\tmove\t\\\$12,\\\$0" } } */ +NOMIPS16 int bazl(int i) +{ + return i + 2; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c new file mode 100644 index 000000000..34b30d987 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-pg -mmcount-ra-address -mabi=64 -mno-abicalls" } */ +/* { dg-skip-if "requiring a specific frame layout makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdla\t\\\$12,8\\(\\\$sp\\)" } } */ +int foo (int); +NOMIPS16 int bar (int i) +{ + return foo (i) + 2; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c new file mode 100644 index 000000000..17bcb76be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-pg -mmcount-ra-address -mabi=64 -mno-abicalls" } */ +/* { dg-skip-if "requiring a specific frame layout makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdla\t\\\$12,200008\\(\\\$sp\\)" } } */ +int foo (int *); +NOMIPS16 int bar(int i) +{ + int big[50000]; + return foo (big) + 2; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c new file mode 100644 index 000000000..b3fe188d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "isa>=4" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmovz\t" } } */ +/* { dg-final { scan-assembler "\tmovn\t" } } */ + +void ext_int (int); + +NOMIPS16 int +sub1 (int i, int j, int k) +{ + ext_int (k ? i : j); +} + +NOMIPS16 int +sub2 (int i, int j, long l) +{ + ext_int (!l ? i : j); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c new file mode 100644 index 000000000..2638d51fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "isa>=4" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmovz\t" } } */ +/* { dg-final { scan-assembler "\tmovn\t" } } */ + +void ext_long (long); + +NOMIPS16 long +sub4 (long i, long j, long k) +{ + ext_long (k ? i : j); +} + +NOMIPS16 long +sub5 (long i, long j, int k) +{ + ext_long (!k ? i : j); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c new file mode 100644 index 000000000..f356465c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "isa>=4 -mhard-float" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmovt\t" } } */ +/* { dg-final { scan-assembler "\tmovf\t" } } */ +/* { dg-final { scan-assembler "\tmovz.s\t" } } */ +/* { dg-final { scan-assembler "\tmovn.s\t" } } */ +/* { dg-final { scan-assembler "\tmovt.s\t" } } */ +/* { dg-final { scan-assembler "\tmovz.d\t" } } */ +/* { dg-final { scan-assembler "\tmovn.d\t" } } */ +/* { dg-final { scan-assembler "\tmovf.d\t" } } */ + +void ext_int (int); +void ext_long (long); +void ext_float (float); +void ext_double (double); + +NOMIPS16 int +sub3 (int i, int j, float f) +{ + ext_int (f ? i : j); +} + +NOMIPS16 long +sub6 (long i, long j, float f) +{ + ext_long (!f ? i : j); +} + +NOMIPS16 float +sub7 (float f, float g, int i) +{ + ext_float (i ? f : g); +} + +NOMIPS16 float +sub8 (float f, float g, long l) +{ + ext_float (!l ? f : g); +} + +NOMIPS16 float +sub9 (float f, float g, float h) +{ + ext_float (h ? f : g); +} + +NOMIPS16 double +suba (double f, double g, int i) +{ + ext_double (i ? f : g); +} + +NOMIPS16 double +subb (double f, double g, long l) +{ + ext_double (!l ? f : g); +} + +NOMIPS16 double +subc (double f, double g, double h) +{ + ext_double (!h ? f : g); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c new file mode 100644 index 000000000..9a222bfda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5400 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsac\t\\\$0," 2 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return z - (long long) y * x; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c new file mode 100644 index 000000000..c0923cd11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return z - (long long) y * x; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c new file mode 100644 index 000000000..aedd04302 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return z - (long long) y * x; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c new file mode 100644 index 000000000..84cb5fe33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsub\t\\\$ac" 2 } } */ + +NOMIPS16 long long +f1 (int x, int y, long long z) +{ + return z - (long long) y * x; +} + +NOMIPS16 long long +f2 (int x, int y, long long z) +{ + long long t = (long long) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c new file mode 100644 index 000000000..eba104c7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c @@ -0,0 +1,9 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsub\t" 4 } } */ +/* { dg-final { scan-assembler-not "\tmtlo\t" } } */ +/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */ + +NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3]; } +NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4]; } +NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4] * a[5]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c new file mode 100644 index 000000000..32411e61f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c @@ -0,0 +1,7 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmsub\t" } } */ +/* { dg-final { scan-assembler "\tmul\t" } } */ +/* { dg-final { scan-assembler "\tsubu\t" } } */ + +NOMIPS16 void f1 (int *a) { a[0] = a[0] - a[1] * a[2]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c new file mode 100644 index 000000000..ee049876e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-skip-if "requires -fira-region=all or =mixed" { *-*-* } { "-Os" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +/* { dg-final { scan-assembler "\tmsub\t" } } */ + +NOMIPS16 int +f1 (int *a, int *b, int n) +{ + int x, i; + + x = 100; + for (i = 0; i < n; i++) + x -= a[i] * b[i]; + return x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c new file mode 100644 index 000000000..a66307f10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c @@ -0,0 +1,16 @@ +/* { dg-options "-march=5kc" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmul\t" } } */ +/* { dg-final { scan-assembler-not "\tmsub\t" } } */ +/* { dg-final { scan-assembler-not "\tmtlo\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +NOMIPS16 int +f2 (int x, int y, int z) +{ + asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", + "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", + "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", + "$31"); + return x - y * z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c new file mode 100644 index 000000000..e1146f8bc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5400 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsacu\t\\\$0," 2 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return z - (ull) y * x; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c new file mode 100644 index 000000000..642d12394 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return z - (ull) y * x; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c new file mode 100644 index 000000000..2e936ebe0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return z - (ull) y * x; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c new file mode 100644 index 000000000..a4f611860 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* This test requires widening_mul */ +/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tmsubu\t\\\$ac" 2 } } */ + +typedef unsigned int ui; +typedef unsigned long long ull; + +NOMIPS16 ull +f1 (ui x, ui y, ull z) +{ + return z - (ull) y * x; +} + +NOMIPS16 ull +f2 (ui x, ui y, ull z) +{ + ull t = (ull) x * y; + int temp = 5; + if (temp == 5) + z -= t; + return z; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c new file mode 100644 index 000000000..0997fd934 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c @@ -0,0 +1,10 @@ +/* { dg-final { scan-assembler "\t.globl\tf7" } } */ +/* { dg-final { scan-assembler "\tsll\t" } } */ +/* { dg-final { scan-assembler "\tsubu\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +int +f7(int x) +{ + return x * 7; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c new file mode 100644 index 000000000..4cc2224df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c @@ -0,0 +1,10 @@ +/* { dg-final { scan-assembler "\t.globl\tf9" } } */ +/* { dg-final { scan-assembler "\tsll\t" } } */ +/* { dg-final { scan-assembler "\taddu\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +int +f9(int x) +{ + return x * 9; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c new file mode 100644 index 000000000..552d8c99d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c @@ -0,0 +1,12 @@ +/* { dg-final { scan-assembler "\t.globl\tf15" } } */ +/* { dg-final { scan-assembler "\tsll\t" } } */ +/* { dg-final { scan-assembler "\tsubu\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +int +f15(int x) +{ + return x * 15; +} + +
\ No newline at end of file diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c new file mode 100644 index 000000000..7694d2c03 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c @@ -0,0 +1,11 @@ +/* { dg-final { scan-assembler "\t.globl\tf17" } } */ +/* { dg-final { scan-assembler "\tsll\t" } } */ +/* { dg-final { scan-assembler "\taddu\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "\tmul\t" } } */ +int +f17(int x) +{ + return x * 17; +} +
\ No newline at end of file diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c new file mode 100644 index 000000000..1038797f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c @@ -0,0 +1,16 @@ +/* For SI->DI widening multiplication we should use DINS to combine the two + halves. For Octeon use DMUL with explicit widening. */ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 isa_rev>=2 forbid_cpu=octeon.* -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdins\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ +/* { dg-final { scan-assembler-not "\tor\t" } } */ + +NOMIPS16 unsigned long long +f (unsigned int i, unsigned int j) +{ + i++; + return (unsigned long long) i * j; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c new file mode 100644 index 000000000..c479ebbc5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c @@ -0,0 +1,15 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c new file mode 100644 index 000000000..8b26c1de7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c @@ -0,0 +1,15 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c new file mode 100644 index 000000000..bf8d36c76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c new file mode 100644 index 000000000..beb6ab943 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c new file mode 100644 index 000000000..e3cbd75bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c @@ -0,0 +1,16 @@ +/* { dg-options "-mgp32 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c new file mode 100644 index 000000000..da47bd292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c @@ -0,0 +1,16 @@ +/* { dg-options "-mgp32 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c new file mode 100644 index 000000000..3e9b3785b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c @@ -0,0 +1,15 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp32 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c new file mode 100644 index 000000000..84baff8cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c @@ -0,0 +1,14 @@ +/* { dg-options "-mgp32 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return ((DI) x * y) >> 32; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c new file mode 100644 index 000000000..52487f30d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp32 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c new file mode 100644 index 000000000..11cdb17c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp32 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 SI +f (SI x, SI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c new file mode 100644 index 000000000..77be31162 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c @@ -0,0 +1,14 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmult\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ + +typedef int TI __attribute__((mode(TI))); +typedef int DI __attribute__((mode(DI))); + +MIPS16 TI +f (DI x, DI y) +{ + return (TI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c new file mode 100644 index 000000000..e46978bc4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c @@ -0,0 +1,14 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmultu\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ + +typedef unsigned int TI __attribute__((mode(TI))); +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 TI +f (DI x, DI y) +{ + return (TI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c new file mode 100644 index 000000000..939ca5cdb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c @@ -0,0 +1,15 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmult\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +typedef int TI __attribute__((mode(TI))); +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return ((TI) x * y) >> 64; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c new file mode 100644 index 000000000..efb06af85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c @@ -0,0 +1,14 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmultu\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +typedef unsigned int TI __attribute__((mode(TI))); +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return ((TI) x * y) >> 64; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c new file mode 100644 index 000000000..82d4f5d45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c new file mode 100644 index 000000000..35b074980 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c @@ -0,0 +1,13 @@ +/* { dg-options "-mgp64 (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdmultu?\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); + +MIPS16 DI +f (DI x, DI y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c new file mode 100644 index 000000000..18dce2013 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c @@ -0,0 +1,17 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmult\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */ +/* { dg-final { scan-assembler "\tdsrl\t" } } */ + +typedef int DI __attribute__((mode(DI))); +typedef int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c new file mode 100644 index 000000000..59d450ab2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c @@ -0,0 +1,17 @@ +/* This test requires widening_mul */ +/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tmultu\t" } } */ +/* { dg-final { scan-assembler "\tmflo\t" } } */ +/* { dg-final { scan-assembler "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */ +/* { dg-final { scan-assembler "\tdsrl\t" } } */ + +typedef unsigned int DI __attribute__((mode(DI))); +typedef unsigned int SI __attribute__((mode(SI))); + +MIPS16 DI +f (SI x, SI y) +{ + return (DI) x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c new file mode 100644 index 000000000..fc776e5fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=2008 -EB" } */ + +double d = __builtin_nan (""); + +/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2146959360\n\t\\.word\t0\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c new file mode 100644 index 000000000..359ca221e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=legacy -EB" } */ + +double d = __builtin_nan (""); + +/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2146959359\n\t\\.word\t(?:-1|4294967295)\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c new file mode 100644 index 000000000..fb5e28588 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=2008 -EB" } */ + +float f = __builtin_nanf (""); + +/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2143289344\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c new file mode 100644 index 000000000..6db278ef1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=legacy -EB" } */ + +float f = __builtin_nanf (""); + +/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2143289343\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c new file mode 100644 index 000000000..2da0c2df4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=2008 -EB" } */ + +double ds = __builtin_nans (""); + +/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2146697216\n\t\\.word\t0\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c new file mode 100644 index 000000000..0ce4226b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=legacy -EB" } */ + +double ds = __builtin_nans (""); + +/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2147483647\n\t\\.word\t(?:-1|4294967295)\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c new file mode 100644 index 000000000..d368add19 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=2008 -EB" } */ + +float fs = __builtin_nansf (""); + +/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2141192192\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c new file mode 100644 index 000000000..8a518670c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mnan=legacy -EB" } */ + +float fs = __builtin_nansf (""); + +/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */ +/* { dg-final { scan-assembler "\t\\.word\t2147483647\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c new file mode 100644 index 000000000..ac0cc1ef7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-mlong-calls addressing=absolute" } */ + +extern int long_call_func () __attribute__((long_call)); +extern int far_func () __attribute__((far)); +extern int near_func () __attribute__((near)); +extern int normal_func (); + +int test () +{ + return (long_call_func () + + far_func () + + near_func () + + normal_func ()); +} + +/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\tjal\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c new file mode 100644 index 000000000..c954b444c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-long-calls addressing=absolute" } */ + +extern int long_call_func () __attribute__((long_call)); +extern int far_func () __attribute__((far)); +extern int near_func () __attribute__((near)); +extern int normal_func (); + +int test () +{ + return (long_call_func () + + far_func () + + near_func () + + normal_func ()); +} + +/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\tjal\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\tjal\tnormal_func\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c new file mode 100644 index 000000000..d4d48b1ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mlong-calls addressing=absolute" } */ + +NOMIPS16 extern int long_call_func () __attribute__((long_call)); +NOMIPS16 extern int far_func () __attribute__((far)); +NOMIPS16 extern int near_func () __attribute__((near)); +NOMIPS16 extern int normal_func (); + +NOMIPS16 int test1 () { return long_call_func (); } +NOMIPS16 int test2 () { return far_func (); } +NOMIPS16 int test3 () { return near_func (); } +NOMIPS16 int test4 () { return normal_func (); } + +/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\tj(|al)\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c new file mode 100644 index 000000000..0ea07b062 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-long-calls addressing=absolute" } */ + +NOMIPS16 extern int long_call_func () __attribute__((long_call)); +NOMIPS16 extern int far_func () __attribute__((far)); +NOMIPS16 extern int near_func () __attribute__((near)); +NOMIPS16 extern int normal_func (); + +NOMIPS16 int test1 () { return long_call_func (); } +NOMIPS16 int test2 () { return far_func (); } +NOMIPS16 int test3 () { return near_func (); } +NOMIPS16 int test4 () { return normal_func (); } + +/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\tj(|al)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\tj(|al)\tnormal_func\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c new file mode 100644 index 000000000..fca525667 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c @@ -0,0 +1,13 @@ +/* Make sure that we use abs.fmt and neg.fmt when the signs of NaNs don't + matter. */ +/* { dg-do compile } */ +/* { dg-options "-mhard-float -ffinite-math-only" } */ +/* { dg-final { scan-assembler "\tneg.s\t" } } */ +/* { dg-final { scan-assembler "\tneg.d\t" } } */ +/* { dg-final { scan-assembler "\tabs.s\t" } } */ +/* { dg-final { scan-assembler "\tabs.d\t" } } */ + +NOMIPS16 float f1 (float f) { return -f; } +NOMIPS16 float f2 (float f) { return __builtin_fabsf (f); } +NOMIPS16 double d1 (double d) { return -d; } +NOMIPS16 double d2 (double d) { return __builtin_fabs (d); } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c new file mode 100644 index 000000000..435751e0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c @@ -0,0 +1,13 @@ +/* Make sure that we avoid abs.fmt and neg.fmt when the signs of NaNs + matter. */ +/* { dg-do compile } */ +/* { dg-options "-mhard-float -fno-finite-math-only" } */ +/* { dg-final { scan-assembler-not "\tneg.s\t" } } */ +/* { dg-final { scan-assembler-not "\tneg.d\t" } } */ +/* { dg-final { scan-assembler-not "\tabs.s\t" } } */ +/* { dg-final { scan-assembler-not "\tabs.d\t" } } */ + +float f1 (float f) { return -f; } +float f2 (float f) { return __builtin_fabsf (f); } +double d1 (double d) { return -d; } +double d2 (double d) { return __builtin_fabs (d); } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c new file mode 100644 index 000000000..00be144d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-ffast-math isa=4 -mhard-float" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tnmadd.s\t" } } */ +/* { dg-final { scan-assembler "\tnmadd.d\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.s\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.d\t" } } */ + +NOMIPS16 float +sub1 (float f, float g, float h) +{ + return -((f * g) + h); +} + +NOMIPS16 double +sub2 (double f, double g, double h) +{ + return -((f * g) + h); +} + +NOMIPS16 float +sub3 (float f, float g, float h) +{ + return -((f * g) - h); +} + +NOMIPS16 double +sub4 (double f, double g, double h) +{ + return -((f * g) - h); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c new file mode 100644 index 000000000..a271f33b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-fno-fast-math -ffinite-math-only isa=4 -mhard-float" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tnmadd.s\t" } } */ +/* { dg-final { scan-assembler "\tnmadd.d\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.s\t" } } */ +/* { dg-final { scan-assembler "\tnmsub.d\t" } } */ + +NOMIPS16 float +sub1 (float f, float g, float h) +{ + return -((f * g) + h); +} + +NOMIPS16 double +sub2 (double f, double g, double h) +{ + return -((f * g) + h); +} + +NOMIPS16 float +sub3 (float f, float g, float h) +{ + return -((f * g) - h); +} + +NOMIPS16 double +sub4 (double f, double g, double h) +{ + return -((f * g) - h); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c new file mode 100644 index 000000000..85de518a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c @@ -0,0 +1,30 @@ +/* The same code as nmadd-2.c, but compiled with -fno-finite-math-only. + We can't use nmadd and nmsub in that case. */ +/* { dg-do compile } */ +/* { dg-options "-fno-fast-math -fno-finite-math-only isa=4 -mhard-float" } */ +/* { dg-final { scan-assembler-not "\tnmadd" } } */ +/* { dg-final { scan-assembler-not "\tnmsub" } } */ + +float +sub1 (float f, float g, float h) +{ + return -((f * g) + h); +} + +double +sub2 (double f, double g, double h) +{ + return -((f * g) + h); +} + +float +sub3 (float f, float g, float h) +{ + return -((f * g) - h); +} + +double +sub4 (double f, double g, double h) +{ + return -((f * g) - h); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c new file mode 100644 index 000000000..c4a7b0aed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c @@ -0,0 +1,8 @@ +/* { dg-options "-mno-dsp -ffat-lto-objects" } */ + +void +foo (void) +{ + register int x asm ("$ac1hi"); /* { dg-error "cannot be accessed" } */ + asm volatile ("" : "=r" (x)); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c new file mode 100644 index 000000000..ecf856ea7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-smartmips" } */ + +NOMIPS16 int scaled_indexed_word_load (int a[], int b) +{ + return a[b]; +} +/* { dg-final { scan-assembler-not "\tlwxs\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c new file mode 100644 index 000000000..419d086b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-smartmips -march=mips32" } */ + +NOMIPS16 int rotate_left (unsigned a, unsigned s) +{ + return (a << s) | (a >> (32 - s)); +} +/* { dg-final { scan-assembler-not "\tror\t" } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c new file mode 100644 index 000000000..e71791ba3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tnor\t" 1 } } */ +/* { dg-final { scan-assembler-not "\tor" } } */ + +/* Test that we generate a 'nor' instruction and no 'or' instructions. */ + +NOMIPS16 int f (int a, int b) +{ + return ~(a|b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c new file mode 100644 index 000000000..e7150d297 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tbaddu\t" 4 } } */ +/* { dg-final { scan-assembler-not "\tandi\t" } } */ + +NOMIPS16 unsigned char +g (long long a, long long b) +{ + return a + b; +} + +NOMIPS16 unsigned long long +h (unsigned long long a, unsigned long long b) +{ + unsigned char c = a + b; + return c; +} + +NOMIPS16 long long +ff (long long a, long long b) +{ + unsigned char c = a + b; + return c; +} + +NOMIPS16 int +gg (int a, int b) +{ + return (a + b) & 0xff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c new file mode 100644 index 000000000..f91c68bcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tbbit1\t" } } */ +/* { dg-final { scan-assembler "\tbbit0\t" } } */ +/* { dg-final { scan-assembler-times "\tbbit.\t" 6 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */ + +NOMIPS16 void foo (void); + +NOMIPS16 void +f1 (long long i) +{ + if (i & 0x80) + foo (); +} + +NOMIPS16 void +f2 (int i) +{ + if (!(i & 0x80)) + foo (); +} + +NOMIPS16 void +f3 (int i) +{ + if (i % 2) + foo (); +} + +NOMIPS16 void +f4 (int i) +{ + if (i & 1) + foo (); +} + +NOMIPS16 void +f5 (long long i) +{ + if ((i >> 3) & 1) + foo (); +} + +unsigned long long r; + +NOMIPS16 static inline __attribute__((always_inline)) int +test_bit(unsigned long long nr, const unsigned long long *addr) +{ + return 1UL & (addr[nr >> 6] >> (nr & 63ULL)); +} + +NOMIPS16 void +f6 () +{ + if (!test_bit(0, &r)) + foo (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c new file mode 100644 index 000000000..7e78d70e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mbranch-likely -fno-unroll-loops" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tbbit\[01\]\t" } } */ +/* { dg-final { scan-assembler-not "\tbbit\[01\]l\t" } } */ +/* { dg-final { scan-assembler "\tbnel\t" } } */ + +NOMIPS16 int +f (int *a, int *b) +{ + do + if (__builtin_expect (*a & 1, 1)) + *a = 0; + while (++a < b); +} + +NOMIPS16 int +g (int *a, int *b) +{ + do + if (__builtin_expect (*a == 3, 1)) + *a = 0; + while (++a < b); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c new file mode 100644 index 000000000..7b73f43a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ + +/* Force big-endian because for little-endian, combine generates this: + + (if_then_else (ne (zero_extract:DI (subreg:DI (truncate:SI (reg:DI 196)) 0) + (const_int 1) + (const_int 0)) + (const_int 0)) + (label_ref 20) + (pc))) + + which does not get recognized as a valid bbit pattern. The + middle-end should be able to simplify this further. */ +/* { dg-options "-march=octeon -meb" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler-times "\tbbit\[01\]\t|\tbgez\t|\tbltz\t" 2 } } */ +/* { dg-final { scan-assembler-not "ext\t" } } */ + +void abort (void); +void abort1 (void); +void exit (int); + +typedef unsigned long long ulong64; + +typedef struct bitfield_s { + ulong64 a:1; + ulong64 b:29; + ulong64 c:1; + ulong64 d:15; + ulong64 f:18; +} bitfield_t; + +bitfield_t bar; + +NOMIPS16 void +f () +{ + foo(&bar); + if (bar.a != 0x1) + abort (); + else if (!bar.c) + abort1 (); + else + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c new file mode 100644 index 000000000..dd0b753ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* The tests also work with -mgp32. For long long tests, only one of + the 32-bit parts is used. */ +/* { dg-options "-march=octeon" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tcins\t" 3 } } */ +/* { dg-final { scan-assembler-not "\tandi\t|sll\t" } } */ + +NOMIPS16 long long +f (long long i) +{ + return (i & 0xff) << 34; +} + +NOMIPS16 int +g (int i) +{ + return (i << 4) & 0xff0; +} + +NOMIPS16 long long +h (long long i) +{ + return (i << 4) & 0xfff; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c new file mode 100644 index 000000000..71611bc9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tcins\t" } } */ + +NOMIPS16 unsigned +f (unsigned i) +{ + return (i & 0xff) << 24; +} + +NOMIPS16 unsigned long long +g (unsigned long long i) +{ + return (i & 0x1ffffffffULL) << 4; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c new file mode 100644 index 000000000..b8b8c1bc3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-final { scan-assembler "\tdmul\t" } } */ +/* { dg-final { scan-assembler-not "\tdmult\t" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ + +NOMIPS16 long long +f (long long a, long long b) +{ + return a * b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c new file mode 100644 index 000000000..cf8da24ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "using DMUL is no worse size-wise, and can be better if the constant is used elsewhere" { *-*-* } { "-Os" } { "" } } */ +/* { dg-final { scan-assembler-not "\tdmul" } } */ + +NOMIPS16 long long +f (long long a) +{ + return a * 7; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c new file mode 100644 index 000000000..38150a87e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c @@ -0,0 +1,20 @@ +/* Use DMUL for widening multiplication too. */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tdmul\t" 2 } } */ +/* { dg-final { scan-assembler-not "\td?mult\t" } } */ +/* { dg-final { scan-assembler-times "\tdext\t" 2 } } */ + +NOMIPS16 long long +f (int i, int j) +{ + i++; + return (long long) i * j; +} + +NOMIPS16 unsigned long long +g (unsigned int i, unsigned int j) +{ + i++; + return (unsigned long long) i * j; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c new file mode 100644 index 000000000..b0f4be143 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon" } */ +/* { dg-final { scan-assembler "\texts\t" } } */ + +struct foo +{ + long long a:3; + long long b:23; + long long c:38; +}; + +NOMIPS16 int +f (struct foo s) +{ + return s.b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c new file mode 100644 index 000000000..21353d906 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -meb" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 4 } } */ + +struct bar +{ + unsigned long long a:1; + long long b:14; + unsigned long long c:48; + long long d:1; +}; + +NOMIPS16 int +f1 (struct bar *s, int a) +{ + return (int) s->b + a; +} + +NOMIPS16 char +f2 (struct bar *s) +{ + return s->d + 1; +} + +NOMIPS16 int +f3 () +{ + struct bar s; + asm ("" : "=r"(s)); + return (int) s.b + 1; +} + +NOMIPS16 long long +f4 (struct bar *s) +{ + return s->d; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c new file mode 100644 index 000000000..be0419890 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 3 } } */ + +struct foo +{ + unsigned long long a:10; + unsigned long long b:32; + unsigned long long c:22; +}; + +NOMIPS16 unsigned +f (struct foo s) +{ + return s.b; +} + +struct bar +{ + unsigned long long a:15; + unsigned long long b:48; + unsigned long long c:1; +}; + +NOMIPS16 int +g (struct bar s) +{ + return (int) s.b; +} + +NOMIPS16 int +h (int i) +{ + return (i << 4) >> 24; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c new file mode 100644 index 000000000..0071ae173 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 6 } } */ + +#define TEST(ID, TYPE, SHIFT) \ + int NOMIPS16 \ + f##ID (long long y) \ + { \ + return (TYPE) ((TYPE) (y >> SHIFT) + 1); \ + } \ + int NOMIPS16 \ + g##ID (unsigned long long y) \ + { \ + return (TYPE) ((TYPE) (y >> SHIFT) + 1); \ + } + +TEST (1, int, 10) +TEST (2, short, 5) +TEST (3, char, 31) diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c new file mode 100644 index 000000000..0e587d7eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c @@ -0,0 +1,39 @@ +/* -mel version of octeon-exts-2.c. */ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mel" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 4 } } */ + +struct bar +{ + long long d:1; + unsigned long long c:48; + long long b:14; + unsigned long long a:1; +}; + +NOMIPS16 int +f1 (struct bar *s, int a) +{ + return (int) s->b + a; +} + +NOMIPS16 char +f2 (struct bar *s) +{ + return s->d + 1; +} + +NOMIPS16 int +f3 () +{ + struct bar s; + asm ("" : "=r"(s)); + return (int) s.b + 1; +} + +NOMIPS16 long long +f4 (struct bar *s) +{ + return s->d; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c new file mode 100644 index 000000000..b8da271ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c @@ -0,0 +1,23 @@ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 5 } } */ +/* { dg-final { scan-assembler-not "\t(dsll|dsra)\t" } } */ +/* { dg-final { scan-assembler-not "\tsll\t" } } */ + +#define TEST_CHAR(T, N) \ + NOMIPS16 T \ + f##N (long long d, T *a, T *r) \ + { \ + T b = (signed char) d; *r = b + *a; \ + } +#define TEST_SHORT(T, N) \ + NOMIPS16 T \ + g##N (long long d, T *a, T *r) \ + { \ + T b = (short) d; *r = b + *a; \ + } +#define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N) + +TEST (int, 1); +TEST (long long, 2); +TEST_CHAR (short, 3); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c new file mode 100644 index 000000000..fcae01261 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c @@ -0,0 +1,19 @@ +/* Remove the redundant sign-extension after the sign-extraction. */ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\texts\t" 1 } } */ +/* { dg-final { scan-assembler-not "\td?(sll|sra)" } } */ + +struct bar +{ + long long a:18; + long long b:24; + long long c:22; +}; + +NOMIPS16 int +f1 (struct bar *s) +{ + return s->b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c new file mode 100644 index 000000000..4488e3d51 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c @@ -0,0 +1,12 @@ +/* Check that we use the octeon pipeline description. */ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -fschedule-insns2 -fdump-rtl-sched2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 int f (int a, int b) +{ + return a / b; +} + +/* { dg-final { scan-rtl-dump "octeon_mult\\*71" "sched2" } } */ +/* { dg-final { cleanup-rtl-dump "sched2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c new file mode 100644 index 000000000..6a6791ce6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-final { scan-assembler "\tpop\t" } } */ +/* { dg-final { scan-assembler "\tdpop\t" } } */ + +NOMIPS16 int +f (long long a) +{ + return __builtin_popcountll (a); +} + +NOMIPS16 int +g (int a) +{ + return __builtin_popcount (a); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c new file mode 100644 index 000000000..d6d2a7afb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* The pop instruction does not depend on the word value to be sign extended. */ +/* { dg-final { scan-assembler-not "sll\t" } } */ + +NOMIPS16 long long f(long long i) +{ + return __builtin_popcount (i); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c new file mode 100644 index 000000000..c07660a2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c @@ -0,0 +1,19 @@ +/* Check if we expand seq and sne. */ + +/* { dg-do compile } */ +/* { dg-options "-march=octeon" } */ +/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 4 } } */ +/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 4 } } */ + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; } + +TEST (0, a, ==, b); +TEST (1, a, ==, 23); +TEST (2, a, ==, 511); +TEST (3, a, ==, -200); + +TEST (10, a, !=, b); +TEST (11, a, !=, 1); +TEST (12, a, !=, 350); +TEST (13, a, !=, -512); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c new file mode 100644 index 000000000..83e068c54 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 3 } } */ +/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 3 } } */ + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 long long f##N (long long a, long long b) { return LHS REL RHS; } + +TEST (0, a, ==, b); +TEST (1, a, ==, 23); +TEST (2, a, ==, 511); + +TEST (3, a, !=, b); +TEST (4, a, !=, 1); +TEST (5, a, !=, 350); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c new file mode 100644 index 000000000..71e09dc6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */ +/* { dg-final { scan-assembler-times "\tseqi\t\|\tsnei\t" 4 } } */ + + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \ + NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \ + +TEST (eq, a, ==, 10); +TEST (ne, a, !=, 32); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c new file mode 100644 index 000000000..0fd83f0b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\txor" } } */ + +unsigned +m (unsigned e); + +NOMIPS16 void +f (unsigned i) +{ + unsigned j = m (i); + h (j, i != j); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c new file mode 100644 index 000000000..445e3fc2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(N, R, T) \ + T fll##N (T j, signed R *b, long long i) { return j + b[i]; } \ + T gll##N (T j, unsigned R *b, long long i) { return j + b[i]; } \ + T fi##N (T j, signed R *b, int i) { return j + b[i]; } \ + T gi##N (T j, unsigned R *b, int i) { return j + b[i]; } \ + +TEST (1, char, int) +TEST (2, char, long long) +/* { dg-final { scan-assembler-times "\tlbx\t" 4 } } */ +/* { dg-final { scan-assembler-times "\tlbux\t" 4 } } */ +TEST (3, short, int) +TEST (4, short, long long) +/* { dg-final { scan-assembler-times "\tlhx\t" 4 } } */ +/* { dg-final { scan-assembler-times "\tlhux\t" 4 } } */ +TEST (5, int, long long) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tlwux\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c new file mode 100644 index 000000000..b487637be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(N, T) \ + T f##N (T *p, int i) { return p[i]; } \ + unsigned T g##N (unsigned T *p, int i) { return p[i]; } + +TEST (1, char) +/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */ +TEST (2, short) +/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */ +TEST (3, int) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ +TEST (4, long long) +/* { dg-final { scan-assembler-times "\tldx\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c new file mode 100644 index 000000000..110cf8bd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=octeon2 -mgp32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(N, T) \ + T f##N (T *p, int i) { return p[i]; } \ + unsigned T g##N (unsigned T *p, int i) { return p[i]; } + +TEST (1, char) +/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */ +TEST (2, short) +/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */ +TEST (3, int) +/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c new file mode 100644 index 000000000..18fd96671 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c @@ -0,0 +1,12 @@ +/* Check that we use the octeon2 pipeline description. */ +/* { dg-do compile } */ +/* { dg-options "-fschedule-insns2 -fdump-rtl-sched2 -march=octeon2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 int f (int a, int b) +{ + return a / b; +} + +/* { dg-final { scan-rtl-dump "octeon_mult\\*17" "sched2" } } */ +/* { dg-final { cleanup-rtl-dump "sched2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c new file mode 100644 index 000000000..c4716cff5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c @@ -0,0 +1,13 @@ +/* PR target/pr26765 + This testcase used to trigger an unrecognizable insn. */ + +/* { dg-do compile } */ +/* { dg-options "-w" } */ + +__thread int *a = 0; + +NOMIPS16 void foo (void) +{ + extern int *b; + b = (int *) ((*a)); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c new file mode 100644 index 000000000..109da4899 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c @@ -0,0 +1,11 @@ +/* GCC used to report an ICE for this test because we generated a LO_SUM + for an illegitimate constant. */ +/* { dg-options "-mabi=64 -msym32 -EB -mno-abicalls" } */ +extern unsigned long a[]; +int b (int); + +int +c (void) +{ + return b (a[0]); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c new file mode 100644 index 000000000..f849b396e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-mabi=64" } */ + +NOMIPS16 long double __powitf2 (long double x, int m) +{ + long double y = x; + while (m >>= 1) + { + x = x * x; + if (m % 2) + y = y * x; + } + return y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c new file mode 100644 index 000000000..c3e2cbfd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c @@ -0,0 +1,29 @@ +/* { dg-do link } */ + +volatile int gv; +const char *ptrs[2]; + +void +foo (volatile int *v, const char **ptrs) +{ + switch (*v & 1) + { + case 0: + ptrs[0] = 0; + break; + case 1: + break; + default: + ptrs[1] = "Some text"; + break; + } + while (*v > 0) + *v -= 1; +} + +int +main (void) +{ + foo (&gv, ptrs); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c new file mode 100644 index 000000000..2da436f71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c @@ -0,0 +1,7 @@ +/* { dg-options "-ffast-math -mips64 -mgp32" } */ + +double +foo (void) +{ + return __builtin_pow (0.0, -1.5); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c new file mode 100644 index 000000000..acdfaebe3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c @@ -0,0 +1,17 @@ +/* { dg-options "-march=74kc -mgp32" } */ +__thread int x __attribute__((tls_model("initial-exec"))); +__thread int y __attribute__((tls_model("initial-exec"))); + +int bar (void); + +NOMIPS16 void +foo (int n) +{ + if (n > 5) + { + y = 0; + do + x += bar (); + while (n--); + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c new file mode 100644 index 000000000..848d879d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c @@ -0,0 +1,20 @@ +/* mips*-sde-elf doesn't have 128-bit long doubles. */ +/* { dg-do compile { target { ! { mips*-sde-elf mips*-mti-elf } } } } */ +/* { dg-options "-march=mips64r2 -mabi=n32" } */ + +typedef float TFtype __attribute__((mode(TF))); + +TFtype +__powitf (TFtype x, int m) +{ + unsigned int n = m < 0 ? -m : m; + TFtype y = n % 2 ? x : 1; + while (n >>= 1) + { + x = x * x; + if (n % 2) + y = y * x; + } + return m < 0 ? 1/y : y; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c new file mode 100644 index 000000000..129467fb0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c @@ -0,0 +1,8 @@ +/* { dg-options "-mhard-float -mgp32" } */ +register double g __asm__("$f20"); + +NOMIPS16 void +test (double a) +{ + g = -a; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c new file mode 100644 index 000000000..2ac806720 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c @@ -0,0 +1,20 @@ +/* { dg-options "-mno-gpopt addressing=absolute" } */ + +int a, b, c, d; + +NOMIPS16 void +foo (void) +{ + asm ("%1 %z3" + : "=m" (a), "=m" (b) + : "m" (c), "m" (d)); +} + +/* { dg-final { scan-assembler-not "%hi\\(a\\)" } } */ +/* { dg-final { scan-assembler-not "%lo\\(a\\)" } } */ +/* { dg-final { scan-assembler "%hi\\(b\\)" } } */ +/* { dg-final { scan-assembler "%lo\\(b\\)" } } */ +/* { dg-final { scan-assembler-not "%hi\\(c\\)" } } */ +/* { dg-final { scan-assembler-not "%lo\\(c\\)" } } */ +/* { dg-final { scan-assembler "%hi\\(d\\)" } } */ +/* { dg-final { scan-assembler "%lo\\(d\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c new file mode 100644 index 000000000..cedb97a6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-fdump-tree-phiopt-details -ffat-lto-objects isa>=4" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-O1" } { "" } } */ + +typedef struct s { + int v; + int b; + struct s *l; + struct s *r; +} S; + +/* Test requires conditional moves. */ +NOMIPS16 int foo(S *s) +{ + S *this; + S *next; + + this = s; + if (this->b) + next = this->l; + else + next = this->r; + + return next->v; +} + +/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt1" } } */ +/* { dg-final { cleanup-tree-dump "phiopt1" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c new file mode 100644 index 000000000..9dcf2893a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ + +int data[4096]; + +int +f (void) +{ + return (((unsigned long) &data[0]) == 0xdeadbea0U); +} + +/* { dg-final { scan-assembler-not "\tmove\t\\\$2,\\\$0" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c new file mode 100644 index 000000000..7df021b69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c @@ -0,0 +1,8 @@ +/* { dg-options "-mips16" } */ + +void bar (void) {} + +void __attribute__((optimize("schedule-insns"))) +foo (void) +{ +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c new file mode 100644 index 000000000..898650656 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mno-plt" } */ + +extern void abort (void); + +struct lispstruct +{ + int e; + int t; +}; + +struct lispstruct Cnil_body; +struct lispstruct Ct_body; +int nvalues; + +struct lispstruct * __attribute__ ((noinline)) +fLlistp (struct lispstruct *x0) +{ + if (x0 == &Cnil_body + || (((unsigned long) x0 >= 0x80000000) ? 0 + : (!x0->e ? (x0 != &Cnil_body) : x0->t))) + x0 = &Ct_body; + else + x0 = &Cnil_body; + nvalues = 1; + return x0; +} + +int main () +{ + if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c new file mode 100644 index 000000000..dd23f7c86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-mips16" } */ +extern void abort(); + +int i_0, i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9; +int j_0, j_1, j_2, j_3, j_4, j_5, j_6, j_7, j_8, j_9; + +int main() +{ + register int *x1 = &i_1; + register int *x2 = &i_2; + register int *x3 = &i_3; + register int *x4 = &i_4; + register int *x5 = &i_5; + register int *x6 = &i_6; + register int *x7 = &i_7; + register int *x8 = &i_8; + register int *x9 = &i_9; + + register int *y0 = &j_0; + register int *y1 = &j_1; + register int *y2 = &i_2; + register int *y3 = &j_3; + register int *y4 = &j_4; + register int *y5 = &j_5; + register int *y6 = &j_6; + register int *y7 = &j_7; + register int *y8 = &j_8; + register int *y9 = &j_9; + + asm volatile ("" : "=r" (x2) : "0" (x2)); + asm volatile ("" : "=r" (x3) : "0" (x3)); + asm volatile ("" : "=r" (x4) : "0" (x4)); + asm volatile ("" : "=r" (x5) : "0" (x5)); + asm volatile ("" : "=r" (x6) : "0" (x6)); + asm volatile ("" : "=r" (x7) : "0" (x7)); + asm volatile ("" : "=r" (x8) : "0" (x8)); + asm volatile ("" : "=r" (x9) : "0" (x9)); + + asm volatile ("" : "=r" (y0) : "0" (y0)); + asm volatile ("" : "=r" (y1) : "0" (y1)); + asm volatile ("" : "=r" (y2) : "0" (y2)); + asm volatile ("" : "=r" (y3) : "0" (y3)); + asm volatile ("" : "=r" (y4) : "0" (y4)); + asm volatile ("" : "=r" (y5) : "0" (y5)); + asm volatile ("" : "=r" (y6) : "0" (y6)); + asm volatile ("" : "=r" (y7) : "0" (y7)); + asm volatile ("" : "=r" (y8) : "0" (y8)); + asm volatile ("" : "=r" (y9) : "0" (y9)); + + asm volatile ("" : "=r" (x1) : "0" (x1)); + asm volatile ("" : "=r" (x2) : "0" (x2)); + asm volatile ("" : "=r" (x3) : "0" (x3)); + asm volatile ("" : "=r" (x4) : "0" (x4)); + asm volatile ("" : "=r" (x5) : "0" (x5)); + asm volatile ("" : "=r" (x6) : "0" (x6)); + asm volatile ("" : "=r" (x7) : "0" (x7)); + asm volatile ("" : "=r" (x8) : "0" (x8)); + asm volatile ("" : "=r" (x9) : "0" (x9)); + + asm volatile ("" : "=r" (y0) : "0" (y0)); + asm volatile ("" : "=r" (y1) : "0" (y1)); + asm volatile ("" : "=r" (y2) : "0" (y2)); + asm volatile ("" : "=r" (y3) : "0" (y3)); + asm volatile ("" : "=r" (y4) : "0" (y4)); + asm volatile ("" : "=r" (y5) : "0" (y5)); + asm volatile ("" : "=r" (y6) : "0" (y6)); + asm volatile ("" : "=r" (y7) : "0" (y7)); + asm volatile ("" : "=r" (y8) : "0" (y8)); + asm volatile ("" : "=r" (y9) : "0" (y9)); + + if (y0 != &j_0) abort (); + if (y1 != &j_1) abort (); + if (y2 != &j_2) abort (); + if (y3 != &j_3) abort (); + if (y4 != &j_4) abort (); + if (y5 != &j_5) abort (); + if (y6 != &j_6) abort (); + if (y7 != &j_7) abort (); + if (y8 != &j_8) abort (); + if (y9 != &j_9) abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c new file mode 100644 index 000000000..b5ffd0aeb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c @@ -0,0 +1,45 @@ +/* { dg-options "-mabi=64 -mr10k-cache-barrier=store" } */ + +/* Test that stores to uncached addresses do not get unnecessary + cache barriers. */ + +#define TEST(ADDR) \ + NOMIPS16 void \ + test_##ADDR (int n) \ + { \ + while (n--) \ + { \ + *(volatile char *) (0x##ADDR##UL) = 1; \ + *(volatile short *) (0x##ADDR##UL + 2) = 2; \ + *(volatile int *) (0x##ADDR##UL + 4) = 0; \ + } \ + } + +TEST (9000000000000000) +TEST (900000fffffffff8) + +TEST (9200000000000000) +TEST (920000fffffffff8) + +TEST (9400000000000000) +TEST (940000fffffffff8) + +TEST (9600000000000000) +TEST (960000fffffffff8) + +TEST (b800000000000000) +TEST (b80000fffffffff8) + +TEST (ba00000000000000) +TEST (ba0000fffffffff8) + +TEST (bc00000000000000) +TEST (bc0000fffffffff8) + +TEST (be00000000000000) +TEST (be0000fffffffff8) + +TEST (ffffffffa0000000) +TEST (ffffffffbffffff8) + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c new file mode 100644 index 000000000..ad0d2b049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c @@ -0,0 +1,26 @@ +/* { dg-options "-mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +unsigned char *bar (int); + +/* Test that code after a branch-likely does not get an unnecessary + cache barrier. */ + +NOMIPS16 void +foo (unsigned char *n) +{ + /* n starts in $4, but will be in $2 after the call to bar. + Encourage it to be in $2 on entry to the loop as well, + by doing some computation on it beforehand (D?ADDIU $2,$4,4). + dbr_schedule should then pull the *n load (L[WD] ...,0($2)) + into the delay slot. */ + n += 4; + do + n = bar (*n + 1); + while (n); + /* The preceding branch should be a branch likely, with the shift as + its delay slot. We therefore don't need a cache barrier here. */ + n[0] = 0; +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c new file mode 100644 index 000000000..936c2589d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c @@ -0,0 +1,13 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */ + +/* Test that loads are not unnecessarily protected. */ + +int bar (int); + +NOMIPS16 void +foo (int *ptr) +{ + *ptr = bar (*ptr); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c new file mode 100644 index 000000000..34a12489c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c @@ -0,0 +1,13 @@ +/* { dg-options "-mr10k-cache-barrier=load-store -mno-abicalls" } */ + +/* Test that loads are correctly protected. */ + +int bar (int); + +NOMIPS16 void +foo (int *ptr) +{ + *ptr = bar (*ptr); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c new file mode 100644 index 000000000..ee9c84b59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c @@ -0,0 +1,14 @@ +/* { dg-options "-mr10k-cache-barrier=store" } */ + +/* Test that indirect calls are protected. */ + +int bar (int); + +NOMIPS16 void +foo (void (*fn) (void), int x) +{ + if (x) + (*fn) (); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c new file mode 100644 index 000000000..92c37f497 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c @@ -0,0 +1,5 @@ +/* { dg-options "(-mips16) -mr10k-cache-barrier=store -ffat-lto-objects" } */ + +/* Test that indirect calls are protected. */ + +MIPS16 void foo (void) { } /* { dg-message "sorry, unimplemented" } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c new file mode 100644 index 000000000..da655cda1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c @@ -0,0 +1,2 @@ +/* { dg-options "-mr10k-cache-barrier=store -mips2" } */ +/* { dg-error "requires.*cache.*instruction" "" { target *-*-* } 0 } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c new file mode 100644 index 000000000..ebf45f94f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c @@ -0,0 +1,40 @@ +/* { dg-options "-mabi=64 -mr10k-cache-barrier=store" } */ + +/* Test that stores to constant cached addresses are protected + by cache barriers. */ + +#define TEST(ADDR) \ + NOMIPS16 void \ + test_##ADDR (int n) \ + { \ + *(volatile int *) (0x##ADDR##UL) = 1; \ + } + +TEST (8ffffffffffffffc) +TEST (9000010000000000) + +TEST (91fffffffffffffc) +TEST (9200010000000000) + +TEST (93fffffffffffffc) +TEST (9500010000000000) + +TEST (95fffffffffffffc) +TEST (9600010000000000) + +TEST (b7fffffffffffffc) +TEST (b800010000000000) + +TEST (b9fffffffffffffc) +TEST (ba00010000000000) + +TEST (bbfffffffffffffc) +TEST (bc00010000000000) + +TEST (bdfffffffffffffc) +TEST (be00010000000000) + +TEST (ffffffff9ffffffc) +TEST (ffffffffc0000000) + +/* { dg-final { scan-assembler-times "\tcache\t" 18 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c new file mode 100644 index 000000000..9e5678981 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */ + +/* Test that in-range stores to the frame are not protected by + cache barriers. */ + +void bar (int *x); + +NOMIPS16 void +foo (int v) +{ + int x[0x100000]; + bar (x); + x[0x20] = v; + bar (x); +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c new file mode 100644 index 000000000..7780460b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c @@ -0,0 +1,20 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */ + +void bar (int *x); + +/* Test that out-of-range stores to the frame are protected by cache + barriers. */ + +NOMIPS16 void +foo (int v) +{ + int x[8]; + bar (x); + if (v & 1) + x[0x100] = 0; + if (v & 2) + x[-0x100] = 0; + bar (x); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c new file mode 100644 index 000000000..757beefc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c @@ -0,0 +1,19 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls -mabi=64" } */ + +/* Test that in-range stores to static objects do not get an unnecessary + cache barrier. */ + +int x[4]; +void bar (void); + +NOMIPS16 void +foo (int n) +{ + while (n--) + { + x[3] = 1; + bar (); + } +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c new file mode 100644 index 000000000..32dd78cb5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c @@ -0,0 +1,19 @@ +/* { dg-options "-mr10k-cache-barrier=store -mabi=64" } */ + +int x[4]; +void bar (void); + +/* Test that out-of-range stores to static objects are protected by a + cache barrier. */ + +NOMIPS16 void +foo (int n) +{ + while (n--) + { + x[4] = 1; + bar (); + } +} + +/* { dg-final { scan-assembler "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c new file mode 100644 index 000000000..3a7a2538e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c @@ -0,0 +1,27 @@ +/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */ + +void bar1 (void); +void bar2 (void); +void bar3 (void); + +NOMIPS16 void +foo (int *x, int sel, int n) +{ + if (sel) + { + bar1 (); + x[0] = 1; + } + else + { + bar2 (); + x[1] = 0; + } + /* If there is one copy of this code, reached by two unconditional edges, + then it shouldn't need a third cache barrier. */ + x[2] = 2; + while (n--) + bar3 (); +} + +/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c new file mode 100644 index 000000000..121b90723 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c @@ -0,0 +1,15 @@ +/* { dg-options "-mr10k-cache-barrier=store -G8" } */ + +/* Test that in-range stores to components of static objects + do not get an unnecessary cache barrier. */ + +struct { struct { char i[4]; } a; struct { char j[4]; } b; } s; + +NOMIPS16 void +foo (int sel) +{ + s.a.i[0] = 1; + s.b.j[3] = 100; +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c new file mode 100644 index 000000000..2f83968aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c @@ -0,0 +1,19 @@ +/* { dg-options "-mr10k-cache-barrier=store -G8" } */ + +/* Test that out-of-range stores to components of static objects + are protected by a cache barrier. */ + +struct { struct { char i[4]; } a; struct { char j[4]; } b; } s; + +NOMIPS16 void +foo (int sel1, int sel2, int sel3) +{ + if (sel1) + s.a.i[8] = 1; + if (sel2) + s.b.j[4] = 100; + if (sel3) + s.a.i[-1] = 0; +} + +/* { dg-final { scan-assembler-times "\tcache\t" 3 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c new file mode 100644 index 000000000..4dc2b003f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=r3900" } */ +/* { dg-final { scan-assembler "\tmult\t\[^\n\]*,\[^\n\]*," } } */ + +NOMIPS16 int +f (int a, int b) +{ + return a * b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c new file mode 100644 index 000000000..d8b811810 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +register int g asm ("$18"); + +void __attribute__((noinline)) +test (void) +{ + g = g + 1; +} + +int +main (void) +{ + g = 2; + test (); + return g != 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c new file mode 100644 index 000000000..93fca39d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-ffast-math isa=4 -mhard-float -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\trsqrt.d\t" } } */ +/* { dg-final { scan-assembler "\trsqrt.s\t" } } */ + +extern double sqrt(double); +extern float sqrtf(float); + +NOMIPS16 double foo(double x) +{ + return 1.0/sqrt(x); +} + +NOMIPS16 float bar(float x) +{ + return 1.0f/sqrtf(x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c new file mode 100644 index 000000000..c35ca0c6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-ffast-math isa=4 -mhard-float -mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\trsqrt.d\t" } } */ +/* { dg-final { scan-assembler "\trsqrt.s\t" } } */ + +extern double sqrt(double); +extern float sqrtf(float); + +NOMIPS16 double foo(double x) +{ + return sqrt(1.0/x); +} + +NOMIPS16 float bar(float x) +{ + return sqrtf(1.0f/x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c new file mode 100644 index 000000000..25178f2c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "isa=4 -mhard-float" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\trsqrt.d\t" } } */ +/* { dg-final { scan-assembler-not "\trsqrt.s\t" } } */ + +extern double sqrt(double); +extern float sqrtf(float); + +double foo(double x) +{ + return 1.0/sqrt(x); +} + +double bar(double x) +{ + return sqrt(1.0/x); +} + +float foof(float x) +{ + return 1.0f/sqrtf(x); +} + +float barf(float x) +{ + return sqrtf(1.0f/x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c new file mode 100644 index 000000000..6b6577e2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-ffast-math -mips64 -mhard-float -mgp32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\trsqrt.d\t" } } */ +/* { dg-final { scan-assembler-times "\trsqrt.s\t" 2 } } */ + +extern double sqrt(double); +extern float sqrtf(float); + +NOMIPS16 double f1 (double x) +{ + return 1.0 / sqrt (x); +} + +NOMIPS16 double f2 (double x) +{ + return sqrt (1.0 / x); +} + +NOMIPS16 float f3 (float x) +{ + return 1.0f / sqrtf (x); +} + +NOMIPS16 float f4 (float x) +{ + return sqrtf (1.0f / x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c new file mode 100644 index 000000000..b3ce1b18d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c @@ -0,0 +1,20 @@ +/* Check that we can use the save instruction to save varargs. */ +/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */ + +#include <stdarg.h> + +int bar (int, va_list ap); + +MIPS16 int +foo (int n, ...) +{ + va_list ap; + int i; + + va_start (ap, n); + i = bar (n, ap); + va_end (ap); + return i + 1; +} +/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$7" } } */ +/* { dg-final { scan-assembler "\trestore\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c new file mode 100644 index 000000000..899460fe7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c @@ -0,0 +1,16 @@ +/* Check that we can use the save instruction to save spilled arguments. */ +/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MIPS16 void +foo (int *a, int b, int c) +{ + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "memory"); + a[b] = 1; + a[c] = 1; +} +/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */ +/* { dg-final { scan-assembler "\trestore\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c new file mode 100644 index 000000000..5d7aeb0ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c @@ -0,0 +1,20 @@ +/* Check that we can use the save instruction to save spilled arguments + when the argument save area is out of range of a direct load or store. */ +/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */ + +void bar (int *); + +MIPS16 void +foo (int *a, int b, int c) +{ + int x[0x4000]; + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "memory"); + bar (x); + a[b] = 1; + a[c] = 1; +} +/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */ +/* { dg-final { scan-assembler "\trestore\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c new file mode 100644 index 000000000..25f3e6199 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c @@ -0,0 +1,14 @@ +/* Check that we can use the save instruction to save $16, $17 and $31. */ +/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void bar (void); + +MIPS16 void +foo (void) +{ + bar (); + asm volatile ("" ::: "$16", "$17"); +} +/* { dg-final { scan-assembler "\tsave\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */ +/* { dg-final { scan-assembler "\trestore\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c new file mode 100644 index 000000000..b0dc1f057 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c @@ -0,0 +1,15 @@ +/* Check that we don't try to save the same register twice. */ +/* { dg-options "(-mips16) isa_rev>=1 -mgp32" } */ + +int bar (int, int, int, int); +void frob (void); + +MIPS16 void +foo (int a1, int a2, int a3, int a4) +{ + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "$31", "memory"); + __builtin_eh_return (bar (a1, a2, a3, a4), frob); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c new file mode 100644 index 000000000..0c2ae066a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c @@ -0,0 +1,30 @@ +/* Test SB-1 v2sf extensions. */ +/* { dg-do compile } */ +/* { dg-options "-march=sb1 -mpaired-single -mgp64 -ffast-math" } */ +/* { dg-skip-if "rsqrt code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tdiv.ps\t" } } */ +/* { dg-final { scan-assembler "\trecip.ps\t" } } */ +/* { dg-final { scan-assembler "\tsqrt.ps\t" } } */ +/* { dg-final { scan-assembler "\trsqrt.ps\t" } } */ + +typedef float v2sf __attribute__ ((vector_size (8))); + +NOMIPS16 v2sf divide (v2sf a, v2sf b) +{ + return a / b; +} + +NOMIPS16 v2sf recip (v2sf a) +{ + return ((v2sf) {1.0, 1.0}) / a; +} + +NOMIPS16 v2sf squareroot (v2sf a) +{ + return __builtin_mips_sqrt_ps (a); +} + +NOMIPS16 v2sf rsqrt (v2sf a) +{ + return ((v2sf) {1.0, 1.0}) / __builtin_mips_sqrt_ps (a); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c new file mode 100644 index 000000000..17599a837 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c @@ -0,0 +1,35 @@ +/* { dg-options "(-mips16) isa_rev>=1" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$5,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$5,\$4} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$0,\$4} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$0,\$4} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$4,\$5} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$4,\$5} 1 } } */ + +/* { dg-final { scan-assembler-times {slt \$2,\$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$2,\$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {slt \$4,23} 1 } } */ +/* { dg-final { scan-assembler-times {sltu \$4,23} 1 } } */ + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \ + NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } \ + MIPS16 int s##N##_16 (int a, int b) { return LHS REL RHS; } \ + MIPS16 int u##N##_16 (unsigned a, unsigned b) { return LHS REL RHS; } + +#define TEST_NO16(N, LHS, REL, RHS) \ + NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \ + NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } + +TEST (1, a, >, b); +TEST_NO16 (2, a, >=, 1); +TEST (3, a, <, b); +TEST (4, a, <=, 22); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c new file mode 100644 index 000000000..132da7bcf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */ +/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 12 } } */ + + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \ + NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \ + +TEST (eq, a, ==, 0); +TEST (ne, a, !=, 0); +TEST (gt, a, >, b); +TEST (ge, a, >=, 1); +TEST (lt, a, <, b); +TEST (le, a, <=, 11); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c new file mode 100644 index 000000000..a07a85ada --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c @@ -0,0 +1,17 @@ +/* { dg-options "(-mips16) -mabi=o64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */ +/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 8 } } */ + + +#define TEST(N, LHS, REL, RHS) \ + MIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \ + MIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \ + +TEST (eq, a, ==, 0); + +TEST (gt, a, >, b); + +TEST (lt, a, <, b); +TEST (le, a, <=, 11); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c new file mode 100644 index 000000000..b8e289982 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=o64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* { dg-final { scan-assembler "\tslt\t" } } */ +/* { dg-final { scan-assembler "\tsltu\t\|\txor\t\|\txori\t" } } */ + +/* This test should work both in mips16 and non-mips16 mode. */ + +int +f (long long a, long long b) +{ + return a > 5; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c new file mode 100644 index 000000000..646a44994 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c @@ -0,0 +1,61 @@ +/* { dg-options "-G4 -mexplicit-relocs" } */ + +/* { dg-final { scan-assembler "%gp_?rel\\(l4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l4c\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(c4\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4c\\)" } } */ + +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l8c\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e8b\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g8c\\)" } } */ + +static volatile int l4a; +static volatile int l4b = 1; +static volatile int __attribute__((section(".sdata"))) l4c; +extern int e4a; +extern int __attribute__((section(".sdata"))) e4b; +int __attribute__((common)) c4; +int __attribute__((nocommon)) g4a; +int g4b = 1; +int __attribute__((section(".sdata"))) g4c = 2; + +static volatile int l8a[2]; +static volatile int l8b[2] = { 1, 2 }; +static volatile int __attribute__((section(".sdata"))) l8c[2]; +extern int e8a[2]; +extern int __attribute__((section(".sdata"))) e8b[2]; +int __attribute__((common)) c8[2]; +int __attribute__((nocommon)) g8a[2]; +int g8b[2] = { 1, 2 }; +int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 }; + +int f32a (void) { return l4a; } +int f32b (void) { return l4b; } +int f32c (void) { return l4c; } +int f32d (void) { return e4a; } +int f32e (void) { return e4b; } +int f32f (void) { return c4; } +int f32g (void) { return g4a; } +int f32h (void) { return g4b; } +int f32i (void) { return g4c; } + +int f64a (void) { return l8a[0]; } +int f64b (void) { return l8b[0]; } +int f64c (void) { return l8c[0]; } +int f64d (void) { return e8a[0]; } +int f64e (void) { return e8b[0]; } +int f64f (void) { return c8[0]; } +int f64g (void) { return g8a[0]; } +int f64h (void) { return g8b[0]; } +int f64i (void) { return g8c[0]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c new file mode 100644 index 000000000..fe55120f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c @@ -0,0 +1,61 @@ +/* { dg-options "-G4 -mexplicit-relocs -mno-local-sdata" } */ + +/* { dg-final { scan-assembler-not "%gp_?rel\\(l4a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(l4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l4c\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(c4\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4c\\)" } } */ + +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l8c\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e8b\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g8c\\)" } } */ + +static volatile int l4a; +static volatile int l4b = 1; +static volatile int __attribute__((section(".sdata"))) l4c; +extern int e4a; +extern int __attribute__((section(".sdata"))) e4b; +int __attribute__((common)) c4; +int __attribute__((nocommon)) g4a; +int g4b = 1; +int __attribute__((section(".sdata"))) g4c = 2; + +static volatile int l8a[2]; +static volatile int l8b[2] = { 1, 2 }; +static volatile int __attribute__((section(".sdata"))) l8c[2]; +extern int e8a[2]; +extern int __attribute__((section(".sdata"))) e8b[2]; +int __attribute__((common)) c8[2]; +int __attribute__((nocommon)) g8a[2]; +int g8b[2] = { 1, 2 }; +int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 }; + +int f32a (void) { return l4a; } +int f32b (void) { return l4b; } +int f32c (void) { return l4c; } +int f32d (void) { return e4a; } +int f32e (void) { return e4b; } +int f32f (void) { return c4; } +int f32g (void) { return g4a; } +int f32h (void) { return g4b; } +int f32i (void) { return g4c; } + +int f64a (void) { return l8a[0]; } +int f64b (void) { return l8b[0]; } +int f64c (void) { return l8c[0]; } +int f64d (void) { return e8a[0]; } +int f64e (void) { return e8b[0]; } +int f64f (void) { return c8[0]; } +int f64g (void) { return g8a[0]; } +int f64h (void) { return g8b[0]; } +int f64i (void) { return g8c[0]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c new file mode 100644 index 000000000..6705ee35a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c @@ -0,0 +1,61 @@ +/* { dg-options "-G4 -mexplicit-relocs -mno-extern-sdata" } */ + +/* { dg-final { scan-assembler "%gp_?rel\\(l4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l4c\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(e4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e4b\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(c4\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g4c\\)" } } */ + +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(l8c\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(e8b\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */ +/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */ +/* { dg-final { scan-assembler "%gp_?rel\\(g8c\\)" } } */ + +static volatile int l4a; +static volatile int l4b = 1; +static volatile int __attribute__((section(".sdata"))) l4c; +extern int e4a; +extern int __attribute__((section(".sdata"))) e4b; +int __attribute__((common)) c4; +int __attribute__((nocommon)) g4a; +int g4b = 1; +int __attribute__((section(".sdata"))) g4c = 2; + +static volatile int l8a[2]; +static volatile int l8b[2] = { 1, 2 }; +static volatile int __attribute__((section(".sdata"))) l8c[2]; +extern int e8a[2]; +extern int __attribute__((section(".sdata"))) e8b[2]; +int __attribute__((common)) c8[2]; +int __attribute__((nocommon)) g8a[2]; +int g8b[2] = { 1, 2 }; +int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 }; + +int f32a (void) { return l4a; } +int f32b (void) { return l4b; } +int f32c (void) { return l4c; } +int f32d (void) { return e4a; } +int f32e (void) { return e4b; } +int f32f (void) { return c4; } +int f32g (void) { return g4a; } +int f32h (void) { return g4b; } +int f32i (void) { return g4c; } + +int f64a (void) { return l8a[0]; } +int f64b (void) { return l8b[0]; } +int f64c (void) { return l8c[0]; } +int f64d (void) { return e8a[0]; } +int f64e (void) { return e8b[0]; } +int f64f (void) { return c8[0]; } +int f64g (void) { return g8a[0]; } +int f64h (void) { return g8b[0]; } +int f64i (void) { return g8c[0]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c new file mode 100644 index 000000000..82cfa61f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c @@ -0,0 +1,44 @@ +/* { dg-options "-G4 -mexplicit-relocs -mno-gpopt" } */ + +/* { dg-final { scan-assembler-not "%gp_?rel" } } */ +/* { dg-final { scan-assembler-not "\\\$gp" } } */ + +static volatile int l4a; +static volatile int l4b = 1; +static volatile int __attribute__((section(".sdata"))) l4c; +extern int e4a; +extern int __attribute__((section(".sdata"))) e4b; +int __attribute__((common)) c4; +int __attribute__((nocommon)) g4a; +int g4b = 1; +int __attribute__((section(".sdata"))) g4c = 2; + +static volatile int l8a[2]; +static volatile int l8b[2] = { 1, 2 }; +static volatile int __attribute__((section(".sdata"))) l8c[2]; +extern int e8a[2]; +extern int __attribute__((section(".sdata"))) e8b[2]; +int __attribute__((common)) c8[2]; +int __attribute__((nocommon)) g8a[2]; +int g8b[2] = { 1, 2 }; +int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 }; + +int f32a (void) { return l4a; } +int f32b (void) { return l4b; } +int f32c (void) { return l4c; } +int f32d (void) { return e4a; } +int f32e (void) { return e4b; } +int f32f (void) { return c4; } +int f32g (void) { return g4a; } +int f32h (void) { return g4b; } +int f32i (void) { return g4c; } + +int f64a (void) { return l8a[0]; } +int f64b (void) { return l8b[0]; } +int f64c (void) { return l8c[0]; } +int f64d (void) { return e8a[0]; } +int f64e (void) { return e8b[0]; } +int f64f (void) { return c8[0]; } +int f64g (void) { return g8a[0]; } +int f64h (void) { return g8b[0]; } +int f64i (void) { return g8c[0]; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c new file mode 100644 index 000000000..ae23608ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-times "\tsltu\t|\tsltiu\t" 4 } } */ + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; } + +TEST (0, a, ==, 0); +TEST (1, a, ==, 600); +TEST (10, a, !=, 0); +TEST (11, a, !=, -800); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c new file mode 100644 index 000000000..0237272cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-mhard-float" } */ +/* { dg-skip-if "requiring \$4 is a code-quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 void +foo (unsigned int x) +{ + __builtin_mips_set_fcsr (x); +} + +/* { dg-final { scan-assembler "ctc1\t\\\$4,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c new file mode 100644 index 000000000..82696298f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-mhard-float (-mips16)" } */ + +MIPS16 void +foo (unsigned int x) +{ + __builtin_mips_set_fcsr (x); +} + +/* { dg-final { scan-assembler "__mips16_set_fcsr" } } */ +/* { dg-final { scan-assembler "ctc1\t\\\$4,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c new file mode 100644 index 000000000..ce64b13a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-msmartmips" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 int scaled_indexed_word_load (int a[], int b) +{ + return a[b]; +} +/* { dg-final { scan-assembler "\tlwxs\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c new file mode 100644 index 000000000..6300f8f03 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-msmartmips" } */ + +NOMIPS16 int rotate_left (unsigned a, unsigned s) +{ + return (a << s) | (a >> (32 - s)); +} +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c new file mode 100644 index 000000000..2d7c5dcd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-msmartmips" } */ + +NOMIPS16 int rotate_right (unsigned a, unsigned s) +{ + return (a >> s) | (a << (32 - s)); +} +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c new file mode 100644 index 000000000..5e51aa3f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-msmartmips" } */ + +#define S 13 + +NOMIPS16 int rotate_left_constant (unsigned a) +{ + return (a << S) | (a >> (32 - S)); +} +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c new file mode 100644 index 000000000..fc88a9a82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-msmartmips" } */ + +#define S 13 + +NOMIPS16 int rotate_right_constant (unsigned a) +{ + return (a >> S) | (a << (32 - S)); +} +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c new file mode 100644 index 000000000..855ff8ead --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c @@ -0,0 +1,8 @@ +/* { dg-options "-msoft-float -ffat-lto-objects" } */ + +void +foo (void) +{ + register float x asm ("$f0"); /* { dg-error "cannot be accessed" } */ + asm volatile ("" : "=r" (x)); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c new file mode 100644 index 000000000..a28e4bf20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c @@ -0,0 +1,11 @@ +/* { dg-final { scan-assembler "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\]" } } */ +/* { dg-final { scan-assembler "\tlw\t" } } */ +/* { dg-final { scan-assembler-not "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\].*\tlw\t" } } */ + +/* Avoid use of SAVE and RESTORE. */ +NOMIPS16 int foo (int y) +{ + volatile int a = y; + volatile int *volatile b = &a; + return *b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c new file mode 100644 index 000000000..606fee0cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c @@ -0,0 +1,106 @@ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "we deliberately use calls when optimizing for size" { *-*-* } { "-Os" } { "" } } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +test1 (void) +{ + result = a * b; + if (result != c) + return 1; + return 0; +} + +int +test2 (void) +{ + result = c + d; + if (result != e) + return 1; + return 0; +} + +int +test3 (void) +{ + result = e - d; + if (result != c) + return 1; + return 0; +} + +int +test4 (void) +{ + result = d & e; + if (result != f) + return 1; + return 0; +} + +int +test5 (void) +{ + result = d ^ e; + if (result != g) + return 1; + return 0; +} + +int +test6 (void) +{ + result = d | e; + if (result != h) + return 1; + return 0; +} + +int +test7 (void) +{ + result = g << amount; + if (result != i) + return 1; + return 0; +} + +int +test8 (void) +{ + result = g >> amount; + if (result != j) + return 1; + return 0; +} + +int +test9 (void) +{ + result = (int128_t) g >> amount; + if (result != k) + return 1; + return 0; +} + +/* { dg-final { scan-assembler-not "\tjal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c new file mode 100644 index 000000000..b6b8ea99b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c @@ -0,0 +1,118 @@ +/* { dg-do run } */ +/* { dg-options "-mgp64" } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +test1 (void) +{ + result = a * b; + if (result != c) + return 1; + return 0; +} + +int +test2 (void) +{ + result = c + d; + if (result != e) + return 1; + return 0; +} + +int +test3 (void) +{ + result = e - d; + if (result != c) + return 1; + return 0; +} + +int +test4 (void) +{ + result = d & e; + if (result != f) + return 1; + return 0; +} + +int +test5 (void) +{ + result = d ^ e; + if (result != g) + return 1; + return 0; +} + +int +test6 (void) +{ + result = d | e; + if (result != h) + return 1; + return 0; +} + +int +test7 (void) +{ + result = g << amount; + if (result != i) + return 1; + return 0; +} + +int +test8 (void) +{ + result = g >> amount; + if (result != j) + return 1; + return 0; +} + +int +test9 (void) +{ + result = (int128_t) g >> amount; + if (result != k) + return 1; + return 0; +} + +int +main (void) +{ + return (test1 () + | test2 () + | test3 () + | test4 () + | test5 () + | test6 () + | test7 () + | test8 () + | test9 ()); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c new file mode 100644 index 000000000..d12ebd311 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c @@ -0,0 +1,21 @@ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(ID, TYPE, SHIFT) \ + int __attribute__((nomips16)) \ + f##ID (unsigned long long y) \ + { \ + return (TYPE) ((TYPE) (y >> SHIFT) + 1); \ + } + +TEST (1, int, 32) +TEST (2, short, 32) +TEST (3, char, 32) +TEST (4, int, 33) +TEST (5, short, 33) +TEST (6, char, 33) +TEST (7, int, 61) +TEST (8, short, 61) +TEST (9, char, 61) + +/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c new file mode 100644 index 000000000..06ab58f5a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c @@ -0,0 +1,21 @@ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#define TEST(ID, TYPE, SHIFT) \ + int NOMIPS16 \ + f##ID (long long y) \ + { \ + return (TYPE) ((TYPE) (y >> SHIFT) + 1); \ + } + +TEST (1, int, 32) +TEST (2, short, 32) +TEST (3, char, 32) +TEST (4, int, 33) +TEST (5, short, 33) +TEST (6, char, 33) +TEST (7, int, 61) +TEST (8, short, 61) +TEST (9, char, 61) + +/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c new file mode 100644 index 000000000..fcb69e4b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c @@ -0,0 +1,12 @@ +/* Remove redundant operations in truncate's operand. */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tandi?\t" } } */ + +f (long long d) +{ + long long c = d & 0xffffffffff; + int i = (int) c; + g (i); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c new file mode 100644 index 000000000..cda90e00c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c @@ -0,0 +1,11 @@ +/* The and is performed in DI mode so there is no need for truncation. */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tsll\t" } } */ + +NOMIPS16 unsigned long long +f (unsigned long long s) +{ + unsigned u = s & 0xfff; + return u; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c new file mode 100644 index 000000000..f2a1875e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c @@ -0,0 +1,16 @@ +/* If we AND in DI mode (i.e. replace the order of TRUNCATE and AND) then we + can remove the TRUNCATE. */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */ + +struct s +{ + unsigned a:5; +}; + +NOMIPS16 void +f (struct s *s, unsigned long long a) +{ + s->a = a & 0x3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c new file mode 100644 index 000000000..178d4baa4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c @@ -0,0 +1,13 @@ +/* setup_incoming_promotions should detect x to be already sign-extended due + to PROMOTE_MODE. Thus the truncation should be removed by combine. Based + on gcc.c-torture/execute/pr34070-2.c. */ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */ + +NOMIPS16 int f(unsigned int x, int n, int *p) +{ + if (p) + *p = 1; + return ((int)x) / (1 << n); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c new file mode 100644 index 000000000..f172b2223 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c @@ -0,0 +1,18 @@ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler "\tlw\t" } } */ +/* { dg-final { scan-assembler-not "\tsll\t" } } */ +/* { dg-final { scan-assembler-not "\tld\t" } } */ + +struct s +{ + long long a; + int b; +}; + +int +foo (struct s *x) +{ + return x->a; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c new file mode 100644 index 000000000..441abcaf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c @@ -0,0 +1,10 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int MICROMIPS +foo (void) +{ + return 0; +} + +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tmove\t\\\$2,\\\$0" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c new file mode 100644 index 000000000..156476311 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c @@ -0,0 +1,10 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int MICROMIPS +foo (int *x) +{ + return x[5000]; +} + +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tlw\t\\\$2,20000\\(\\\$4\\)" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c new file mode 100644 index 000000000..8717362e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c @@ -0,0 +1,10 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (void) +{ + return; +} + +/* { dg-final { scan-assembler "\tjrc\t\\\$31\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c new file mode 100644 index 000000000..0bd21f63b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c @@ -0,0 +1,12 @@ +/* { dg-options "(-mmicromips) addressing=absolute" } */ + +void foo (void); + +int MICROMIPS +a (void) +{ + foo (); + return 0; +} + +/* { dg-final { scan-assembler "\tjals\tfoo\n\tnop" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c new file mode 100644 index 000000000..ddec815b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%a0" :: "ZD" (&x[0])); + asm volatile ("insn2\t%a0" :: "ZD" (&x[511])); + asm volatile ("insn3\t%a0" :: "ZD" (&x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c new file mode 100644 index 000000000..0240d4670 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%0" :: "ZC" (x[0])); + asm volatile ("insn2\t%0" :: "ZC" (x[511])); + asm volatile ("insn3\t%0" :: "ZC" (x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c new file mode 100644 index 000000000..0cdb1b7f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c new file mode 100644 index 000000000..ea3f39607 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c new file mode 100644 index 000000000..2cb37510f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c new file mode 100644 index 000000000..b8a86b4ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c new file mode 100644 index 000000000..2315f21e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c new file mode 100644 index 000000000..9534974de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c new file mode 100644 index 000000000..87ff6dc11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c @@ -0,0 +1,41 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int *r4, int dummy, int *other) +{ + int r5 = r4[1]; + int newr4 = r4[0]; + other[0] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f2 (int *r4, int dummy, int *other) +{ + int newr4 = r4[0]; + int r5 = *(int *)(newr4 + 4); + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f3 (int dummy, int *r5, int *other) +{ + int newr5 = r5[1]; + int r4 = *(int *)newr5; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c new file mode 100644 index 000000000..43b98423d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int dummy, int *r5, int *other) +{ + int r4 = r5[0]; + int newr5 = r5[1]; + other[0] = r4 * r4; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$4,0\\(\\\$5\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c new file mode 100644 index 000000000..da2cbaff3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-mmicromips" } */ + +/* This test ensures that we do not generate microMIPS SWP or LWP + instructions when any component of the accessed memory is volatile; + they are unsafe for such since they might cause replay of partial + accesses if interrupted by an exception. */ + +static void set_csr (volatile void *p, int v) +{ + *(volatile int *) (p) = v; +} + +static int get_csr (volatile void *p) +{ + return *(volatile int *) (p); +} + +int main () +{ + int i, q = 0, p = 0, r = 0; + + for (i = 0; i < 20; i++) + { + set_csr ((volatile void *) 0xbf0100a8, 0xffff0002); + set_csr ((volatile void *) 0xbf0100a4, 0x80000008); + } + + for (i = 0; i < 20; i++) + { + register int k, j; + k = get_csr ((volatile void *) 0xbf0100b8); + p += k; + j = get_csr ((volatile void *) 0xbf0100b4); + r += j; + q = j + k; + } + return q + r + p; +} + +/* { dg-final { scan-assembler-not "\tswp" } } */ +/* { dg-final { scan-assembler-not "\tlwp" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c new file mode 100644 index 000000000..0865b78bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c @@ -0,0 +1,16 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-mgp32 -fpeephole2 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +long long bar (long long, long long); + +MICROMIPS long long +foo (long long n, long long a) +{ + long long i, j; + + i = bar (n, a); + j = bar (n, a); + return i + j; +} +/* { dg-final { scan-assembler "\tmovep\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c new file mode 100644 index 000000000..5a3a8419e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c @@ -0,0 +1,13 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int); + +int MICROMIPS +foo (int n, int a) +{ + return bar (0, 0); +} + +/* { dg-final { scan-assembler "\tmovep\t\\\$4,\\\$5,\\\$0,\\\$0" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c new file mode 100644 index 000000000..ff1ea4b33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c @@ -0,0 +1,18 @@ +/* Check that we can use the swm/lwm instructions. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int, int, int, int); + +MICROMIPS int +foo (int n, int a, int b, int c, int d) +{ + int i, j; + + i = bar (n, a, b, c, d); + j = bar (n, a, b, c, d); + return i + j; +} + +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c new file mode 100644 index 000000000..cb421d5d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c @@ -0,0 +1,16 @@ +/* Check that we can use the save instruction to save spilled arguments. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *a, int b, int c) +{ + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "memory"); + a[b] = 1; + a[c] = 1; +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$23,\\\$fp" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$23,\\\$fp" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c new file mode 100644 index 000000000..22c6f45f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c @@ -0,0 +1,14 @@ +/* Check that we can use the swm instruction to save $16, $17 and $31. */ +/* { dg-options "-mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void bar (void); + +MICROMIPS void +foo (void) +{ + bar (); + asm volatile ("" ::: "$16", "$17"); +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$17,\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$17,\\\$31" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c new file mode 100644 index 000000000..5e337b27b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (long long l1, long long *l2) +{ + *l2 = l1; +} + +/* { dg-final { scan-assembler "\tswp\t\\\$4,0\\(\\\$6\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c new file mode 100644 index 000000000..042322c21 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c new file mode 100644 index 000000000..f0e54647d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c new file mode 100644 index 000000000..5e8f5ea2a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c new file mode 100644 index 000000000..dc1938e47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c new file mode 100644 index 000000000..b489006ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c new file mode 100644 index 000000000..6dde49b8a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c new file mode 100644 index 000000000..938f52d21 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c @@ -0,0 +1,45 @@ +/* { dg-options "-mgp64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-times "\tsdl\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tsdr\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tldl\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tldr\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tswl\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tswr\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tlwl\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tlwr\t" 1 } } */ +/* { dg-final { scan-assembler-not "\tnop" } } */ + +/* Test to make sure we produce the unaligned load/store for + both 64bit and 32bits sized accesses. */ + +struct s +{ + char c; + int i; + long long l; +} __attribute__ ((packed)) s __attribute__((aligned(1) )); + +NOMIPS16 void +sd (long long l) +{ + s.l = l; +} + +NOMIPS16 long long +ld () +{ + return s.l; +} + +NOMIPS16 void +sw (int i) +{ + s.i = i; +} + +NOMIPS16 int +lw () +{ + return s.i; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c new file mode 100644 index 000000000..87c95f525 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c @@ -0,0 +1,48 @@ +/* See PR 52154 for the xfail. */ +/* { dg-do run { xfail { mips_eabi && { hard_float && ilp32 } } } } */ + +#include <stdarg.h> + +extern void abort (void); + +struct __attribute__((aligned(16))) empty {}; + +static void __attribute__((noinline)) +check_args (int count, ...) +{ + va_list va; + int i; + + va_start (va, count); + for (i = 0; i < count; i++) + if (va_arg (va, int) != 1000 + i) + abort (); + + va_arg (va, struct empty); + if (va_arg (va, int) != 2000 + count) + abort (); + + va_end (va); +} + +int +main (void) +{ + struct empty e; + + check_args (1, 1000, e, 2001); + check_args (2, 1000, 1001, e, 2002); + check_args (3, 1000, 1001, 1002, e, 2003); + check_args (4, 1000, 1001, 1002, 1003, e, 2004); + check_args (5, 1000, 1001, 1002, 1003, 1004, e, 2005); + check_args (6, 1000, 1001, 1002, 1003, 1004, 1005, e, 2006); + check_args (7, 1000, 1001, 1002, 1003, 1004, 1005, 1006, e, 2007); + check_args (8, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, e, 2008); + check_args (9, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, e, 2009); + check_args (10, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, e, 2010); + check_args (11, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, e, 2011); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c new file mode 100644 index 000000000..db9ae3430 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c @@ -0,0 +1,8 @@ +/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu + is preferred over mtlo/msac. */ +/* { dg-do compile } */ +/* { dg-options "-march=vr5400 -fpeephole2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; } +NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; } +/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c new file mode 100644 index 000000000..58bdc0893 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c @@ -0,0 +1,8 @@ +/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu + is preferred over mtlo/msac. */ +/* { dg-do compile } */ +/* { dg-options "-march=vr5500 -fpeephole2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; } +NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; } +/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */ |