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| author | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
| commit | 1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch) | |
| tree | c607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.target/arm | |
| parent | 283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff) | |
| download | toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2 toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip | |
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/arm')
2480 files changed, 54960 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c new file mode 100644 index 000000000..4ed3640b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c @@ -0,0 +1,5 @@ +/* Verify that ands are combined. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler-not "#255.*#255" } } */ +int f(int a, int b) { return ((a & 0xff) + (b & 0xff)) & 0xff; } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c new file mode 100644 index 000000000..d9b6006f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c @@ -0,0 +1,36 @@ +/* PR optimization/10467 */ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-O2 -mthumb" } */ + +typedef enum {Ident_1} Enumeration; + +typedef struct record +{ + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + } variant; +} *Rec_Pointer; + +Rec_Pointer Ptr_Glob; + +Proc_1 (Ptr_Val_Par) + Rec_Pointer Ptr_Val_Par; +{ + Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + + *Ptr_Val_Par->Ptr_Comp = *Ptr_Glob; + + if (Next_Record->Discr == Ident_1) + { + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c new file mode 100644 index 000000000..0519dc7ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c @@ -0,0 +1,36 @@ +/* ARM's load-and-call patterns used to allow automodified addresses. + This was wrong, because if the modified register were spilled, + the call would need an output reload. */ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-omit-frame-pointer" } */ +extern void abort (void); +typedef void (*callback) (void); + +static void +foo (callback *first, callback *p) +{ + while (p > first) + { + (*--p) (); +#ifndef __thumb__ + asm ("" : "=r" (p) : "0" (p) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10"); +#endif + } +} + +static void +dummy (void) +{ + static int count; + if (count++ == 1) + abort (); +} + +int +main (void) +{ + callback list[1] = { dummy }; + foo (&list[0], &list[1]); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c new file mode 100644 index 000000000..d82060126 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a8" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ +/* { dg-options "-O3 -mcpu=cortex-a8 -mfpu=vfp3 -mfloat-abi=softfp" } */ + +typedef struct cb +{ + int cxc; + short int pside; +} *CBPTR; +typedef struct rwb +{ + int stx; +} RWB; +extern CBPTR *car; +extern RWB *rwAr; +extern int nts; +extern int nRws; +void f() +{ + CBPTR pptr ; + int k_lt, k_rt, k_span, rw, p, rt; + int sa ; + k_rt = 0; + k_lt = 10000000; + for (rw = 1; rw <= nRws; rw++) + k_lt = rwAr[rw].stx; + k_span = k_rt - k_lt; + for (; p <= nts; p++) + { + pptr = car[p]; + if (pptr->pside == 3) + pptr->cxc += (int)(((double)rt / (double) k_span) *((double) sa)); + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c new file mode 100644 index 000000000..c370ae60c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c @@ -0,0 +1,14 @@ +/* Check that CONST_INT is not forced into REG before PLUS. */ +/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +typedef int Arr2[50][50]; + +void +foo (Arr2 a2, int i) +{ + a2[i+20][i] = 1; +} + +/* { dg-final { scan-rtl-dump-not "\\\(set \\\(reg:SI \[0-9\]*\\\)\[\n\r\]+\[ \t]*\\\(const_int 4000" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp new file mode 100644 index 000000000..746429dad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h new file mode 100644 index 000000000..06a92c3ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h @@ -0,0 +1,125 @@ + +#define IN_FRAMEWORK + +#ifdef VFP +#define D0 0 +#define D1 8 +#define D2 16 +#define D3 24 +#define D4 32 +#define D5 40 +#define D6 48 +#define D7 56 + +#ifdef NEON +#define Q0 D0 +#define Q1 D2 +#define Q2 D4 +#define Q3 D6 +#endif + +#define S0 64 +#define S1 68 +#define S2 72 +#define S3 76 +#define S4 80 +#define S5 84 +#define S6 88 +#define S7 92 +#define S8 86 +#define S9 100 +#define S10 104 +#define S11 108 +#define S12 112 +#define S13 116 +#define S14 120 +#define S15 124 + +#define CORE_REG_START 128 +#else +#define CORE_REG_START 0 +#endif + +#define R0 CORE_REG_START +#define R1 (R0 + 4) +#define R2 (R1 + 4) +#define R3 (R2 + 4) +#define STACK (R3 + 4) + + + +extern void abort (void); + +__attribute__((naked)) void dumpregs () __asm("myfunc"); +__attribute__((naked)) void dumpregs () +{ + asm( + "mov ip, sp\n\t" + "stmfd sp!, {r0-r3}\n\t" +#ifdef VFP + "fstmdbs sp!, {s0-s15}\n\t" + "fstmdbd sp!, {d0-d7}\n\t" +#endif + "mov r0, sp\n\t" + "stmfd sp!, {ip, r14}\n\t" + "bl testfunc\n\t" + "ldmfd sp!, {r0, r14}\n\t" + "mov sp, r0\n\t" + "bx lr"); +} + + +#define LAST_ARG(type,val,offset) { type __x = val; if (memcmp(&__x, stack+offset, sizeof(type)) != 0) abort(); } +#define ARG(type,val,offset) LAST_ARG(type, val, offset) +#define ANON(type,val,offset) LAST_ARG(type, val, offset) +#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset) +#define DOTS + +void testfunc(char* stack) +{ +#include TESTFILE + return; +} + +#undef LAST_ARG +#undef ARG +#undef DOTS +#undef ANON +#undef LAST_ANON +#define LAST_ARG(type,val,offset) type +#define ARG(type,val,offset) LAST_ARG(type, val, offset), +#define DOTS ... +#define ANON(type,val, offset) +#define LAST_ANON(type,val, offset) + +#ifndef MYFUNCTYPE +#define MYFUNCTYPE void +#endif + +#ifndef PCSATTR +#define PCSATTR +#endif + +MYFUNCTYPE myfunc( +#include TESTFILE +) PCSATTR; + +#undef LAST_ARG +#undef ARG +#undef DOTS +#undef ANON +#undef LAST_ANON +#define LAST_ARG(type,val,offset) val +#define ARG(type,val,offset) LAST_ARG(type, val, offset), +#define DOTS +#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset) +#define ANON(type,val,offset) LAST_ARG(type, val, offset), + + +int main() +{ + myfunc( +#include TESTFILE +); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h new file mode 100644 index 000000000..08b75f7b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h @@ -0,0 +1,33 @@ + + +#include "arm_neon.h" + +const int32x4_t i32x4_constvec1 = { 1101, 1102, 1103, 1104}; +const int32x4_t i32x4_constvec2 = { 2101, 2102, 2103, 2104}; + +#define ELEM(INDEX) .val[INDEX] + +const int32x4x2_t i32x4x2_constvec1 = {ELEM(0) = {0xaddebccb,11,12,13}, + ELEM(1) = {14, 15, 16, 17} }; + +const int32x4x2_t i32x4x2_constvec2 = { ELEM(0) = {0xaadebcca,11,12,13}, + ELEM(1) = {140, 15, 16, 17}}; + +const int32x4x3_t i32x4x3_constvec1 = { ELEM(0) = {0xabbccdde,8, 9, 10}, + ELEM(1) = {0xabcccdde, 26, 27, 28}, + ELEM(2) = {0xaccccddf, 29, 30, 31}}; + +const int32x4x3_t i32x4x3_constvec2 = { ELEM(0) = {0xbccccdd0,8, 9, 10}, + ELEM(1) = {0xbdfe1000, 26, 27, 28}, + ELEM(2) = {0xaccccddf, 29, 30, 31}}; +const float32x4x2_t f32x4x2_constvec1 = + { ELEM(0) = { 7.101f, 0.201f, 0.301f, 0.401f} , + ELEM(1) = { 8.101f, 0.501f, 0.601f, 0.701f} }; + +const float32x4x2_t f32x4x2_constvec2 = + { ELEM(0) = { 11.99f , 11.21f, 1.27f, 8.74f}, + ELEM(1) = { 13.45f , 1.23f ,1.24f, 1.26f}}; + +const int32x2_t i32x2_constvec1 = { 1283, 1345 }; +const int32x2x2_t i32x2x2_constvec1 = { ELEM(0) = { 0xabcdefab, 32 }, + ELEM(1) = { 0xabcdefbc, 33 }}; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c new file mode 100644 index 000000000..47ae2f65f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect1.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c new file mode 100644 index 000000000..f7b532a3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c @@ -0,0 +1,23 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect2.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */ +ARG(float, 3.0f, S4) /* D2, Q1 occupied. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c new file mode 100644 index 000000000..e5426b0ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c @@ -0,0 +1,26 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect3.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(double, 11.0, STACK+sizeof(int32x4x2_t)) /* No backfill in D3. */ +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c new file mode 100644 index 000000000..96bd09c45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect4.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(float, 5.0f, S5) /* Backfill in S5. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c new file mode 100644 index 000000000..59e58c96c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c @@ -0,0 +1,28 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect5.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(float, 3.0f, S4) /* D2, Q1 */ +ARG(float32x4x2_t, f32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */ +ARG(double, 12.0, D3) /* Backfill this particular argument. */ +ARG(int32x4x2_t, i32x4x2_constvec2, STACK) +ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */ +LAST_ARG(int, 3, R0) + +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c new file mode 100644 index 000000000..fcb399882 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c @@ -0,0 +1,24 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect6.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */ +ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */ +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c new file mode 100644 index 000000000..f8d1d0730 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect7.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(float, 24.3f, S0) /* S0 , D0, Q0 */ +ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */ +ARG(double, 25.6, D1) +ARG(float, 12.67f, S1) +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +ARG(double, 2.47, STACK+sizeof(int32x4x3_t)) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c new file mode 100644 index 000000000..f2c295d84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c @@ -0,0 +1,27 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-add-options arm_neon } */ + + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect8.c" +#include "neon-constants.h" + + +#include "abitest.h" +#else + +ARG(float, 24.3f, S0) /* S0 , D0, Q0 */ +ARG(int32x2_t, i32x2_constvec1, D1) /* D1 */ +ARG(double, 25.6, D2) +ARG(float, 12.67f, S1) +ARG(int32x4x3_t, i32x4x3_constvec2, STACK) +ARG(double, 2.47, STACK+sizeof(int32x4x3_t)) +LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c new file mode 100644 index 000000000..9fb926dbd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c @@ -0,0 +1,17 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp1.c" +#include "abitest.h" + +#else + ARG(int, 4, R0) + ARG(double, 4.0, D0) + LAST_ARG(int, 3, R1) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c new file mode 100644 index 000000000..c3a1b39a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c @@ -0,0 +1,38 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp10.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + /* A variadic function passes using the base ABI */ + ARG(double, 11.0, R0) + DOTS + ANON(struct z, a, R2) + ANON(struct z, b, STACK+24) + LAST_ANON(double, 0.5, STACK+56) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c new file mode 100644 index 000000000..a496a3ed5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c @@ -0,0 +1,39 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp11.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#define MYFUNCTYPE struct y + +#include "abitest.h" +#else + ARG(int, 7, R1) + ARG(struct y, v, R2) + ARG(struct z, a, D0) + ARG(struct z, b, D4) + LAST_ARG(double, 0.5, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c new file mode 100644 index 000000000..bbfa3df90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c @@ -0,0 +1,38 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp12.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + ARG(int, 7, R0) + ARG(struct y, v, R1) + ARG(struct z, a, D0) + ARG(double, 1.0, D4) + ARG(struct z, b, STACK+8) + LAST_ARG(double, 0.5, STACK+40) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c new file mode 100644 index 000000000..a46361c09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c @@ -0,0 +1,39 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp13.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + ARG(int, 7, R0) + ARG(int, 9, R1) + ARG(struct z, a, D0) + ARG(double, 1.0, D4) + ARG(struct z, b, STACK) + ARG(int, 4, R2) + LAST_ARG(double, 0.5, STACK+32) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c new file mode 100644 index 000000000..43c19f2dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c @@ -0,0 +1,24 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp14.c" + +#include "abitest.h" +#else + ARG(double, 1.0, D0) + ARG(double, 2.0, D1) + ARG(double, 3.0, D2) + ARG(double, 4.0, D3) + ARG(double, 5.0, D4) + ARG(double, 6.0, D5) + ARG(double, 7.0, D6) + ARG(double, 8.0, D7) + ARG(double, 9.0, STACK) + LAST_ARG(double, 10.0, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c new file mode 100644 index 000000000..c98ca3810 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c @@ -0,0 +1,20 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp15.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include "abitest.h" +#else + ARG(double, 1.0, R0) + ARG(double, 2.0, R2) + ARG(double, 3.0, STACK) + LAST_ARG(double, 4.0, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c new file mode 100644 index 000000000..956bc0ab5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c @@ -0,0 +1,22 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp16.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include "abitest.h" +#else + ARG(float, 1.0f, R0) + ARG(float, 2.0f, R1) + ARG(float, 3.0f, R2) + ARG(float, 4.0f, R3) + ARG(float, 5.0f, STACK) + LAST_ARG(float, 5.0f, STACK+4) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c new file mode 100644 index 000000000..9044ec221 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c @@ -0,0 +1,20 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp17.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include "abitest.h" +#else + ARG(float, 1.0f, R0) + ARG(double, 2.0, R2) + ARG(float, 3.0f, STACK) + LAST_ARG(double, 4.0, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c new file mode 100644 index 000000000..bfe90675b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c @@ -0,0 +1,19 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp2.c" +#include "abitest.h" + +#else + ARG(float, 1.0f, S0) + ARG(double, 4.0, D1) + ARG(float, 2.0f, S1) + ARG(double, 5.0, D2) + LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c new file mode 100644 index 000000000..0e645d711 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c @@ -0,0 +1,21 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp3.c" + +__complex__ x = 1.0+2.0i; + +#include "abitest.h" +#else + ARG(float, 1.0f, S0) + ARG(__complex__ double, x, D1) + ARG(float, 2.0f, S1) + ARG(double, 5.0, D3) + LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c new file mode 100644 index 000000000..46dc4b98a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c @@ -0,0 +1,20 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp4.c" + +__complex__ float x = 1.0f + 2.0fi; +#include "abitest.h" +#else + ARG(float, 1.0f, S0) + ARG(__complex__ float, x, S1) + ARG(float, 2.0f, S3) + ARG(double, 5.0, D2) + LAST_ARG(int, 3, R0) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c new file mode 100644 index 000000000..216d98ea8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c @@ -0,0 +1,30 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp5.c" + +__complex__ float x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +#include "abitest.h" +#else + ARG(float, 1.0f, S0) + ARG(__complex__ float, x, S1) + ARG(float, 2.0f, S3) + ARG(double, 5.0, D2) + ARG(struct y, v, R0) + LAST_ARG(int, 3, STACK) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c new file mode 100644 index 000000000..4d718da45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c @@ -0,0 +1,30 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp6.c" + +__complex__ float x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +#include "abitest.h" +#else + ARG(struct y, v, R0) + ARG(float, 1.0f, S0) + ARG(__complex__ float, x, S1) + ARG(float, 2.0f, S3) + ARG(double, 5.0, D2) + LAST_ARG(int, 3, STACK) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c new file mode 100644 index 000000000..3e57e45c7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c @@ -0,0 +1,37 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp7.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + ARG(struct z, a, D0) + ARG(struct z, b, D4) + ARG(double, 0.5, STACK) + ARG(int, 7, R0) + LAST_ARG(struct y, v, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c new file mode 100644 index 000000000..e55006885 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c @@ -0,0 +1,37 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp8.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + ARG(int, 7, R0) + ARG(struct y, v, R1) + ARG(struct z, a, D0) + ARG(struct z, b, D4) + LAST_ARG(double, 0.5, STACK+8) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c new file mode 100644 index 000000000..c2be6bf4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c @@ -0,0 +1,38 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp9.c" + +__complex__ x = 1.0+2.0i; + +struct y +{ + int p; + int q; + int r; + int s; +} v = { 1, 2, 3, 4 }; + +struct z +{ + double x[4]; +}; + +struct z a = { 5.0, 6.0, 7.0, 8.0 }; +struct z b = { 9.0, 10.0, 11.0, 12.0 }; + +#include "abitest.h" +#else + /* A variadic function passes using the base ABI */ + ARG(int, 7, R0) + DOTS + ANON(struct z, a, R2) + ANON(struct z, b, STACK+24) + LAST_ANON(double, 0.5, STACK+56) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp new file mode 100644 index 000000000..c8622697e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2013-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c new file mode 100644 index 000000000..d6f35e9fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c @@ -0,0 +1,20 @@ +/* Test the crc32b ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32b (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint8_t arg1_uint8_t; + + out_uint32_t = __crc32b (arg0_uint32_t, arg1_uint8_t); +} + +/* { dg-final { scan-assembler "crc32b\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c new file mode 100644 index 000000000..44aea21fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c @@ -0,0 +1,20 @@ +/* Test the crc32cb ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32cb (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint8_t arg1_uint8_t; + + out_uint32_t = __crc32cb (arg0_uint32_t, arg1_uint8_t); +} + +/* { dg-final { scan-assembler "crc32cb\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c new file mode 100644 index 000000000..cb7ee0df0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c @@ -0,0 +1,20 @@ +/* Test the crc32cd ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32cd (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint64_t arg1_uint64_t; + + out_uint32_t = __crc32cd (arg0_uint32_t, arg1_uint64_t); +} + +/* { dg-final { scan-assembler-times "crc32cw\t...?, ...?, ...?\n" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c new file mode 100644 index 000000000..d8e733894 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c @@ -0,0 +1,20 @@ +/* Test the crc32ch ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32ch (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint16_t arg1_uint16_t; + + out_uint32_t = __crc32ch (arg0_uint32_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "crc32ch\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c new file mode 100644 index 000000000..84384c5d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c @@ -0,0 +1,20 @@ +/* Test the crc32cw ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32cw (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint32_t arg1_uint32_t; + + out_uint32_t = __crc32cw (arg0_uint32_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "crc32cw\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c new file mode 100644 index 000000000..c90fad9a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c @@ -0,0 +1,20 @@ +/* Test the crc32d ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32d (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint64_t arg1_uint64_t; + + out_uint32_t = __crc32d (arg0_uint32_t, arg1_uint64_t); +} + +/* { dg-final { scan-assembler-times "crc32w\t...?, ...?, ...?\n" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c new file mode 100644 index 000000000..c21a4ae3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c @@ -0,0 +1,20 @@ +/* Test the crc32h ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32h (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint16_t arg1_uint16_t; + + out_uint32_t = __crc32h (arg0_uint32_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "crc32h\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c new file mode 100644 index 000000000..60cd09e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c @@ -0,0 +1,20 @@ +/* Test the crc32w ACLE intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crc_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crc } */ + +#include "arm_acle.h" + +void test_crc32w (void) +{ + uint32_t out_uint32_t; + uint32_t arg0_uint32_t; + uint32_t arg1_uint32_t; + + out_uint32_t = __crc32w (arg0_uint32_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "crc32w\t...?, ...?, ...?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c new file mode 100644 index 000000000..cd0d08386 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +unsigned long long +muld (unsigned long long X, unsigned long long Y) +{ + unsigned long long mask = 0xffffffffull; + return (X & mask) * (Y & mask); +} + +/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c new file mode 100644 index 000000000..efe71f42e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +long long muld(long long X, long long Y) +{ + return X & ~1; +} + +/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp new file mode 100644 index 000000000..54ff2370a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp @@ -0,0 +1,47 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# This variable should only apply to tests called in this exp file. +global dg_runtest_extra_prunes +set dg_runtest_extra_prunes "" +lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch" + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +set dg_runtest_extra_prunes "" +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c new file mode 100644 index 000000000..452ebf4de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c @@ -0,0 +1,13 @@ +/* ARM and Thumb asm statements should be able to access the constant + pool. */ +/* { dg-do compile } */ +extern unsigned x[]; +unsigned *trapTable() +{ + unsigned *i; + + __asm__ volatile("ldr %0,%1" : "=r"(i) : "m"(x[0])); + + return i; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c new file mode 100644 index 000000000..ea6fdd96d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c new file mode 100644 index 000000000..ccfa31c34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c new file mode 100644 index 000000000..52bcf99e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c new file mode 100644 index 000000000..0c30922db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c new file mode 100644 index 000000000..0354717cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-consume.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c new file mode 100644 index 000000000..7716994f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c new file mode 100644 index 000000000..4b72fd95b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c new file mode 100644 index 000000000..8582e4f1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c new file mode 100644 index 000000000..70b5b9ebb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c new file mode 100644 index 000000000..a6f5a6df6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c new file mode 100644 index 000000000..43195bd82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_arch_v6_ok } */ +/* { dg-add-options arm_arch_v6 } */ +/* { dg-final { scan-assembler-not "orr\[ \t\]" } } */ +/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb } } } } */ + +/* revsh */ +short swaps16 (short x) +{ + return __builtin_bswap16 (x); +} + +extern short foos16 (short); + +/* revshne */ +short swaps16_cond (short x, int y) +{ + short z = x; + if (y) + z = __builtin_bswap16 (x); + return foos16 (z); +} + +/* rev16 */ +unsigned short swapu16 (unsigned short x) +{ + return __builtin_bswap16 (x); +} + +extern unsigned short foou16 (unsigned short); + +/* rev16ne */ +unsigned short swapu16_cond (unsigned short x, int y) +{ + unsigned short z = x; + if (y) + z = __builtin_bswap16 (x); + return foou16 (z); +} + +/* rev */ +int swaps32 (int x) { + return __builtin_bswap32 (x); +} + +extern int foos32 (int); + +/* revne */ +int swaps32_cond (int x, int y) +{ + int z = x; + if (y) + z = __builtin_bswap32 (x); + return foos32 (z); +} + +/* rev */ +unsigned int swapu32 (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +extern unsigned int foou32 (unsigned int); + +/* revne */ +unsigned int swapsu2 (unsigned int x, int y) +{ + int z = x; + if (y) + z = __builtin_bswap32 (x); + return foou32 (z); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c new file mode 100644 index 000000000..6920f004e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_arch_v6_ok } */ +/* { dg-add-options arm_arch_v6 } */ +/* { dg-final { scan-assembler-not "orr\[ \t\]" } } */ + +unsigned short swapu16_1 (unsigned short x) +{ + return (x << 8) | (x >> 8); +} + +unsigned short swapu16_2 (unsigned short x) +{ + return (x >> 8) | (x << 8); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c new file mode 100644 index 000000000..4ff8d253e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ + +void +trap () +{ + __builtin_trap (); +} + +/* { dg-final { scan-assembler "0xe7f000f0" { target { arm_nothumb } } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c new file mode 100644 index 000000000..0d6b7c266 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler-not "\tbl\t" } } */ +/* { dg-final { scan-assembler-not "__aeabi" } } */ +int x, y; + +#define TEST_EXPR(NAME, ARGS, EXPR) \ + int NAME##1 ARGS { return (EXPR); } \ + int NAME##2 ARGS { return !(EXPR); } \ + int NAME##3 ARGS { return (EXPR) ? x : y; } \ + void NAME##4 ARGS { if (EXPR) x++; } \ + void NAME##5 ARGS { if (!(EXPR)) x++; } + +#define TEST(NAME, TYPE, OPERATOR) \ + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \ + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \ + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \ + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \ + TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \ + TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1) + +#define TEST_OP(NAME, OPERATOR) \ + TEST (sc_##NAME, signed char, OPERATOR) \ + TEST (uc_##NAME, unsigned char, OPERATOR) \ + TEST (ss_##NAME, short, OPERATOR) \ + TEST (us_##NAME, unsigned short, OPERATOR) \ + TEST (si_##NAME, int, OPERATOR) \ + TEST (ui_##NAME, unsigned int, OPERATOR) \ + TEST (sll_##NAME, long long, OPERATOR) \ + TEST (ull_##NAME, unsigned long long, OPERATOR) + +TEST_OP (eq, ==) +TEST_OP (ne, !=) +TEST_OP (lt, <) +TEST_OP (gt, >) +TEST_OP (le, <=) +TEST_OP (ge, >=) diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c new file mode 100644 index 000000000..ed6b609ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */ +/* { dg-final { scan-assembler-not "\tbl\t" } } */ +/* { dg-final { scan-assembler-not "__aeabi" } } */ +int x, y; + +#define EQ(X, Y) ((X) == (Y)) +#define NE(X, Y) ((X) != (Y)) +#define LT(X, Y) ((X) < (Y)) +#define GT(X, Y) ((X) > (Y)) +#define LE(X, Y) ((X) <= (Y)) +#define GE(X, Y) ((X) >= (Y)) + +#define TEST_EXPR(NAME, ARGS, EXPR) \ + int NAME##1 ARGS { return (EXPR); } \ + int NAME##2 ARGS { return !(EXPR); } \ + int NAME##3 ARGS { return (EXPR) ? x : y; } \ + void NAME##4 ARGS { if (EXPR) x++; } \ + void NAME##5 ARGS { if (!(EXPR)) x++; } + +#define TEST(NAME, TYPE, OPERATOR) \ + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \ + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \ + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \ + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \ + TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \ + TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1)) + +#define TEST_OP(NAME, OPERATOR) \ + TEST (f_##NAME, float, OPERATOR) \ + TEST (d_##NAME, double, OPERATOR) \ + TEST (ld_##NAME, long double, OPERATOR) + +TEST_OP (eq, EQ) +TEST_OP (ne, NE) +TEST_OP (lt, LT) +TEST_OP (gt, GT) +TEST_OP (le, LE) +TEST_OP (ge, GE) +TEST_OP (blt, __builtin_isless) +TEST_OP (bgt, __builtin_isgreater) +TEST_OP (ble, __builtin_islessequal) +TEST_OP (bge, __builtin_isgreaterequal) +/* This one should be expanded into separate ordered and equality + comparisons. */ +TEST_OP (blg, __builtin_islessgreater) +TEST_OP (bun, __builtin_isunordered) diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c new file mode 100644 index 000000000..295c29fe8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-calls" } */ +/* { dg-final { scan-assembler-not "bl\[^\n\]*dump_stack" } } */ + +extern void dump_stack (void) __attribute__ ((__cold__)) __attribute__ ((noinline)); +struct thread_info { + struct task_struct *task; +}; +extern struct thread_info *current_thread_info (void); + +void dump_stack (void) +{ + unsigned long stack; + show_stack ((current_thread_info ()->task), &stack); +} + +void die (char *str, void *fp, int nr) +{ + dump_stack (); + while (1); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c new file mode 100644 index 000000000..a64f20e06 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c @@ -0,0 +1,16 @@ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-options "-O2 -mcpu=cortex-a8" } */ +/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */ + +typedef int SItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +void abort (void); + +SItype +__mulvsi3 (SItype a, SItype b) +{ + const DItype w = (DItype) a * (DItype) b; + if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1)) + abort (); + return w; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c new file mode 100644 index 000000000..e9fd6cb45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { arm_thumb1 } } */ +/* { dg-options "-O" } */ + +void foo (unsigned long r[], unsigned int d) +{ + int i, n = d / 32; + for (i = 0; i < n; ++i) + r[i] = 0; +} + +/* { dg-final { scan-assembler "lsrs\tr\[0-9\]" { target arm_thumb2 } } } */ +/* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2 } } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c new file mode 100644 index 000000000..450bd9d6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c @@ -0,0 +1,13 @@ +/* Check that %? in inline asm expands to nothing. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +int b; +int foo(int a) +{ + if (a) + b = 42; + asm ("test%?me":"=r"(a):"0"(a)); + return a; +} +/* { dg-final { scan-assembler "testme" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c new file mode 100644 index 000000000..e0b25b93c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint8x16_t a, b, c; + int i = 0; + + for (i = 0; i < 16; ++i) + { + a[i] = i; + b[i] = 15 - i; + } + c = vaesdq_u8 (a, b); + return c[0]; +} + +/* { dg-final { scan-assembler "aesd.8\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c new file mode 100644 index 000000000..f47864662 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint8x16_t a, b, c; + int i = 0; + + for (i = 0; i < 16; ++i) + { + a[i] = i; + b[i] = 15 - i; + } + c = vaeseq_u8 (a, b); + return c[0]; +} + +/* { dg-final { scan-assembler "aese.8\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c new file mode 100644 index 000000000..fbbfda609 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint8x16_t a, b; + int i = 0; + + for (i = 0; i < 16; ++i) + a[i] = i; + + b = vaesimcq_u8 (a); + return b[0]; +} + +/* { dg-final { scan-assembler "aesimc.8\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c new file mode 100644 index 000000000..cae8bd096 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint8x16_t a, b; + int i = 0; + + for (i = 0; i < 16; ++i) + a[i] = i; + + b = vaesmcq_u8 (a); + return b[0]; +} + +/* { dg-final { scan-assembler "aesmc.8\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c new file mode 100644 index 000000000..96c0e9a75 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +poly128_t +foo (poly128_t* ptr) +{ + return vldrq_p128 (ptr); +} + +/* { dg-final { scan-assembler "vld1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c new file mode 100644 index 000000000..1290f31a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +poly128_t +foo (void) +{ + poly64x2_t a = { 0xdeadbeef, 0xadabcaca }; + poly64x2_t b = { 0xdcdcdcdc, 0xbdbdbdbd }; + return vmull_high_p64 (a, b); +} + +/* { dg-final { scan-assembler "vmull.p64.*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c new file mode 100644 index 000000000..b788dca52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +poly128_t +foo (void) +{ + poly64_t a = 0xdeadbeef; + poly64_t b = 0xadadadad; + return vmull_p64 (a, b); +} + +/* { dg-final { scan-assembler "vmull.p64.*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c new file mode 100644 index 000000000..4dc9dee66 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32_t hash = 0xdeadbeef; + uint32x4_t a = {0, 1, 2, 3}; + uint32x4_t b = {3, 2, 1, 0}; + + uint32x4_t res = vsha1cq_u32 (a, hash, b); + return res[0]; +} + +/* { dg-final { scan-assembler "sha1c.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c new file mode 100644 index 000000000..dee277485 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32_t val = 0xdeadbeef; + return vsha1h_u32 (val); +} + +/* { dg-final { scan-assembler "sha1h.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c new file mode 100644 index 000000000..672b93a97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32_t hash = 0xdeadbeef; + uint32x4_t a = {0, 1, 2, 3}; + uint32x4_t b = {3, 2, 1, 0}; + + uint32x4_t res = vsha1mq_u32 (a, hash, b); + return res[0]; +} + +/* { dg-final { scan-assembler "sha1m.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c new file mode 100644 index 000000000..ff508e0dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32_t hash = 0xdeadbeef; + uint32x4_t a = {0, 1, 2, 3}; + uint32x4_t b = {3, 2, 1, 0}; + + uint32x4_t res = vsha1pq_u32 (a, hash, b); + return res[0]; +} + +/* { dg-final { scan-assembler "sha1p.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c new file mode 100644 index 000000000..4435d1800 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + uint32x4_t c = {3, 2, 1, 0}; + + uint32x4_t res = vsha1su0q_u32 (a, b, c); + return res[0]; +} + +/* { dg-final { scan-assembler "sha1su0.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c new file mode 100644 index 000000000..8610c4de2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + + uint32x4_t res = vsha1su1q_u32 (a, b); + return res[0]; +} + +/* { dg-final { scan-assembler "sha1su1.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c new file mode 100644 index 000000000..4a3e2e158 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + uint32x4_t c = {3, 2, 1, 0}; + + uint32x4_t res = vsha256h2q_u32 (a, b, c); + return res[0]; +} + +/* { dg-final { scan-assembler "sha256h2.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c new file mode 100644 index 000000000..49577f2b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + uint32x4_t c = {3, 2, 1, 0}; + + uint32x4_t res = vsha256hq_u32 (a, b, c); + return res[0]; +} + +/* { dg-final { scan-assembler "sha256h.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c new file mode 100644 index 000000000..cc4305d38 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + + uint32x4_t res = vsha256su0q_u32 (a, b); + return res[0]; +} + +/* { dg-final { scan-assembler "sha256su0.32\tq\[0-9\]+, q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c new file mode 100644 index 000000000..430f38adc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +int +foo (void) +{ + uint32x4_t a = {0xd, 0xe, 0xa, 0xd}; + uint32x4_t b = {0, 1, 2, 3}; + uint32x4_t c = {3, 2, 1, 0}; + + uint32x4_t res = vsha256su1q_u32 (a, b, c); + return res[0]; +} + +/* { dg-final { scan-assembler "sha256su1.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c new file mode 100644 index 000000000..acd8af34f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void +foo (poly128_t* ptr, poly128_t val) +{ + vstrq_p128 (ptr, val); +} + +/* { dg-final { scan-assembler "vst1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c new file mode 100644 index 000000000..2455f6740 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2" } */ + +unsigned int functest(unsigned int x) +{ + return __builtin_ctz(x); +} + +/* { dg-final { scan-assembler "rbit" } } */ +/* { dg-final { scan-assembler "clz" } } */ +/* { dg-final { scan-assembler-not "rsb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c new file mode 100644 index 000000000..c2959165b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v5_ok } */ +/* { dg-options "-std=gnu99" } */ +/* { dg-add-options arm_arch_v5 } */ +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */ +/* { dg-message "file included" "In file included" { target *-*-* } 0 } */ + +#include "../../gcc.dg/di-longlong64-sync-1.c" + +/* On an old ARM we have no ldrexd or strexd so we have to use helpers. */ +/* { dg-final { scan-assembler-not "ldrexd" } } */ +/* { dg-final { scan-assembler-not "strexd" } } */ +/* { dg-final { scan-assembler "__sync_" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c new file mode 100644 index 000000000..517c4a89d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-options "-marm -std=gnu99" } */ +/* { dg-require-effective-target arm_arch_v6k_ok } */ +/* { dg-add-options arm_arch_v6k } */ +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ +/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */ +/* { dg-message "file included" "In file included" { target *-*-* } 0 } */ + +#include "../../gcc.dg/di-longlong64-sync-1.c" + +/* We should be using ldrexd, strexd and no helpers or shorter ldrex. */ +/* { dg-final { scan-assembler-times "\tldrexd" 48 } } */ +/* { dg-final { scan-assembler-times "\tstrexd" 48 } } */ +/* { dg-final { scan-assembler-not "__sync_" } } */ +/* { dg-final { scan-assembler-not "ldrex\t" } } */ +/* { dg-final { scan-assembler-not "strex\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c new file mode 100644 index 000000000..7f112eeab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c @@ -0,0 +1,24 @@ +/* Performing a 64-bit division should not pull in the unwinder. */ + +/* { dg-do run { target { ! *-*-linux* } } } */ +/* { dg-options "-O0" } */ + +#include <stdlib.h> + +long long +foo (long long c, long long d) +{ + return c/d; +} + +long long x = 0; +long long y = 1; + +extern int (*_Unwind_RaiseException) (void *) __attribute__((weak)); + +int main(void) +{ + if (&_Unwind_RaiseException != NULL) + abort ();; + return foo (x, y); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c new file mode 100644 index 000000000..c90f5ff08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c @@ -0,0 +1,342 @@ +/* { dg-do run { target arm*-*-symbianelf* arm*-*-eabi* } } */ +/* { dg-options "" } */ + +/* This file tests most of the non-C++ run-time helper functions + described in Section 4 of the "Run-Time ABI for the ARM + Architecture". These are basic tests; they do not try to validate + all of the corner cases in these routines. + + The functions not tested here are: + + __aeabi_cdcmpeq + __aeabi_cdcmple + __aeabi_cdrcmple + __aeabi_cfcmpeq + __aeabi_cfcmple + __aeabi_cfrcmple + __aeabi_ldivmod + __aeabi_uldivmod + __aeabi_idivmod + __aeabi_uidivmod + + These functions have non-standard calling conventions that would + require the use of inline assembly to test. It would be good to + add such tests, but they have not yet been implemented. + + There are also no tests for the "division by zero", "memory copying, + clearing, and setting" functions. */ + +#include <stdio.h> +#include <stdlib.h> +#include <math.h> + +/* All these functions are defined to use the base ABI, so use the + attribute to ensure the tests use the base ABI to call them even + when the VFP ABI is otherwise in effect. */ +#define PCS __attribute__((pcs("aapcs"))) + +#define decl_float(code, type) \ + extern type __aeabi_ ## code ## add (type, type) PCS; \ + extern type __aeabi_ ## code ## div (type, type) PCS; \ + extern type __aeabi_ ## code ## mul (type, type) PCS; \ + extern type __aeabi_ ## code ## neg (type) PCS; \ + extern type __aeabi_ ## code ## rsub (type, type) PCS; \ + extern type __aeabi_ ## code ## sub (type, type) PCS; \ + extern int __aeabi_ ## code ## cmpeq (type, type) PCS; \ + extern int __aeabi_ ## code ## cmplt (type, type) PCS; \ + extern int __aeabi_ ## code ## cmple (type, type) PCS; \ + extern int __aeabi_ ## code ## cmpge (type, type) PCS; \ + extern int __aeabi_ ## code ## cmpgt (type, type) PCS; \ + extern int __aeabi_ ## code ## cmpun (type, type) PCS; \ + extern int __aeabi_ ## code ## 2iz (type) PCS; \ + extern unsigned int __aeabi_ ## code ## 2uiz (type) PCS; \ + extern long long __aeabi_ ## code ## 2lz (type) PCS; \ + extern unsigned long long __aeabi_ ## code ## 2ulz (type) PCS; \ + extern type __aeabi_i2 ## code (int) PCS; \ + extern type __aeabi_ui2 ## code (int) PCS; \ + extern type __aeabi_l2 ## code (long long) PCS; \ + extern type __aeabi_ul2 ## code (unsigned long long) PCS; \ + \ + type code ## zero = 0.0; \ + type code ## one = 1.0; \ + type code ## two = 2.0; \ + type code ## four = 4.0; \ + type code ## minus_one = -1.0; \ + type code ## minus_two = -2.0; \ + type code ## minus_four = -4.0; \ + type code ## epsilon = 1E-32; \ + type code ## NaN = 0.0 / 0.0; + +decl_float (d, double) +decl_float (f, float) + +extern float __aeabi_d2f (double) PCS; +extern double __aeabi_f2d (float) PCS; +extern long long __aeabi_lmul (long long, long long); +extern long long __aeabi_llsl (long long, int); +extern long long __aeabi_llsr (long long, int); +extern long long __aeabi_lasr (long long, int); +extern int __aeabi_lcmp (long long, long long); +extern int __aeabi_ulcmp (unsigned long long, unsigned long long); +extern int __aeabi_idiv (int, int); +extern unsigned int __aeabi_uidiv (unsigned int, unsigned int); +extern int __aeabi_uread4 (void *); +extern int __aeabi_uwrite4 (int, void *); +extern long long __aeabi_uread8 (void *); +extern long long __aeabi_uwrite8 (long long, void *); + +#define eq(a, b, type, abs, epsilon, format) \ + { \ + type a1; \ + type b1; \ + \ + a1 = a; \ + b1 = b; \ + if (abs (a1 - b1) > epsilon) \ + { \ + fprintf (stderr, "%d: Test %s == %s\n", __LINE__, #a, #b); \ + fprintf (stderr, "%d: " format " != " format "\n", \ + __LINE__, a1, b1); \ + abort (); \ + } \ + } + +#define ieq(a, b) eq (a, b, int, abs, 0, "%d") +#define ueq(a, b) eq (a, b, unsigned int, abs, 0, "%u") +#define leq(a, b) eq (a, b, long long, abs, 0, "%lld") +#define uleq(a, b) eq (a, b, unsigned long long, abs, 0, "%llu") +#define feq(a, b) eq (a, b, float, fabs, fepsilon, "%f") +#define deq(a, b) eq (a, b, double, fabs, depsilon, "%g") + +#define NUM_CMP_VALUES 6 + +/* Values picked to cover a range of small, large, positive and negative. */ +static unsigned int cmp_val[NUM_CMP_VALUES] = +{ + 0, + 1, + 0x40000000, + 0x80000000, + 0xc0000000, + 0xffffffff +}; + +/* All combinations for each of the above values. */ +#define ulcmp(l, s, m) \ + s, l, l, l, l, l, m, s, l, l, l, l, \ + m, m, s, l, l, l, m, m, m, s, l, l, \ + m, m, m, m, s, l, m, m, m, m, m, s + +#define lcmp(l, s, m) \ + s, l, l, m, m, m, m, s, l, m, m, m, \ + m, m, s, m, m, m, l, l, l, s, l, l, \ + l, l, l, m, s, l, l, l, l, m, m, s + +/* All combinations of the above for high/low words. */ +static int lcmp_results[] = +{ + lcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1)) +}; + +static int ulcmp_results[] = +{ + ulcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1)) +}; + +static int signof(int i) +{ + if (i < 0) + return -1; + + if (i == 0) + return 0; + + return 1; +} + +int main () { + unsigned char bytes[256]; + int i, j, k, n; + int *result; + + /* Table 2. Double-precision floating-point arithmetic. */ + deq (__aeabi_dadd (dzero, done), done); + deq (__aeabi_dadd (done, done), dtwo); + deq (__aeabi_ddiv (dminus_four, dminus_two), dtwo); + deq (__aeabi_ddiv (dminus_two, dtwo), dminus_one); + deq (__aeabi_dmul (dtwo, dtwo), dfour); + deq (__aeabi_dmul (dminus_one, dminus_two), dtwo); + deq (__aeabi_dneg (dminus_one), done); + deq (__aeabi_dneg (dfour), dminus_four); + deq (__aeabi_drsub (done, dzero), dminus_one); + deq (__aeabi_drsub (dtwo, dminus_two), dminus_four); + deq (__aeabi_dsub (dzero, done), dminus_one); + deq (__aeabi_dsub (dminus_two, dtwo), dminus_four); + + /* Table 3. Double-precision floating-point comparisons. */ + ieq (__aeabi_dcmpeq (done, done), 1); + ieq (__aeabi_dcmpeq (done, dzero), 0); + ieq (__aeabi_dcmpeq (dNaN, dzero), 0); + ieq (__aeabi_dcmpeq (dNaN, dNaN), 0); + + ieq (__aeabi_dcmplt (dzero, done), 1); + ieq (__aeabi_dcmplt (done, dzero), 0); + ieq (__aeabi_dcmplt (dzero, dzero), 0); + ieq (__aeabi_dcmplt (dzero, dNaN), 0); + ieq (__aeabi_dcmplt (dNaN, dNaN), 0); + + ieq (__aeabi_dcmple (dzero, done), 1); + ieq (__aeabi_dcmple (done, dzero), 0); + ieq (__aeabi_dcmple (dzero, dzero), 1); + ieq (__aeabi_dcmple (dzero, dNaN), 0); + ieq (__aeabi_dcmple (dNaN, dNaN), 0); + + ieq (__aeabi_dcmpge (dzero, done), 0); + ieq (__aeabi_dcmpge (done, dzero), 1); + ieq (__aeabi_dcmpge (dzero, dzero), 1); + ieq (__aeabi_dcmpge (dzero, dNaN), 0); + ieq (__aeabi_dcmpge (dNaN, dNaN), 0); + + ieq (__aeabi_dcmpgt (dzero, done), 0); + ieq (__aeabi_dcmpgt (done, dzero), 1); + ieq (__aeabi_dcmplt (dzero, dzero), 0); + ieq (__aeabi_dcmpgt (dzero, dNaN), 0); + ieq (__aeabi_dcmpgt (dNaN, dNaN), 0); + + ieq (__aeabi_dcmpun (done, done), 0); + ieq (__aeabi_dcmpun (done, dzero), 0); + ieq (__aeabi_dcmpun (dNaN, dzero), 1); + ieq (__aeabi_dcmpun (dNaN, dNaN), 1); + + /* Table 4. Single-precision floating-point arithmetic. */ + feq (__aeabi_fadd (fzero, fone), fone); + feq (__aeabi_fadd (fone, fone), ftwo); + feq (__aeabi_fdiv (fminus_four, fminus_two), ftwo); + feq (__aeabi_fdiv (fminus_two, ftwo), fminus_one); + feq (__aeabi_fmul (ftwo, ftwo), ffour); + feq (__aeabi_fmul (fminus_one, fminus_two), ftwo); + feq (__aeabi_fneg (fminus_one), fone); + feq (__aeabi_fneg (ffour), fminus_four); + feq (__aeabi_frsub (fone, fzero), fminus_one); + feq (__aeabi_frsub (ftwo, fminus_two), fminus_four); + feq (__aeabi_fsub (fzero, fone), fminus_one); + feq (__aeabi_fsub (fminus_two, ftwo), fminus_four); + + /* Table 5. Single-precision floating-point comparisons. */ + ieq (__aeabi_fcmpeq (fone, fone), 1); + ieq (__aeabi_fcmpeq (fone, fzero), 0); + ieq (__aeabi_fcmpeq (fNaN, fzero), 0); + ieq (__aeabi_fcmpeq (fNaN, fNaN), 0); + + ieq (__aeabi_fcmplt (fzero, fone), 1); + ieq (__aeabi_fcmplt (fone, fzero), 0); + ieq (__aeabi_fcmplt (fzero, fzero), 0); + ieq (__aeabi_fcmplt (fzero, fNaN), 0); + ieq (__aeabi_fcmplt (fNaN, fNaN), 0); + + ieq (__aeabi_fcmple (fzero, fone), 1); + ieq (__aeabi_fcmple (fone, fzero), 0); + ieq (__aeabi_fcmple (fzero, fzero), 1); + ieq (__aeabi_fcmple (fzero, fNaN), 0); + ieq (__aeabi_fcmple (fNaN, fNaN), 0); + + ieq (__aeabi_fcmpge (fzero, fone), 0); + ieq (__aeabi_fcmpge (fone, fzero), 1); + ieq (__aeabi_fcmpge (fzero, fzero), 1); + ieq (__aeabi_fcmpge (fzero, fNaN), 0); + ieq (__aeabi_fcmpge (fNaN, fNaN), 0); + + ieq (__aeabi_fcmpgt (fzero, fone), 0); + ieq (__aeabi_fcmpgt (fone, fzero), 1); + ieq (__aeabi_fcmplt (fzero, fzero), 0); + ieq (__aeabi_fcmpgt (fzero, fNaN), 0); + ieq (__aeabi_fcmpgt (fNaN, fNaN), 0); + + ieq (__aeabi_fcmpun (fone, fone), 0); + ieq (__aeabi_fcmpun (fone, fzero), 0); + ieq (__aeabi_fcmpun (fNaN, fzero), 1); + ieq (__aeabi_fcmpun (fNaN, fNaN), 1); + + /* Table 6. Floating-point to integer conversions. */ + ieq (__aeabi_d2iz (dminus_one), -1); + ueq (__aeabi_d2uiz (done), 1); + leq (__aeabi_d2lz (dminus_two), -2LL); + uleq (__aeabi_d2ulz (dfour), 4LL); + ieq (__aeabi_f2iz (fminus_one), -1); + ueq (__aeabi_f2uiz (fone), 1); + leq (__aeabi_f2lz (fminus_two), -2LL); + uleq (__aeabi_f2ulz (ffour), 4LL); + + /* Table 7. Conversions between floating types. */ + feq (__aeabi_d2f (dtwo), ftwo); + deq (__aeabi_f2d (fminus_four), dminus_four); + + /* Table 8. Integer to floating-point conversions. */ + deq (__aeabi_i2d (-1), dminus_one); + deq (__aeabi_ui2d (2), dtwo); + deq (__aeabi_l2d (-1), dminus_one); + deq (__aeabi_ul2d (2ULL), dtwo); + feq (__aeabi_i2f (-1), fminus_one); + feq (__aeabi_ui2f (2), ftwo); + feq (__aeabi_l2f (-1), fminus_one); + feq (__aeabi_ul2f (2ULL), ftwo); + + /* Table 9. Long long functions. */ + leq (__aeabi_lmul (4LL, -1LL), -4LL); + leq (__aeabi_llsl (2LL, 1), 4LL); + leq (__aeabi_llsr (-1LL, 63), 1); + leq (__aeabi_lasr (-1LL, 63), -1); + + result = lcmp_results; + for (i = 0; i < NUM_CMP_VALUES; i++) + for (j = 0; j < NUM_CMP_VALUES; j++) + for (k = 0; k < NUM_CMP_VALUES; k++) + for (n = 0; n < NUM_CMP_VALUES; n++) + { + ieq (signof (__aeabi_lcmp + (((long long)cmp_val[i] << 32) | cmp_val[k], + ((long long)cmp_val[j] << 32) | cmp_val[n])), + *result); + result++; + } + result = ulcmp_results; + for (i = 0; i < NUM_CMP_VALUES; i++) + for (j = 0; j < NUM_CMP_VALUES; j++) + for (k = 0; k < NUM_CMP_VALUES; k++) + for (n = 0; n < NUM_CMP_VALUES; n++) + { + ieq (signof (__aeabi_ulcmp + (((long long)cmp_val[i] << 32) | cmp_val[k], + ((long long)cmp_val[j] << 32) | cmp_val[n])), + *result); + result++; + } + + ieq (__aeabi_idiv (-550, 11), -50); + ueq (__aeabi_uidiv (4000000000U, 1000000U), 4000U); + + for (i = 0; i < 256; i++) + bytes[i] = i; + +#ifdef __ARMEB__ + ieq (__aeabi_uread4 (bytes + 1), 0x01020304U); + leq (__aeabi_uread8 (bytes + 3), 0x030405060708090aLL); + ieq (__aeabi_uwrite4 (0x66778899U, bytes + 5), 0x66778899U); + leq (__aeabi_uwrite8 (0x2030405060708090LL, bytes + 15), + 0x2030405060708090LL); +#else + ieq (__aeabi_uread4 (bytes + 1), 0x04030201U); + leq (__aeabi_uread8 (bytes + 3), 0x0a09080706050403LL); + ieq (__aeabi_uwrite4 (0x99887766U, bytes + 5), 0x99887766U); + leq (__aeabi_uwrite8 (0x9080706050403020LL, bytes + 15), + 0x9080706050403020LL); +#endif + + for (i = 0; i < 4; i++) + ieq (bytes[5 + i], (6 + i) * 0x11); + + for (i = 0; i < 8; i++) + ieq (bytes[15 + i], (2 + i) * 0x10); + + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c new file mode 100644 index 000000000..f254dd811 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct X +{ + int c; +}; + +extern void bar(struct X *); + +void foo () +{ + struct X x; + bar (&x); + bar (&x); + bar (&x); +} + +/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c new file mode 100644 index 000000000..f97f1ebea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c @@ -0,0 +1,17 @@ +/* Register liveness information from epilgoue enables peephole optimization. */ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +volatile int g_k; +extern void bar(int, int, int, int); + +int foo(int a, int b, int c, int d) +{ + if (g_k & 4) c++; + bar (a, b, c, d); + return 0; +} + +/* { dg-final { scan-assembler-times "lsls.*#29" 1 } } */ +/* { dg-final { scan-assembler-not "tst" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c new file mode 100644 index 000000000..6bc3b07d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c @@ -0,0 +1,301 @@ +/* { dg-do run { target { fixed_point } } } */ +/* { dg-options "-std=gnu99" } */ + +/* Check basic arithmetic ops for ARM fixed-point/saturating operation support. + Not target-independent since we make various assumptions about precision and + magnitudes of various types. */ + +#include <stdlib.h> +#include <stdio.h> +#include <math.h> +#include <stdfix.h> + +#define TEST(TYPE, OP, NAME, SUFFIX) \ + TYPE NAME##SUFFIX (TYPE A, TYPE B) \ + { \ + return A OP B; \ + } + +#define VARIANTS(TYPE, OP, NAME) \ + TEST (short TYPE, OP, NAME, _short); \ + TEST (TYPE, OP, NAME, _regular); \ + TEST (long TYPE, OP, NAME, _long); \ + TEST (_Sat short TYPE, OP, NAME, _sat_short); \ + TEST (_Sat TYPE, OP, NAME, _sat_regular); \ + TEST (_Sat long TYPE, OP, NAME, _sat_long); \ + TEST (unsigned short TYPE, OP, NAME, _uns_short); \ + TEST (unsigned TYPE, OP, NAME, _uns_regular); \ + TEST (unsigned long TYPE, OP, NAME, _uns_long); \ + TEST (unsigned _Sat short TYPE, OP, NAME, _uns_sat_short); \ + TEST (unsigned _Sat TYPE, OP, NAME, _uns_sat_regular); \ + TEST (unsigned _Sat long TYPE, OP, NAME, _uns_sat_long) + +VARIANTS (_Fract, +, plus_fract); +VARIANTS (_Accum, +, plus_accum); +VARIANTS (_Fract, -, minus_fract); +VARIANTS (_Accum, -, minus_accum); +VARIANTS (_Fract, *, mult_fract); +VARIANTS (_Accum, *, mult_accum); +VARIANTS (_Accum, /, div_accum); + +/* Inputs for signed add, multiply fractional tests. */ +short _Fract sf_a = 0.9hr; +short _Fract sf_b = -0.8hr; +_Fract f_a = 0.9r; +_Fract f_b = -0.8r; +long _Fract lf_a = 0.9lr; +long _Fract lf_b = -0.8lr; + +/* Inputs for signed subtract fractional tests. */ +short _Fract sf_c = 0.7hr; +short _Fract sf_d = 0.9hr; +_Fract f_c = 0.7r; +_Fract f_d = 0.9r; +long _Fract lf_c = 0.7lr; +long _Fract lf_d = 0.9lr; + +/* Inputs for unsigned add, subtract, multiply fractional tests. */ +unsigned short _Fract usf_a = 0.4uhr; +unsigned short _Fract usf_b = 0.3uhr; +unsigned _Fract uf_a = 0.4ur; +unsigned _Fract uf_b = 0.3ur; +unsigned long _Fract ulf_a = 0.4ulr; +unsigned long _Fract ulf_b = 0.3ulr; + +/* Inputs for saturating signed add tests. */ +short _Sat _Fract sf_e = 0.8hr; +short _Sat _Fract sf_f = 0.8hr; +_Sat _Fract f_e = 0.8r; +_Sat _Fract f_f = 0.8r; +long _Sat _Fract lf_e = 0.8r; +long _Sat _Fract lf_f = 0.8r; + +short _Sat _Fract sf_g = -0.8hr; +short _Sat _Fract sf_h = -0.8hr; +_Sat _Fract f_g = -0.8r; +_Sat _Fract f_h = -0.8r; +long _Sat _Fract lf_g = -0.8r; +long _Sat _Fract lf_h = -0.8r; + +/* Inputs for saturating unsigned subtract tests. */ +unsigned short _Sat _Fract usf_c = 0.3uhr; +unsigned short _Sat _Fract usf_d = 0.4uhr; +unsigned _Sat _Fract uf_c = 0.3ur; +unsigned _Sat _Fract uf_d = 0.4ur; +unsigned long _Sat _Fract ulf_c = 0.3ulr; +unsigned long _Sat _Fract ulf_d = 0.4ulr; + +/* Inputs for signed accumulator tests. */ + +short _Accum sa_a = 1.25hk; +short _Accum sa_b = -1.5hk; +_Accum a_a = 100.25k; +_Accum a_b = -100.5k; +long _Accum la_a = 1000.25lk; +long _Accum la_b = -1000.5lk; + +/* Inputs for unsigned accumulator tests. */ + +unsigned short _Accum usa_a = 2.5uhk; +unsigned short _Accum usa_b = 1.75uhk; +unsigned _Accum ua_a = 255.5uk; +unsigned _Accum ua_b = 170.25uk; +unsigned long _Accum ula_a = 1550.5ulk; +unsigned long _Accum ula_b = 999.5ulk; + +/* Inputs for signed saturating accumulator tests. */ + +short _Sat _Accum sa_c = 240.0hk; +short _Sat _Accum sa_d = 250.0hk; +short _Sat _Accum sa_e = -240.0hk; +short _Sat _Accum sa_f = -250.0hk; +short _Sat _Accum sa_g = 0.5hk; + +_Sat _Accum a_c = 65000.0k; +_Sat _Accum a_d = 20000.0k; +_Sat _Accum a_e = -65000.0k; +_Sat _Accum a_f = -20000.0k; +_Sat _Accum a_g = 0.5k; + +long _Sat _Accum la_c = 3472883712.0lk; +long _Sat _Accum la_d = 3456106496.0lk; +long _Sat _Accum la_e = -3472883712.0lk; +long _Sat _Accum la_f = -3456106496.0lk; +long _Sat _Accum la_g = 0.5lk; + +/* Inputs for unsigned saturating accumulator tests. */ + +unsigned short _Sat _Accum usa_c = 250.0uhk; +unsigned short _Sat _Accum usa_d = 240.0uhk; +unsigned short _Sat _Accum usa_e = 0.5uhk; + +unsigned _Sat _Accum ua_c = 65000.0uk; +unsigned _Sat _Accum ua_d = 20000.0uk; +unsigned _Sat _Accum ua_e = 0.5uk; + +unsigned long _Sat _Accum ula_c = 3472883712.0ulk; +unsigned long _Sat _Accum ula_d = 3456106496.0ulk; +unsigned long _Sat _Accum ula_e = 0.5ulk; + +#define CHECK(FN, EXP) do { \ + if (fabs ((float) (FN) - (EXP)) > 0.05) \ + { \ + fprintf (stderr, "result for " #FN " (as float): %f\n", (double) (FN));\ + abort (); \ + } \ + } while (0) + +#define CHECK_EXACT(FN, EXP) do { \ + if ((FN) != (EXP)) \ + { \ + fprintf (stderr, "result for " #FN " (as float): %f, should be %f\n", \ + (double) (FN), (double) (EXP)); \ + abort (); \ + } \ + } while (0) + +int +main (int argc, char *argv[]) +{ + /* Fract/fract operations, non-saturating. */ + + CHECK (plus_fract_short (sf_a, sf_b), 0.1); + CHECK (plus_fract_regular (f_a, f_b), 0.1); + CHECK (plus_fract_long (lf_a, lf_b), 0.1); + + CHECK (plus_fract_uns_short (usf_a, usf_b), 0.7); + CHECK (plus_fract_uns_regular (uf_a, uf_b), 0.7); + CHECK (plus_fract_uns_long (ulf_a, ulf_b), 0.7); + + CHECK (minus_fract_short (sf_c, sf_d), -0.2); + CHECK (minus_fract_regular (f_c, f_d), -0.2); + CHECK (minus_fract_long (lf_c, lf_d), -0.2); + + CHECK (minus_fract_uns_short (usf_a, usf_b), 0.1); + CHECK (minus_fract_uns_regular (uf_a, uf_b), 0.1); + CHECK (minus_fract_uns_long (ulf_a, ulf_b), 0.1); + + CHECK (mult_fract_short (sf_a, sf_b), -0.72); + CHECK (mult_fract_regular (f_a, f_b), -0.72); + CHECK (mult_fract_long (lf_a, lf_b), -0.72); + + CHECK (mult_fract_uns_short (usf_a, usf_b), 0.12); + CHECK (mult_fract_uns_regular (uf_a, uf_b), 0.12); + CHECK (mult_fract_uns_long (ulf_a, ulf_b), 0.12); + + /* Fract/fract operations, saturating. */ + + CHECK (plus_fract_sat_short (sf_e, sf_f), 1.0); + CHECK (plus_fract_sat_regular (f_e, f_f), 1.0); + CHECK (plus_fract_sat_long (lf_e, lf_f), 1.0); + + CHECK (plus_fract_sat_short (sf_g, sf_h), -1.0); + CHECK (plus_fract_sat_regular (f_g, f_h), -1.0); + CHECK (plus_fract_sat_long (lf_g, lf_h), -1.0); + + CHECK (plus_fract_uns_sat_short (sf_e, sf_f), 1.0); + CHECK (plus_fract_uns_sat_regular (f_e, f_f), 1.0); + CHECK (plus_fract_uns_sat_long (lf_e, lf_f), 1.0); + + CHECK (plus_fract_sat_short (sf_a, sf_b), 0.1); + CHECK (plus_fract_sat_regular (f_a, f_b), 0.1); + CHECK (plus_fract_sat_long (lf_a, lf_b), 0.1); + + CHECK (plus_fract_uns_sat_short (usf_a, usf_b), 0.7); + CHECK (plus_fract_uns_sat_regular (uf_a, uf_b), 0.7); + CHECK (plus_fract_uns_sat_long (ulf_a, ulf_b), 0.7); + + CHECK (minus_fract_uns_sat_short (usf_c, usf_d), 0.0); + CHECK (minus_fract_uns_sat_regular (uf_c, uf_d), 0.0); + CHECK (minus_fract_uns_sat_short (ulf_c, ulf_d), 0.0); + + CHECK (minus_fract_sat_short (sf_c, sf_d), -0.2); + CHECK (minus_fract_sat_regular (f_c, f_d), -0.2); + CHECK (minus_fract_sat_long (lf_c, lf_d), -0.2); + + /* Accum/accum operations, non-saturating. */ + + CHECK (plus_accum_short (sa_a, sa_b), -0.25); + CHECK (plus_accum_regular (a_a, a_b), -0.25); + CHECK (plus_accum_long (la_a, la_b), -0.25); + + CHECK (minus_accum_short (sa_a, sa_b), 2.75); + CHECK (minus_accum_regular (a_a, a_b), 200.75); + CHECK (minus_accum_long (la_a, la_b), 2000.75); + + CHECK (mult_accum_short (sa_a, sa_b), -1.875); + CHECK (mult_accum_regular (a_a, a_b), -10075.125); + CHECK (mult_accum_long (la_a, la_b), -1000750.125); + + CHECK (div_accum_short (sa_a, sa_b), -1.25/1.5); + CHECK (div_accum_regular (a_a, a_b), -100.25/100.5); + CHECK (div_accum_long (la_a, la_b), -1000.25/1000.5); + + /* Unsigned accum/accum operations, non-saturating. */ + + CHECK (plus_accum_uns_short (usa_a, usa_b), 4.25); + CHECK (plus_accum_uns_regular (ua_a, ua_b), 425.75); + CHECK (plus_accum_uns_long (ula_a, ula_b), 2550.0); + + CHECK (minus_accum_uns_short (usa_a, usa_b), 0.75); + CHECK (minus_accum_uns_regular (ua_a, ua_b), 85.25); + CHECK (minus_accum_uns_long (ula_a, ula_b), 551.0); + + CHECK (mult_accum_uns_short (usa_a, usa_b), 4.375); + CHECK (mult_accum_uns_regular (ua_a, ua_b), 43498.875); + CHECK (mult_accum_uns_long (ula_a, ula_b), 1549724.75); + + CHECK (div_accum_uns_short (usa_a, usa_b), 2.5/1.75); + CHECK (div_accum_uns_regular (ua_a, ua_b), 255.5/170.25); + CHECK (div_accum_uns_long (ula_a, ula_b), 1550.5/999.5); + + /* Signed accum/accum operations, saturating. */ + + CHECK_EXACT (plus_accum_sat_short (sa_c, sa_d), SACCUM_MAX); + CHECK_EXACT (plus_accum_sat_short (sa_e, sa_f), SACCUM_MIN); + CHECK_EXACT (plus_accum_sat_regular (a_c, a_d), ACCUM_MAX); + CHECK_EXACT (plus_accum_sat_regular (a_e, a_f), ACCUM_MIN); + CHECK_EXACT (plus_accum_sat_long (la_c, la_d), LACCUM_MAX); + CHECK_EXACT (plus_accum_sat_long (la_e, la_f), LACCUM_MIN); + + CHECK_EXACT (minus_accum_sat_short (sa_e, sa_d), SACCUM_MIN); + CHECK_EXACT (minus_accum_sat_short (sa_c, sa_f), SACCUM_MAX); + CHECK_EXACT (minus_accum_sat_regular (a_e, a_d), ACCUM_MIN); + CHECK_EXACT (minus_accum_sat_regular (a_c, a_f), ACCUM_MAX); + CHECK_EXACT (minus_accum_sat_long (la_e, la_d), LACCUM_MIN); + CHECK_EXACT (minus_accum_sat_long (la_c, la_f), LACCUM_MAX); + + CHECK_EXACT (mult_accum_sat_short (sa_c, sa_d), SACCUM_MAX); + CHECK_EXACT (mult_accum_sat_short (sa_c, sa_e), SACCUM_MIN); + CHECK_EXACT (mult_accum_sat_regular (a_c, a_d), ACCUM_MAX); + CHECK_EXACT (mult_accum_sat_regular (a_c, a_e), ACCUM_MIN); + CHECK_EXACT (mult_accum_sat_long (la_c, la_d), LACCUM_MAX); + CHECK_EXACT (mult_accum_sat_long (la_c, la_e), LACCUM_MIN); + + CHECK_EXACT (div_accum_sat_short (sa_d, sa_g), SACCUM_MAX); + CHECK_EXACT (div_accum_sat_short (sa_e, sa_g), SACCUM_MIN); + CHECK_EXACT (div_accum_sat_regular (a_c, a_g), ACCUM_MAX); + CHECK_EXACT (div_accum_sat_regular (a_e, a_g), ACCUM_MIN); + CHECK_EXACT (div_accum_sat_long (la_d, la_g), LACCUM_MAX); + CHECK_EXACT (div_accum_sat_long (la_e, la_g), LACCUM_MIN); + + /* Unsigned accum/accum operations, saturating. */ + + CHECK_EXACT (plus_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX); + CHECK_EXACT (plus_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX); + CHECK_EXACT (plus_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX); + + CHECK_EXACT (minus_accum_uns_sat_short (usa_d, usa_c), 0uhk); + CHECK_EXACT (minus_accum_uns_sat_regular (ua_d, ua_c), 0uk); + CHECK_EXACT (minus_accum_uns_sat_long (ula_d, ula_c), 0ulk); + + CHECK_EXACT (mult_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX); + CHECK_EXACT (mult_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX); + CHECK_EXACT (mult_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX); + + CHECK_EXACT (div_accum_uns_sat_short (usa_c, usa_e), USACCUM_MAX); + CHECK_EXACT (div_accum_uns_sat_regular (ua_c, ua_e), UACCUM_MAX); + CHECK_EXACT (div_accum_uns_sat_long (ula_c, ula_e), ULACCUM_MAX); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c new file mode 100644 index 000000000..078b10374 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c @@ -0,0 +1,20 @@ +/* Check that vcvt is used for fixed and float data conversions. */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp3_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_vfp3 } */ + +float +fixed_to_float (int i) +{ + return ((float) i / (1 << 16)); +} + +int +float_to_fixed (float f) +{ + return ((int) (f * (1 << 16))); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ +/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c new file mode 100644 index 000000000..e1884545f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicts with multilib options" { ! arm_thumb2_ok } { "-march=*" } { "" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv4-sp-d16" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-O2 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mthumb -mfloat-abi=hard" } */ + +#include "fma.h" + +/* { dg-final { scan-assembler-not "vfma\.f64\td\[0-9\]" } } */ +/* { dg-final { scan-assembler-times "vfma\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-not "vfms\.f64\td\[0-9\]" } } */ +/* { dg-final { scan-assembler-times "vfms\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-not "vfnma\.f64\td\[0-9\]" } } */ +/* { dg-final { scan-assembler-times "vfnma\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-not "vfnms\.f64\td\[0-9\]" } } */ +/* { dg-final { scan-assembler-times "vfnms\.f32\ts\[0-9\]" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c new file mode 100644 index 000000000..704559a57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicts with multilib options" { ! arm_thumb2_ok } { "-mthumb" } { "" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a15" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=vfpv4" } } */ +/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-O2 -mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=hard" } */ + +#include "fma.h" + +/* { dg-final { scan-assembler-times "vfma\.f64\td\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfma\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfms\.f64\td\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfms\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfnma\.f64\td\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfnma\.f32\ts\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfnms\.f64\td\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfnms\.f32\ts\[0-9\]" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h new file mode 100644 index 000000000..0812c2d73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h @@ -0,0 +1,50 @@ +extern double fma (double, double, double); +extern float fmaf (float, float, float); + +float +vfma32 (float x, float y, float z) +{ + return fmaf (x, y, z); +} + +float +vfms32 (float x, float y, float z) +{ + return fmaf (-x, y, z); +} + +float +vfnms32 (float x, float y, float z) +{ + return fmaf (x, y, -z); +} + +float +vfnma32 (float x, float y, float z) +{ + return fmaf (-x, y, -z); +} + +double +vfma64 (double x, double y, double z) +{ + return fma (x, y, z); +} + +double +vfms64 (double x, double y, double z) +{ + return fma (-x, y, z); +} + +double +vfnms64 (double x, double y, double z) +{ + return fma (x, y, -z); +} + +double +vfnma64 (double x, double y, double z) +{ + return fma (-x, y, -z); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c new file mode 100644 index 000000000..868768028 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c @@ -0,0 +1,92 @@ +/* Test type-generic builtins with __fp16 arguments. + Except as otherwise noted, they should behave exactly + the same as those with float arguments. */ + +/* { dg-do run } */ +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */ + +#include <stdlib.h> +#include <math.h> + +volatile __fp16 h1, h2; +volatile float f1, f2; + +void +set1 (double x) +{ + h1 = x; + f1 = h1; +} + +void +set2 (double x, double y) +{ + h1 = x; + f1 = h1; + h2 = y; + f2 = h2; +} + +#define test1(p,x) \ + set1 (x); \ + hp = (p (h1) ? 1 : 0); \ + fp = (p (f1) ? 1 : 0); \ + if (hp ^ fp) abort () + +#define test2(p,x,y) \ + set2 (x,y); \ + hp = (p (h1, h2) ? 1 : 0); \ + fp = (p (f1, f2) ? 1 : 0); \ + if (hp ^ fp) abort () + +int +main (void) +{ + int hp, fp; + + test1 (__builtin_isfinite, 17.0); + test1 (__builtin_isfinite, INFINITY); + test1 (__builtin_isinf, -0.5); + test1 (__builtin_isinf, INFINITY); + test1 (__builtin_isnan, 493.0); + test1 (__builtin_isnan, NAN); + test1 (__builtin_isnormal, 3.14159); + + test2 (__builtin_isgreater, 5.0, 3.0); + test2 (__builtin_isgreater, 3.0, 5.0); + test2 (__builtin_isgreater, 73.5, 73.5); + test2 (__builtin_isgreater, 1.0, NAN); + + test2 (__builtin_isgreaterequal, 5.0, 3.0); + test2 (__builtin_isgreaterequal, 3.0, 5.0); + test2 (__builtin_isgreaterequal, 73.5, 73.5); + test2 (__builtin_isgreaterequal, 1.0, NAN); + + test2 (__builtin_isless, 5.0, 3.0); + test2 (__builtin_isless, 3.0, 5.0); + test2 (__builtin_isless, 73.5, 73.5); + test2 (__builtin_isless, 1.0, NAN); + + test2 (__builtin_islessequal, 5.0, 3.0); + test2 (__builtin_islessequal, 3.0, 5.0); + test2 (__builtin_islessequal, 73.5, 73.5); + test2 (__builtin_islessequal, 1.0, NAN); + + test2 (__builtin_islessgreater, 5.0, 3.0); + test2 (__builtin_islessgreater, 3.0, 5.0); + test2 (__builtin_islessgreater, 73.5, 73.5); + test2 (__builtin_islessgreater, 1.0, NAN); + + test2 (__builtin_isunordered, 5.0, 3.0); + test2 (__builtin_isunordered, 3.0, 5.0); + test2 (__builtin_isunordered, 73.5, 73.5); + test2 (__builtin_isunordered, 1.0, NAN); + + /* Test that __builtin_isnormal recognizes a denormalized __fp16 value, + even if it's representable as a normalized float. */ + h1 = 5.96046E-8; + if (__builtin_isnormal (h1)) + abort (); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c new file mode 100644 index 000000000..3abcd947a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +__fp16 xx = 0.0; + +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */ +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.space\t2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c new file mode 100644 index 000000000..2e3d31fdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */ + +#include <math.h> + +/* NaNs are not representable in the alternative format; we should get a + diagnostic. */ +__fp16 xx = NAN; /* { dg-warning "overflow" } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c new file mode 100644 index 000000000..62a7a3df5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */ + +#include <math.h> + +/* Infinities are not representable in the alternative format; + we should get a diagnostic, and the value set to the largest + representable value. */ +/* 0x7fff = 32767 */ +__fp16 xx = INFINITY; /* { dg-warning "overflow" } */ + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t32767" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c new file mode 100644 index 000000000..09586e9b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +float xx __attribute__((mode(HF))) = 0.0; + +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */ +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.space\t2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c new file mode 100644 index 000000000..b7fe99d53 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x3c00 = 15360 */ +__fp16 xx = 1.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t15360" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c new file mode 100644 index 000000000..f325a84fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0xc000 = 49152 */ +__fp16 xx = -2.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t49152" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c new file mode 100644 index 000000000..4b9b33117 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x7bff = 31743 */ +__fp16 xx = 65504.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t31743" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c new file mode 100644 index 000000000..458f5073b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x3555 = 13653 */ +__fp16 xx = (1.0/3.0); + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t13653" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c new file mode 100644 index 000000000..dbb4a9999 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* This number is the maximum value representable in the alternative + encoding. */ +/* 0x7fff = 32767 */ +__fp16 xx = 131008.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t32767" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c new file mode 100644 index 000000000..40940a634 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative -pedantic" } */ + +/* This number overflows the range of the alternative encoding. Since this + encoding doesn't have infinities, we should get a pedantic warning, + and the value should be set to the largest representable value. */ +/* 0x7fff = 32767 */ +__fp16 xx = 123456789.0; /* { dg-warning "overflow" } */ + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t32767" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c new file mode 100644 index 000000000..cbc0a3947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This is the minimum normalized value. */ +/* 0x0400 = 1024 */ +__fp16 xx = 6.10352E-5; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t1024" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c new file mode 100644 index 000000000..6487c8d67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=alternative" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This is the minimum denormalized value. */ +/* 0x0001 = 1 */ +__fp16 xx = 5.96046E-8; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t1" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c new file mode 100644 index 000000000..1d8953b48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c @@ -0,0 +1,29 @@ +/* Test that expressions involving __fp16 values have the right types. */ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* This produces a diagnostic if EXPR doesn't have type TYPE. */ +#define CHECK(expr,type) \ + do { \ + type v; \ + __typeof (expr) *p = &v; \ + } while (0); + +volatile __fp16 f1; +volatile __fp16 f2; + +int +main (void) +{ + CHECK (f1, __fp16); + CHECK (+f1, float); + CHECK (-f1, float); + CHECK (f1+f2, float); + CHECK ((__fp16)(f1+f2), __fp16); + CHECK ((__fp16)99.99, __fp16); + CHECK ((f1+f2, f1), __fp16); +} + + + + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c new file mode 100644 index 000000000..d5d0ba2e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +__fp16 xx = 0.0; + +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */ +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.space\t2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c new file mode 100644 index 000000000..51604374e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */ + +#include <math.h> + +/* 0x7e00 = 32256 */ +__fp16 xx = NAN; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t32256" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c new file mode 100644 index 000000000..afab518b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */ + +#include <math.h> + +/* 0x7c00 = 31744 */ +__fp16 xx = INFINITY; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t31744" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c new file mode 100644 index 000000000..244c96ffd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +float xx __attribute__((mode(HF))) = 0.0; + +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */ +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.space\t2" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c new file mode 100644 index 000000000..35f2031c7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x3c00 = 15360 */ +__fp16 xx = 1.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t15360" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c new file mode 100644 index 000000000..90edd0119 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0xc000 = 49152 */ +__fp16 xx = -2.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t49152" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c new file mode 100644 index 000000000..20676d89d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x7bff = 31743 */ +__fp16 xx = 65504.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t31743" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c new file mode 100644 index 000000000..aff9e1356 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* 0x3555 = 13653 */ +__fp16 xx = (1.0/3.0); + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t13653" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c new file mode 100644 index 000000000..c736e63a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This number is too big and is represented as infinity. */ +/* 0x7c00 = 31744 */ +__fp16 xx = 131008.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t31744" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c new file mode 100644 index 000000000..93163772b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee -pedantic" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This number is too big and is represented as infinity. */ +/* We should *not* get an overflow warning here. */ +/* 0x7c00 = 31744 */ +__fp16 xx = 123456789.0; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t31744" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c new file mode 100644 index 000000000..a9646739f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This is the minimum normalized value. */ +/* 0x0400 = 1024 */ +__fp16 xx = 6.10352E-5; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t1024" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c new file mode 100644 index 000000000..11b31ce40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */ +/* This is the minimum denormalized value. */ +/* 0x0001 = 1 */ +__fp16 xx = 5.96046E-8; + +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */ +/* { dg-final { scan-assembler "\t.short\t1" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c new file mode 100644 index 000000000..e91250581 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=none" } */ + +/* __fp16 type name is not recognized unless you explicitly enable it + by selecting -mfp16-format=ieee or -mfp16-format=alternative. */ +__fp16 xx = 0.0; /* { dg-error "unknown type name" } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c new file mode 100644 index 000000000..eb7eef5ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=none" } */ + +/* mode(HF) attributes are not recognized unless you explicitly enable + half-precision floating point by selecting -mfp16-format=ieee or + -mfp16-format=alternative. */ +float xx __attribute__((mode(HF))) = 0.0; /* { dg-error "HF" } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c new file mode 100644 index 000000000..e40e1a3f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_fp16_ok } */ +/* { dg-options "-mfp16-format=ieee" } */ +/* { dg-add-options arm_fp16 } */ + +/* Test generation of VFP __fp16 instructions. */ + +__fp16 h1 = 0.0; +__fp16 h2 = 1234.0; +float f1 = 2.0; +float f2 = -999.9; + +void f (void) +{ + h1 = f1; + f2 = h2; +} + +/* { dg-final { scan-assembler "\tvcvtb.f32.f16" } } */ +/* { dg-final { scan-assembler "\tvcvtb.f16.f32" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c new file mode 100644 index 000000000..af4845f9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Functions cannot have parameters of type __fp16. */ +extern void f (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */ +extern void (*pf) (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */ + +/* These should be OK. */ +extern void g (__fp16 *); +extern void (*pg) (__fp16 *); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c new file mode 100644 index 000000000..f76394126 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +/* Functions cannot return type __fp16. */ +extern __fp16 f (void); /* { dg-error "cannot return __fp16" } */ +extern __fp16 (*pf) (void); /* { dg-error "cannot return __fp16" } */ + +/* These should be OK. */ +extern __fp16 *g (void); +extern __fp16 *(*pg) (void); diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c new file mode 100644 index 000000000..f50b4475f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c @@ -0,0 +1,47 @@ +/* Test intermediate rounding of double to float and then to __fp16, using + an example of a number that would round differently if it went directly + from double to __fp16. */ + +/* { dg-do run } */ +/* { dg-options "-mfp16-format=alternative" } */ + +#include <stdlib.h> + +/* The original double value. */ +#define ORIG 0x1.0020008p0 + +/* The expected (double)((__fp16)((float)ORIG)) value. */ +#define ROUNDED 0x1.0000000p0 + +typedef union u { + __fp16 f; + unsigned short h; +} ufh; + +ufh s = { ORIG }; +ufh r = { ROUNDED }; + +double d = ORIG; + +int +main (void) +{ + ufh x; + + /* Test that the rounding is correct for static initializers. */ + if (s.h != r.h) + abort (); + + /* Test that the rounding is correct for a casted constant expression + not in a static initializer. */ + x.f = (__fp16)ORIG; + if (x.h != r.h) + abort (); + + /* Test that the rounding is correct for a runtime conversion. */ + x.f = (__fp16)d; + if (x.h != r.h) + abort (); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c new file mode 100644 index 000000000..866d4d824 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c @@ -0,0 +1,47 @@ +/* Test intermediate rounding of double to float and then to __fp16, using + an example of a number that would round differently if it went directly + from double to __fp16. */ + +/* { dg-do run } */ +/* { dg-options "-mfp16-format=ieee" } */ + +#include <stdlib.h> + +/* The original double value. */ +#define ORIG 0x1.0020008p0 + +/* The expected (double)((__fp16)((float)ORIG)) value. */ +#define ROUNDED 0x1.0000000p0 + +typedef union u { + __fp16 f; + unsigned short h; +} ufh; + +ufh s = { ORIG }; +ufh r = { ROUNDED }; + +double d = ORIG; + +int +main (void) +{ + ufh x; + + /* Test that the rounding is correct for static initializers. */ + if (s.h != r.h) + abort (); + + /* Test that the rounding is correct for a casted constant expression + not in a static initializer. */ + x.f = (__fp16)ORIG; + if (x.h != r.h) + abort (); + + /* Test that the rounding is correct for a runtime conversion. */ + x.f = (__fp16)d; + if (x.h != r.h) + abort (); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c new file mode 100644 index 000000000..70c295648 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c @@ -0,0 +1,21 @@ +/* Test promotion of __fp16 to double as arguments to unprototyped + function in another compilation unit. */ + +/* { dg-do run } */ +/* { dg-options "-mfp16-format=ieee" } */ +/* { dg-additional-sources "fp16-unprototyped-2.c" } */ + +#include <stdlib.h> + +extern int f (); + +static __fp16 x = 42.0; +static __fp16 y = -42.0; + +int +main (void) +{ + if (!f (x, y)) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c new file mode 100644 index 000000000..0c0f9cda6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp16-format=ieee" } */ + +extern int f (); + +int +f (double xx, double yy) +{ + if (xx == 42.0 && yy == -42.0) + return 1; + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c new file mode 100644 index 000000000..52b438638 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c @@ -0,0 +1,37 @@ +/* Test promotion of __fp16 to double as arguments to variadic function. */ + +/* { dg-do run } */ +/* { dg-options "-mfp16-format=ieee" } */ + +#include <stdlib.h> +#include <stdarg.h> + +extern int f (int n, ...); + +int +f (int n, ...) +{ + if (n == 2) + { + double xx, yy; + va_list ap; + va_start (ap, n); + xx = va_arg (ap, double); + yy = va_arg (ap, double); + va_end (ap); + if (xx == 42.0 && yy == -42.0) + return 1; + } + return 0; +} + +static __fp16 x = 42.0; +static __fp16 y = -42.0; + +int +main (void) +{ + if (!f (2, x, y)) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c new file mode 100644 index 000000000..bb1888e38 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c @@ -0,0 +1,42 @@ +/* Check local register variables using a register conventionally + used as the frame pointer aren't clobbered under high register pressure. */ +/* { dg-do run } */ +/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ + +#include <stdlib.h> + +int global=5; + +void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4) +{ + if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4) + abort(); +} + +int __attribute__((noinline)) test(int a, int b, int c, int d) +{ + register unsigned long r __asm__("r7") = 0xdeadbeef; + int e; + + /* ABCD are live after the call which should be enough + to cause r7 to be used if it weren't for the register variable. */ + foo(a,b,c,d); + + e = 0; + __asm__ __volatile__ ("mov %0, %2" + : "=r" (e) + : "0" (e), "r" (r)); + + global = a+b+c+d; + + return e; +} + +int main() +{ + if (test(1, 2, 3, 4) != 0xdeadbeef) + abort(); + if (global != 10) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c new file mode 100644 index 000000000..4b48ef803 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v4 } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 4 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#include "ftest-support.h" + + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c new file mode 100644 index 000000000..016506f46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v4t } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 4 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c new file mode 100644 index 000000000..9ef944e5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v4t } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 4 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c new file mode 100644 index 000000000..a9403e97c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v5t } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 5 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c new file mode 100644 index 000000000..f3ad07ec0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v5t } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 5 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c new file mode 100644 index 000000000..f98c01a0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v5te } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 5 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c new file mode 100644 index 000000000..5d71787e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v5te } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 5 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c new file mode 100644 index 000000000..88a508954 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v6 } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 4 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c new file mode 100644 index 000000000..0f42a0ca8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v6 } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c new file mode 100644 index 000000000..8de021a0f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v6k } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c new file mode 100644 index 000000000..8e4a18804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v6k } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c new file mode 100644 index 000000000..ee075e290 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6-m" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v6m } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'M' + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c new file mode 100644 index 000000000..83b4bc4c9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v6t2 } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 4 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c new file mode 100644 index 000000000..1a1cbc5ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v6t2 } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c new file mode 100644 index 000000000..e2df0d482 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v6z } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 4 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c new file mode 100644 index 000000000..9761f0a96 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v6z } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 6 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 1 + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c new file mode 100644 index 000000000..c71a7cdb7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v7a } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c new file mode 100644 index 000000000..f1f789e8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v7a } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c new file mode 100644 index 000000000..688d766e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7e-m" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v7em } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'M' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 7 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c new file mode 100644 index 000000000..363b48b75 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=arm7-m" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v7m } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'M' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 7 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c new file mode 100644 index 000000000..08c017fc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v7r } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'R' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c new file mode 100644 index 000000000..1b69dc0f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v7r } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'R' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c new file mode 100644 index 000000000..3cf987ccc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v7ve } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c new file mode 100644 index 000000000..0d6b43221 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v7ve } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 7 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c new file mode 100644 index 000000000..7812c5cd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 8 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c new file mode 100644 index 000000000..605b1735e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v8a } */ + +#define NEED_ARM_ARCH +#define VALUE_ARM_ARCH 8 + +#define NEED_ARM_ARCH_ISA_ARM +#define VALUE_ARM_ARCH_ISA_ARM 1 + +#define NEED_ARM_ARCH_ISA_THUMB +#define VALUE_ARM_ARCH_ISA_THUMB 2 + +#define NEED_ARM_ARCH_PROFILE +#define VALUE_ARM_ARCH_PROFILE 'A' + +#define NEED_ARM_FEATURE_UNALIGNED +#define VALUE_ARM_FEATURE_UNALIGNED 1 + +#define NEED_ARM_FEATURE_LDREX +#define VALUE_ARM_FEATURE_LDREX 15 + +#define NEED_ARM_FEATURE_CLZ +#define VALUE_ARM_FEATURE_CLZ 1 + +#define NEED_ARM_FEATURE_DSP +#define VALUE_ARM_FEATURE_DSP 1 + +#define NEED_ARM_FEATURE_SIMD32 +#define VALUE_ARM_FEATURE_SIMD32 1 + +#define NEED_ARM_FEATURE_QBIT +#define VALUE_ARM_FEATURE_QBIT 1 + +#define NEED_ARM_FEATURE_SAT +#define VALUE_ARM_FEATURE_SAT 1 + +#include "ftest-support.h" diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h new file mode 100644 index 000000000..c56d2d588 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h @@ -0,0 +1,156 @@ +/* For each of several ARM architecture features, check that relevant + macros are defined or not, and that they have the expected values. */ + +#ifdef NEED_ARM_ARCH +# ifdef __ARM_ARCH +# if __ARM_ARCH != VALUE_ARM_ARCH +# error __ARM_ARCH has unexpected value +# endif +# else +# error __ARM_ARCH is not defined but should be +# endif +#else +# ifdef __ARM_ARCH +# error __ARM_ARCH is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_ARCH_ISA_ARM +# ifdef __ARM_ARCH_ISA_ARM +# if __ARM_ARCH_ISA_ARM != VALUE_ARM_ARCH_ISA_ARM +# error __ARM_ARCH_ISA_ARM has unexpected value +# endif +# else +# error __ARM_ARCH_ISA_ARM is not defined but should be +# endif +#else +# ifdef __ARM_ARCH_ISA_ARM +# error __ARM_ARCH_ISA_ARM is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_ARCH_ISA_THUMB +# ifdef __ARM_ARCH_ISA_THUMB +# if __ARM_ARCH_ISA_THUMB != VALUE_ARM_ARCH_ISA_THUMB +# error __ARM_ARCH_ISA_THUMB has unexpected value +# endif +# else +# error __ARM_ARCH_ISA_THUMB is not defined but should be +# endif +#else +# ifdef __ARM_ARCH_ISA_THUMB +# error __ARM_ARCH_ISA_THUMB is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_ARCH_PROFILE +# ifdef __ARM_ARCH_PROFILE +# if __ARM_ARCH_PROFILE != VALUE_ARM_ARCH_PROFILE +# error __ARM_ARCH_PROFILE has unexpected value +# endif +# else +# error __ARM_ARCH_PROFILE is not defined but should be +# endif +#else +# ifdef __ARM_ARCH_PROFILE +# error __ARM_ARCH_PROFILE is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_UNALIGNED +# ifdef __ARM_FEATURE_UNALIGNED +# if __ARM_FEATURE_UNALIGNED != VALUE_ARM_FEATURE_UNALIGNED +# error __ARM_FEATURE_UNALIGNED has unexpected value +# endif +# else +# error __ARM_FEATURE_UNALIGNED is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_UNALIGNED +# error __ARM_FEATURE_UNALIGNED is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_LDREX +# ifdef __ARM_FEATURE_LDREX +# if __ARM_FEATURE_LDREX != VALUE_ARM_FEATURE_LDREX +# error __ARM_FEATURE_LDREX has unexpected value +# endif +# else +# error __ARM_FEATURE_LDREX is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_LDREX +# error __ARM_FEATURE_LDREX is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_CLZ +# ifdef __ARM_FEATURE_CLZ +# if __ARM_FEATURE_CLZ != VALUE_ARM_FEATURE_CLZ +# error __ARM_FEATURE_CLZ has unexpected value +# endif +# else +# error __ARM_FEATURE_CLZ is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_CLZ +# error __ARM_FEATURE_CLZ is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_DSP +# ifdef __ARM_FEATURE_DSP +# if __ARM_FEATURE_DSP != VALUE_ARM_FEATURE_DSP +# error __ARM_FEATURE_DSP has unexpected value +# endif +# else +# error __ARM_FEATURE_DSP is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_DSP +# error __ARM_FEATURE_DSP is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_SIMD32 +# ifdef __ARM_FEATURE_SIMD32 +# if __ARM_FEATURE_SIMD32 != VALUE_ARM_FEATURE_SIMD32 +# error __ARM_FEATURE_SIMD32 has unexpected value +# endif +# else +# error __ARM_FEATURE_SIMD32 is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_SIMD32 +# error __ARM_FEATURE_SIMD32 is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_QBIT +# ifdef __ARM_FEATURE_QBIT +# if __ARM_FEATURE_QBIT != VALUE_ARM_FEATURE_QBIT +# error __ARM_FEATURE_QBIT has unexpected value +# endif +# else +# error __ARM_FEATURE_QBIT is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_QBIT +# error __ARM_FEATURE_QBIT is defined but should not be +# endif +#endif + +#ifdef NEED_ARM_FEATURE_SAT +# ifdef __ARM_FEATURE_SAT +# if __ARM_FEATURE_SAT != VALUE_ARM_FEATURE_SAT +# error __ARM_FEATURE_SAT has unexpected value +# endif +# else +# error __ARM_FEATURE_SAT is not defined but should be +# endif +#else +# ifdef __ARM_FEATURE_SAT +# error __ARM_FEATURE_SAT is defined but should not be +# endif +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c new file mode 100644 index 000000000..85ba1906a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c @@ -0,0 +1,22 @@ +/* Verify that hardware multiply is preferred on XScale. */ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xscale -O2" } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ +/* { dg-require-effective-target arm32 } */ + +/* Brett Gaines' test case. */ +unsigned BCPL(unsigned) __attribute__ ((naked)); +unsigned BCPL(unsigned seed) +{ + /* Best code would be: + ldr r1, =2147001325 + ldr r2, =715136305 + mla r0, r1, r0, r2 + mov pc, lr */ + + return seed * 2147001325U + 715136305U; +} + +/* { dg-final { scan-assembler "mla\[ ].*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c new file mode 100644 index 000000000..6c5187b20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c @@ -0,0 +1,42 @@ +/* Test epilogue of a realigned interrupt handler. */ +/* { dg-do run } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-require-effective-target arm_cortex_m } */ +/* { dg-require-effective-target arm_eabi } */ + +extern __attribute__((noreturn)) void abort(void); +extern int snprintf(char *, int, const char *, ...); + +#define BUFF_LEN 256 +char buff[BUFF_LEN]; + +char *get_buffer(void) +{ + return buff; +} + +void __attribute__((interrupt)) foo(void) +{ + char *msg = get_buffer(); + snprintf(msg, BUFF_LEN, "%d %p", 1, buff+BUFF_LEN); +} + +volatile void * save_sp; +int main() +{ + register volatile void * sp asm("sp"); + /* Check stack pointer before/after calling the interrupt + * handler. Not equal means that handler doesn't restore + * stack correctly. */ + save_sp = sp; + foo(); + /* Abort here instead of return non-zero. Due to wrong sp, lr value, + * returning from main may not work. */ + if (save_sp != sp) + { + sp = save_sp; + abort(); + } + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c new file mode 100644 index 000000000..218c6a21e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "#120" 1 } } */ + +extern void foo1 (int); +extern void foo2 (int); + +void t (int x, int y) +{ + if (y < 5) + foo1 (120); + else + foo2 (120); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c new file mode 100644 index 000000000..17d8e9365 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "120\n" 1 } } */ + +extern void foo1 (int); +extern void foo2 (int); +extern void foo3 (int); +extern void foo4 (int); +extern void foo5 (int); +extern void foo6 (int); + +void t (int x, int y) +{ + switch (y) + { + case 1: + foo1 (120); + break; + case 5: + foo2 (120); + break; + case 7: + foo3 (120); + break; + case 10: + foo4 (120); + break; + case 13: + foo5 (120); + break; + default: + foo6 (120); + break; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c new file mode 100644 index 000000000..a38424228 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c @@ -0,0 +1,17 @@ +/* Verify that prologue and epilogue are correct for functions with + __attribute__ ((interrupt)). */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_nothumb } */ +/* { dg-options "-O0 -marm" } */ + +/* This test is not valid when -mthumb. */ +extern void bar (int); +extern void foo (void) __attribute__ ((interrupt("IRQ"))); + +void foo () +{ + bar (0); +} + +/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, lr}" } } */ +/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, pc}\\^" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c new file mode 100644 index 000000000..61d313053 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c @@ -0,0 +1,19 @@ +/* Verify that prologue and epilogue are correct for functions with + __attribute__ ((interrupt)). */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_nothumb } */ +/* { dg-options "-O1 -marm" } */ + +/* This test is not valid when -mthumb. */ +extern void bar (int); +extern void test (void) __attribute__((__interrupt__)); + +int foo; +void test() +{ + bar (foo); + foo = 0; +} + +/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, lr}" } } */ +/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, pc}\\^" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c new file mode 100644 index 000000000..b3f465b74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +unsigned long long or64 (unsigned long long input) +{ + return input | 0x200000004ULL; +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c new file mode 100644 index 000000000..5425f1e92 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +int test (int a, int b) +{ + int r; + if (a > 10) + { + r = a - b; + r += 10; + } + else + { + r = b - a; + r -= 7; + } + if (r > 0) + r -= 3; + return r; +} +/* { dg-final { scan-assembler-times "\tit" 2 { target arm_thumb2 } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c new file mode 100644 index 000000000..2cf637230 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern void foo2 (short*); + +void +tr4 (short array[], int n) +{ + int x; + if (n > 0) + for (x = 0; x < n; x++) + foo2 (&array[x]); +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ +/* { dg-final { object-size text <= 26 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c new file mode 100644 index 000000000..11d9aac80 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo2 (short*) __attribute__((pure)); + +unsigned int +tr3 (short array[], unsigned int n) +{ + int sum = 0; + unsigned int x; + for (x = 0; x < n; ++x) + sum += foo2 (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c new file mode 100644 index 000000000..0c476b874 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo (int*) __attribute__((pure)); + +unsigned int +tr2 (int array[], int n) +{ + unsigned int sum = 0; + int x; + if (n > 0) + for (x = 0; x < n; x++) + sum += foo (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 36 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c new file mode 100644 index 000000000..0f9023808 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +extern unsigned int foo (int*) __attribute__((pure)); + +unsigned int +tr1 (int array[], unsigned int n) +{ + int sum = 0; + unsigned int x; + for (x = 0; x < n; ++x) + sum += foo (&array[x]); + return sum; +} + +/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */ +/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */ +/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c new file mode 100644 index 000000000..f466ff35f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-ivopts-details" } */ +/* { dg-skip-if "" { arm_thumb1 } } */ + +extern char *__ctype_ptr__; + +unsigned char * foo(unsigned char *ReadPtr) +{ + + unsigned char c; + + while (!(((__ctype_ptr__+sizeof(""[*ReadPtr]))[(int)(*ReadPtr)])&04) == (!(0))) + ReadPtr++; + + return ReadPtr; +} + +/* { dg-final { scan-tree-dump-times "original biv" 2 "ivopts"} } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c new file mode 100644 index 000000000..8183d1d5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */ + +void +tr5 (short array[], int n) +{ + int x; + if (n > 0) + for (x = 0; x < n; x++) + array[x] = 0; +} + +/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ +/* { dg-final { object-size text <= 20 { target arm_thumb2 } } } */ +/* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ +/* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ +/* { dg-final { cleanup-tree-dump "ivopts" } } */ +/* { dg-final { cleanup-saved-temps "ivopts" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c new file mode 100644 index 000000000..a128a0a0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct +{ + int x; + int i, j; +} off_struct; + +int foo (char *str, int *a, int b, int c) +{ + off_struct *p = (off_struct *)(str + 3); + b = p->i; + c = p->j; + *a = b + c; + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c new file mode 100644 index 000000000..f10f10606 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c @@ -0,0 +1,134 @@ +/* Check that long calls to different sections are not optimized to "bl". */ +/* { dg-do compile { target { arm32 && nonpic } } } */ +/* { dg-options "-O2" } */ +/* This test expects that short calls are the default. */ +/* { dg-skip-if "-mlong-calls in use" { "*-*-*" } { "-mlong-calls" } { "" } } */ + +#define section(S) __attribute__((section(S))) +#define weak __attribute__((weak)) +#define noinline __attribute__((noinline)) +#define long_call __attribute__((long_call)) +#define short_call __attribute__((short_call)) + +#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS ID (void); \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } + +#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + static const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS) \ + TEST (ID##1, TARGET_ATTRS, ) \ + TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b")) \ + TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c")) + +#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call) \ + DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call) + +DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,) +DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,) +DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak) +DO_TESTS_CALL_ATTR (static_, STATIC_CALL,) + + +/* Calls to remote_* should honor the call type attribute, + with "short" being the default. + + In the regular expressions below: + + * We allow both "b" and "bl" in some cases to allow for the + possibility of sibling calls. As of this writing, GCC does not + use sibling calls in Thumb-2 mode. */ + +/* { dg-final { scan-assembler "\tbl\tremote_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_n3\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */ + + +/* Calls to strong_*2 calls should honor the call type attribute, + with "short" being the default. Calls to other strong_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */ + + +/* Calls to weak_* should honor the call type attribute, + with "short" being the default. */ + +/* { dg-final { scan-assembler "\tbl\tweak_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_n3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n3\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */ + + +/* Calls to static_*2 calls should honor the call type attribute, + with "short" being the default. Calls to other static_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c new file mode 100644 index 000000000..8ce2404c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c @@ -0,0 +1,127 @@ +/* Check that long calls to different sections are not optimized to "bl". */ +/* { dg-do compile { target { arm32 && nonpic } } } */ +/* { dg-options "-O2 -mlong-calls" } */ + +#define section(S) __attribute__((section(S))) +#define weak __attribute__((weak)) +#define noinline __attribute__((noinline)) +#define long_call __attribute__((long_call)) +#define short_call __attribute__((short_call)) + +#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS ID (void); \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } + +#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + static const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS) \ + TEST (ID##1, TARGET_ATTRS, ) \ + TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b")) \ + TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c")) + +#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call) \ + DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call) + +DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,) +DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,) +DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak) +DO_TESTS_CALL_ATTR (static_, STATIC_CALL,) + + +/* Calls to remote_* should honor the call type attribute, + with "long" being the default. + + In the regular expressions below: + + * We allow both "b" and "bl" in some cases to allow for the + possibility of sibling calls. As of this writing, GCC does not + use sibling calls in Thumb-2 mode. */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_n1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_n2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_n3\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */ + + +/* Calls to strong_*2 calls should honor the call type attribute, + with "long" being the default. Calls to other strong_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tstrong_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */ + + +/* Calls to weak_* should honor the call type attribute, + with "long" being the default. */ + +/* { dg-final { scan-assembler-not "\tbl?\tweak_n1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_n2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_n3\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */ + + +/* Calls to static_*2 calls should honor the call type attribute, + with "long" being the default. Calls to other static_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c new file mode 100644 index 000000000..bd1891c00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c @@ -0,0 +1,126 @@ +/* Check that long calls to different sections are not optimized to "bl". */ +/* { dg-do compile { target { arm32 && fpic } } } */ +/* { dg-options "-O2 -fpic" } */ + +#define section(S) __attribute__((section(S))) +#define weak __attribute__((weak)) +#define noinline __attribute__((noinline)) +#define long_call __attribute__((long_call)) +#define short_call __attribute__((short_call)) + +#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS ID (void); \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } + +#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + static const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS) \ + TEST (ID##1, TARGET_ATTRS, ) \ + TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b")) \ + TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c")) + +#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call) \ + DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call) + +DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,) +DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,) +DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak) +DO_TESTS_CALL_ATTR (static_, STATIC_CALL,) + + +/* Calls to remote_*, strong_* and weak_* should honor the call type + attribute, with "short" being the default. + + In the regular expressions below: + + * The PLT marker is optional, even though we are using -fpic, + because it is not used (or required) on some targets. + + * We allow both "b" and "bl" in some cases to allow for the + possibility of sibling calls. As of this writing, GCC does not + use sibling calls in Thumb-2 mode. */ + +/* { dg-final { scan-assembler "\tbl\tremote_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */ + + +/* { dg-final { scan-assembler "\tbl\tstrong_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_n3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl\tstrong_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tstrong_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */ + + +/* { dg-final { scan-assembler "\tbl\tweak_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_n3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */ + + +/* Calls to static_*2 calls should honor the call type attribute, + with "short" being the default. Calls to other static_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c new file mode 100644 index 000000000..dc184b8f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c @@ -0,0 +1,119 @@ +/* Check that long calls to different sections are not optimized to "bl". */ +/* { dg-do compile { target { arm32 && fpic } } } */ +/* { dg-options "-O2 -fpic -mlong-calls" } */ + +#define section(S) __attribute__((section(S))) +#define weak __attribute__((weak)) +#define noinline __attribute__((noinline)) +#define long_call __attribute__((long_call)) +#define short_call __attribute__((short_call)) + +#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS ID (void); \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } + +#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS) \ + static const char *TARGET_ATTRS noinline ID (void) { return #ID; } \ + const char *CALL_ATTRS call_##ID (void) { return ID () + 1; } \ + const char *CALL_ATTRS sibcall_##ID (void) { return ID (); } + +#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS) \ + TEST (ID##1, TARGET_ATTRS, ) \ + TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b")) \ + TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c")) + +#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS) \ + DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call) \ + DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call) + +DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,) +DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,) +DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak) +DO_TESTS_CALL_ATTR (static_, STATIC_CALL,) + + +/* Calls to remote_*, strong_* and weak_* should honor the call type + attribute, with "long" being the default. + + In the regular expressions below: + + * The PLT marker is optional, even though we are using -fpic, + because it is not used (or required) on some targets. + + * We allow both "b" and "bl" in some cases to allow for the + possibility of sibling calls. As of this writing, GCC does not + use sibling calls in Thumb-2 mode. */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */ + + +/* { dg-final { scan-assembler-not "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstrong_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */ + + +/* { dg-final { scan-assembler-not "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */ + + +/* Calls to static_*2 calls should honor the call type attribute, + with "long" being the default. Calls to other static_* functions + should be short. */ + +/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */ + +/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */ +/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c new file mode 100644 index 000000000..766748e55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-add-options arm_neon } */ +/* { dg-options "-O3" } */ + +int id; +int +test (const long int *data) +{ + int i, retval; + retval = id; + for (i = 0; i < id; i++) + { + retval &= (data[i] <= 0); + } + + return (retval); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c new file mode 100644 index 000000000..cb405908e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c @@ -0,0 +1,201 @@ +/* { dg-do compile { target arm_thumb2 } } */ +/* { dg-options "-O2 -fdump-rtl-subreg2" } */ + +/* { dg-final { scan-rtl-dump "REG_INC" "subreg2" { target { ! arm_neon } } } } */ +/* { dg-final { cleanup-rtl-dump "subreg2" } } */ +struct device; +typedef unsigned int __u32; +typedef unsigned long long u64; +typedef __u32 __le32; +typedef u64 dma_addr_t; +typedef unsigned gfp_t; +int dev_warn (const struct device *dev, const char *fmt, ...); +struct usb_bus +{ + struct device *controller; +}; +struct usb_hcd +{ + struct usb_bus self; +}; +struct xhci_generic_trb +{ + __le32 field[4]; +}; +union xhci_trb +{ + struct xhci_generic_trb generic; +}; +struct xhci_segment +{ + union xhci_trb *trbs; + dma_addr_t dma; +}; +struct xhci_ring +{ + struct xhci_segment *first_seg; +}; +struct xhci_hcd +{ + struct xhci_ring *cmd_ring; + struct xhci_ring *event_ring; +}; +struct usb_hcd *xhci_to_hcd (struct xhci_hcd *xhci) +{ +} +dma_addr_t xhci_trb_virt_to_dma (struct xhci_segment * seg, + union xhci_trb * trb); +struct xhci_segment *trb_in_td (struct xhci_segment *start_seg, + dma_addr_t suspect_dma); +xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg, + union xhci_trb *start_trb, union xhci_trb *end_trb, + dma_addr_t input_dma, struct xhci_segment *result_seg, + char *test_name, int test_number) +{ + unsigned long long start_dma; + unsigned long long end_dma; + struct xhci_segment *seg; + start_dma = xhci_trb_virt_to_dma (input_seg, start_trb); + end_dma = xhci_trb_virt_to_dma (input_seg, end_trb); + { + dev_warn (xhci_to_hcd (xhci)->self.controller, + "%d\n", test_number); + dev_warn (xhci_to_hcd (xhci)->self.controller, + "Expected seg %p, got seg %p\n", result_seg, seg); + } +} +xhci_check_trb_in_td_math (struct xhci_hcd *xhci, gfp_t mem_flags) +{ + struct + { + dma_addr_t input_dma; + struct xhci_segment *result_seg; + } + simple_test_vector[] = + { + { + 0, ((void *) 0) + } + , + { + xhci->event_ring->first_seg->dma - 16, ((void *) 0)} + , + { + xhci->event_ring->first_seg->dma - 1, ((void *) 0)} + , + { + xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg} + , + { + xhci->event_ring->first_seg->dma + (64 - 1) * 16, + xhci->event_ring->first_seg + } + , + { + xhci->event_ring->first_seg->dma + (64 - 1) * 16 + 1, ((void *) 0)} + , + { + xhci->event_ring->first_seg->dma + (64) * 16, ((void *) 0)} + , + { + (dma_addr_t) (~0), ((void *) 0) + } + }; + struct + { + struct xhci_segment *input_seg; + union xhci_trb *start_trb; + union xhci_trb *end_trb; + dma_addr_t input_dma; + struct xhci_segment *result_seg; + } + complex_test_vector[] = + { + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + xhci->event_ring->first_seg->trbs,.end_trb = + &xhci->event_ring->first_seg->trbs[64 - 1],.input_dma = + xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + xhci->event_ring->first_seg->trbs,.end_trb = + &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma = + xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + xhci->cmd_ring->first_seg->trbs,.end_trb = + &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma = + xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + &xhci->event_ring->first_seg->trbs[0],.end_trb = + &xhci->event_ring->first_seg->trbs[3],.input_dma = + xhci->event_ring->first_seg->dma + 4 * 16,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + &xhci->event_ring->first_seg->trbs[3],.end_trb = + &xhci->event_ring->first_seg->trbs[6],.input_dma = + xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = + &xhci->event_ring->first_seg->trbs[1],.input_dma = + xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = + &xhci->event_ring->first_seg->trbs[1],.input_dma = + xhci->event_ring->first_seg->dma + (64 - 4) * 16,.result_seg = + ((void *) 0), + } + , + { + .input_seg = xhci->event_ring->first_seg,.start_trb = + &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = + &xhci->event_ring->first_seg->trbs[1],.input_dma = + xhci->cmd_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), + } + }; + unsigned int num_tests; + int i, ret; + num_tests = + (sizeof (simple_test_vector) / sizeof ((simple_test_vector)[0]) + + (sizeof (struct + { + } + ))); + for (i = 0; i < num_tests; i++) + { + ret = + xhci_test_trb_in_td (xhci, xhci->event_ring->first_seg, + xhci->event_ring->first_seg->trbs, + &xhci->event_ring->first_seg->trbs[64 - 1], + simple_test_vector[i].input_dma, + simple_test_vector[i].result_seg, "Simple", i); + if (ret < 0) + return ret; + } + for (i = 0; i < num_tests; i++) + { + ret = + xhci_test_trb_in_td (xhci, complex_test_vector[i].input_seg, + complex_test_vector[i].start_trb, + complex_test_vector[i].end_trb, + complex_test_vector[i].input_dma, + complex_test_vector[i].result_seg, "Complex", i); + if (ret < 0) + return ret; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c new file mode 100644 index 000000000..906342a87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_cond_exec } */ +/* { dg-options "-O2" } */ + +#define MAX(a, b) (a > b ? a : b) +int +foo (int a, int b, int c) +{ + return c - MAX (a, b); +} + +/* { dg-final { scan-assembler-not "mov" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c new file mode 100644 index 000000000..42101ef37 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { arm_thumb1 } { "*" } { "" } } */ +/* { dg-options "-O2" } */ + + +int +foo (int *p, int *q) +{ + int i; + int accum = 0; + + for (i = 0 ; i < 1024; i++) + { + accum += ((*p--) * (*q++)); + accum += 4096; + accum >>= 13 ; + } + + return accum; +} + +/* { dg-final { scan-assembler "mla\\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c new file mode 100644 index 000000000..1e3ca200b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long foolong (long long x, short *a, short *b) +{ + return x + *a * *b; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c new file mode 100644 index 000000000..d13c98284 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c @@ -0,0 +1,25 @@ +/* Verify that if IP is saved to ensure stack alignment, we don't load + it into sp. */ +/* { dg-do compile } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ +/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_iwmmxt_ok } */ +/* { dg-final { scan-assembler "ldmfd\[ ]sp!.*ip,\[ ]*pc" } } */ + +/* This function uses all the call-saved registers, namely r4, r5, r6, + r7, r8, r9, sl, fp. Since we also save lr, that leaves an odd + number of registers, and the compiler will push ip to align the + stack. Make sure that we restore ip into ip, not into sp as is + done when using a frame pointer. The -mno-apcs-frame option + permits the frame pointer to be used as an ordinary register. */ + +void +foo(void) +{ + __asm volatile ("" : : : + "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr"); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c new file mode 100644 index 000000000..0540f659d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c @@ -0,0 +1,166 @@ +/* { dg-do compile } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_iwmmxt_ok } */ +/* { dg-options "-mcpu=iwmmxt -flax-vector-conversions -std=gnu99" } */ + +/* Internal data types for implementing the intrinsics. */ +typedef int __v2si __attribute__ ((vector_size (8))); +typedef short __v4hi __attribute__ ((vector_size (8))); +typedef signed char __v8qi __attribute__ ((vector_size (8))); + +void +foo(void) +{ + volatile int isink; + volatile long long llsink; + volatile __v8qi v8sink; + volatile __v4hi v4sink; + volatile __v2si v2sink; + + isink = __builtin_arm_getwcgr0 (); + __builtin_arm_setwcgr0 (isink); + isink = __builtin_arm_getwcgr1 (); + __builtin_arm_setwcgr1 (isink); + isink = __builtin_arm_getwcgr2 (); + __builtin_arm_setwcgr2 (isink); + isink = __builtin_arm_getwcgr3 (); + __builtin_arm_setwcgr3 (isink); + + isink = __builtin_arm_textrmsb (v8sink, 0); + isink = __builtin_arm_textrmsh (v4sink, 0); + isink = __builtin_arm_textrmsw (v2sink, 0); + isink = __builtin_arm_textrmub (v8sink, 0); + isink = __builtin_arm_textrmuh (v4sink, 0); + isink = __builtin_arm_textrmuw (v2sink, 0); + v8sink = __builtin_arm_tinsrb (v8sink, isink, 0); + v4sink = __builtin_arm_tinsrh (v4sink, isink, 0); + v2sink = __builtin_arm_tinsrw (v2sink, isink, 0); + llsink = __builtin_arm_tmia (llsink, isink, isink); + llsink = __builtin_arm_tmiabb (llsink, isink, isink); + llsink = __builtin_arm_tmiabt (llsink, isink, isink); + llsink = __builtin_arm_tmiaph (llsink, isink, isink); + llsink = __builtin_arm_tmiatb (llsink, isink, isink); + llsink = __builtin_arm_tmiatt (llsink, isink, isink); + isink = __builtin_arm_tmovmskb (v8sink); + isink = __builtin_arm_tmovmskh (v4sink); + isink = __builtin_arm_tmovmskw (v2sink); + llsink = __builtin_arm_waccb (v8sink); + llsink = __builtin_arm_wacch (v4sink); + llsink = __builtin_arm_waccw (v2sink); + v8sink = __builtin_arm_waddb (v8sink, v8sink); + v8sink = __builtin_arm_waddbss (v8sink, v8sink); + v8sink = __builtin_arm_waddbus (v8sink, v8sink); + v4sink = __builtin_arm_waddh (v4sink, v4sink); + v4sink = __builtin_arm_waddhss (v4sink, v4sink); + v4sink = __builtin_arm_waddhus (v4sink, v4sink); + v2sink = __builtin_arm_waddw (v2sink, v2sink); + v2sink = __builtin_arm_waddwss (v2sink, v2sink); + v2sink = __builtin_arm_waddwus (v2sink, v2sink); + v8sink = __builtin_arm_walign (v8sink, v8sink, 0); /* waligni: 3-bit immediate. */ + v8sink = __builtin_arm_walign (v8sink, v8sink, isink); /* walignr: GP register. */ + llsink = __builtin_arm_wand(llsink, llsink); + llsink = __builtin_arm_wandn (llsink, llsink); + v8sink = __builtin_arm_wavg2b (v8sink, v8sink); + v8sink = __builtin_arm_wavg2br (v8sink, v8sink); + v4sink = __builtin_arm_wavg2h (v4sink, v4sink); + v4sink = __builtin_arm_wavg2hr (v4sink, v4sink); + v8sink = __builtin_arm_wcmpeqb (v8sink, v8sink); + v4sink = __builtin_arm_wcmpeqh (v4sink, v4sink); + v2sink = __builtin_arm_wcmpeqw (v2sink, v2sink); + v8sink = __builtin_arm_wcmpgtsb (v8sink, v8sink); + v4sink = __builtin_arm_wcmpgtsh (v4sink, v4sink); + v2sink = __builtin_arm_wcmpgtsw (v2sink, v2sink); + v8sink = __builtin_arm_wcmpgtub (v8sink, v8sink); + v4sink = __builtin_arm_wcmpgtuh (v4sink, v4sink); + v2sink = __builtin_arm_wcmpgtuw (v2sink, v2sink); + llsink = __builtin_arm_wmacs (llsink, v4sink, v4sink); + llsink = __builtin_arm_wmacsz (v4sink, v4sink); + llsink = __builtin_arm_wmacu (llsink, v4sink, v4sink); + llsink = __builtin_arm_wmacuz (v4sink, v4sink); + v4sink = __builtin_arm_wmadds (v4sink, v4sink); + v4sink = __builtin_arm_wmaddu (v4sink, v4sink); + v8sink = __builtin_arm_wmaxsb (v8sink, v8sink); + v4sink = __builtin_arm_wmaxsh (v4sink, v4sink); + v2sink = __builtin_arm_wmaxsw (v2sink, v2sink); + v8sink = __builtin_arm_wmaxub (v8sink, v8sink); + v4sink = __builtin_arm_wmaxuh (v4sink, v4sink); + v2sink = __builtin_arm_wmaxuw (v2sink, v2sink); + v8sink = __builtin_arm_wminsb (v8sink, v8sink); + v4sink = __builtin_arm_wminsh (v4sink, v4sink); + v2sink = __builtin_arm_wminsw (v2sink, v2sink); + v8sink = __builtin_arm_wminub (v8sink, v8sink); + v4sink = __builtin_arm_wminuh (v4sink, v4sink); + v2sink = __builtin_arm_wminuw (v2sink, v2sink); + v4sink = __builtin_arm_wmulsm (v4sink, v4sink); + v4sink = __builtin_arm_wmulul (v4sink, v4sink); + v4sink = __builtin_arm_wmulum (v4sink, v4sink); + llsink = __builtin_arm_wor (llsink, llsink); + v2sink = __builtin_arm_wpackdss (llsink, llsink); + v2sink = __builtin_arm_wpackdus (llsink, llsink); + v8sink = __builtin_arm_wpackhss (v4sink, v4sink); + v8sink = __builtin_arm_wpackhus (v4sink, v4sink); + v4sink = __builtin_arm_wpackwss (v2sink, v2sink); + v4sink = __builtin_arm_wpackwus (v2sink, v2sink); + llsink = __builtin_arm_wrord (llsink, llsink); + llsink = __builtin_arm_wrordi (llsink, isink); + v4sink = __builtin_arm_wrorh (v4sink, llsink); + v4sink = __builtin_arm_wrorhi (v4sink, isink); + v2sink = __builtin_arm_wrorw (v2sink, llsink); + v2sink = __builtin_arm_wrorwi (v2sink, isink); + v2sink = __builtin_arm_wsadb (v2sink, v8sink, v8sink); + v2sink = __builtin_arm_wsadbz (v8sink, v8sink); + v2sink = __builtin_arm_wsadh (v2sink, v4sink, v4sink); + v2sink = __builtin_arm_wsadhz (v4sink, v4sink); + v4sink = __builtin_arm_wshufh (v4sink, 0); + llsink = __builtin_arm_wslld (llsink, llsink); + llsink = __builtin_arm_wslldi (llsink, 0); + v4sink = __builtin_arm_wsllh (v4sink, llsink); + v4sink = __builtin_arm_wsllhi (v4sink, isink); + v2sink = __builtin_arm_wsllw (v2sink, llsink); + v2sink = __builtin_arm_wsllwi (v2sink, isink); + llsink = __builtin_arm_wsrad (llsink, llsink); + llsink = __builtin_arm_wsradi (llsink, isink); + v4sink = __builtin_arm_wsrah (v4sink, llsink); + v4sink = __builtin_arm_wsrahi (v4sink, isink); + v2sink = __builtin_arm_wsraw (v2sink, llsink); + v2sink = __builtin_arm_wsrawi (v2sink, isink); + llsink = __builtin_arm_wsrld (llsink, llsink); + llsink = __builtin_arm_wsrldi (llsink, isink); + v4sink = __builtin_arm_wsrlh (v4sink, llsink); + v4sink = __builtin_arm_wsrlhi (v4sink, isink); + v2sink = __builtin_arm_wsrlw (v2sink, llsink); + v2sink = __builtin_arm_wsrlwi (v2sink, isink); + v8sink = __builtin_arm_wsubb (v8sink, v8sink); + v8sink = __builtin_arm_wsubbss (v8sink, v8sink); + v8sink = __builtin_arm_wsubbus (v8sink, v8sink); + v4sink = __builtin_arm_wsubh (v4sink, v4sink); + v4sink = __builtin_arm_wsubhss (v4sink, v4sink); + v4sink = __builtin_arm_wsubhus (v4sink, v4sink); + v2sink = __builtin_arm_wsubw (v2sink, v2sink); + v2sink = __builtin_arm_wsubwss (v2sink, v2sink); + v2sink = __builtin_arm_wsubwus (v2sink, v2sink); + v4sink = __builtin_arm_wunpckehsb (v8sink); + v2sink = __builtin_arm_wunpckehsh (v4sink); + llsink = __builtin_arm_wunpckehsw (v2sink); + v4sink = __builtin_arm_wunpckehub (v8sink); + v2sink = __builtin_arm_wunpckehuh (v4sink); + llsink = __builtin_arm_wunpckehuw (v2sink); + v4sink = __builtin_arm_wunpckelsb (v8sink); + v2sink = __builtin_arm_wunpckelsh (v4sink); + llsink = __builtin_arm_wunpckelsw (v2sink); + v4sink = __builtin_arm_wunpckelub (v8sink); + v2sink = __builtin_arm_wunpckeluh (v4sink); + llsink = __builtin_arm_wunpckeluw (v2sink); + v8sink = __builtin_arm_wunpckihb (v8sink, v8sink); + v4sink = __builtin_arm_wunpckihh (v4sink, v4sink); + v2sink = __builtin_arm_wunpckihw (v2sink, v2sink); + v8sink = __builtin_arm_wunpckilb (v8sink, v8sink); + v4sink = __builtin_arm_wunpckilh (v4sink, v4sink); + v2sink = __builtin_arm_wunpckilw (v2sink, v2sink); + llsink = __builtin_arm_wxor (llsink, llsink); + llsink = __builtin_arm_wzero (); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c new file mode 100644 index 000000000..fefffae81 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ +/* Check that function arguments aren't assigned and copied to stack slots + in naked functions. This usually happens at -O0 (presumably for + better debugging), but is highly undesirable if we haven't created + a stack frame. */ +void __attribute__((naked)) +foo(int n) +{ + __asm__ volatile ("frob r0\n"); +} +/* { dg-final { scan-assembler "\tfrob r0" } } */ +/* { dg-final { scan-assembler-not "\tstr" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c new file mode 100644 index 000000000..92e7db444 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c @@ -0,0 +1,12 @@ +/* Verify that __attribute__((naked)) produces a naked function + that does not use bx to return. Naked functions could be used + to implement interrupt routines and must not return using bx. */ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ +/* Use more arguments than we have argument registers. */ +int __attribute__((naked)) foo(int a, int b, int c, int d, int e, int f) +{ + __asm__ volatile ("@ naked"); +} +/* { dg-final { scan-assembler "\t@ naked" } } */ +/* { dg-final { scan-assembler-not "\tbx\tlr" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c new file mode 100644 index 000000000..c9bef049c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2" } */ + +signed long long extendsidi_negsi (signed int x) +{ + return -x; +} + +/* +Expected output: + rsb r0, r0, #0 + mov r1, r0, asr #31 +*/ +/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */ +/* { dg-final { scan-assembler-times "asr" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c new file mode 100644 index 000000000..4444c20ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2" } */ + +signed long long zero_extendsidi_negsi (unsigned int x) +{ + return -x; +} +/* +Expected output: + rsb r0, r0, #0 + mov r1, #0 +*/ +/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "mov" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c new file mode 100644 index 000000000..76ddf49fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2" } */ + +signed long long negdi_zero_extendsidi (unsigned int x) +{ + return -((signed long long) x); +} +/* +Expected output: + rsbs r0, r0, #0 + sbc r1, r1, r1 +*/ +/* { dg-final { scan-assembler-times "rsb" 1 } } */ +/* { dg-final { scan-assembler-times "sbc" 1 } } */ +/* { dg-final { scan-assembler-times "mov" 0 } } */ +/* { dg-final { scan-assembler-times "rsc" 0 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c new file mode 100644 index 000000000..fe3d78b30 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -funsafe-math-optimizations" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +float32x2_t f_sub_abs_to_vabd_32(float32x2_t val1, float32x2_t val2) +{ + float32x2_t sres = vsub_f32(val1, val2); + float32x2_t res = vabs_f32 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.f32" } }*/ + +#include <arm_neon.h> +int8x8_t sub_abs_to_vabd_8(int8x8_t val1, int8x8_t val2) +{ + int8x8_t sres = vsub_s8(val1, val2); + int8x8_t res = vabs_s8 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s8" } }*/ + +int16x4_t sub_abs_to_vabd_16(int16x4_t val1, int16x4_t val2) +{ + int16x4_t sres = vsub_s16(val1, val2); + int16x4_t res = vabs_s16 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s16" } }*/ + +int32x2_t sub_abs_to_vabd_32(int32x2_t val1, int32x2_t val2) +{ + int32x2_t sres = vsub_s32(val1, val2); + int32x2_t res = vabs_s32 (sres); + + return res; +} +/* { dg-final { scan-assembler "vabd\.s32" } }*/ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c new file mode 100644 index 000000000..a67625014 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ +/* Check that the arm_final_prescan_insn ccfsm code does not try to + * conditionally execute NEON instructions. */ +#include <arm_neon.h> +#include <stdlib.h> + +int __attribute__((noinline)) +foo(uint32x2_t a, uint32_t *p, uint32_t *q) +{ + if (p != q) + /* This vst1 instruction could be conditional, except that NEON + instructions are never conditional in ARM mode. */ + vst1_u32(p, a); + return 0; +} + +int +main() +{ + uint32x2_t v; + uint32_t a[2] = {1, 42}; + v = vld1_u32(a); + v = vadd_u32(v, v); + foo(v, a, a); + if (a[0] != 1 || a[1] != 42) + abort(); + exit(0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c new file mode 100644 index 000000000..cfe83ce1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +void +f (unsigned int a) +{ + unsigned long long b = a; + asm volatile ("@ extended to %0" : : "w" (b)); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ +/* { dg-final { scan-assembler "vshr.u64" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c new file mode 100644 index 000000000..1c5a17e42 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +void +f (int a) +{ + long long b = a; + asm volatile ("@ extended to %0" : : "w" (b)); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ +/* { dg-final { scan-assembler "vshr.s64" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c new file mode 100644 index 000000000..a2a4103b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c @@ -0,0 +1,54 @@ +/* Check that Neon is *not* used by default to handle 64-bits scalar + operations. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +typedef long long i64; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef int i32; + +/* Unary operators */ +#define UNARY_OP(name, op) \ + void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + +/* Binary operators */ +#define BINARY_OP(name, op) \ + void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + +/* Unsigned shift */ +#define SHIFT_U(name, op, amount) \ + void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + +/* Signed shift */ +#define SHIFT_S(name, op, amount) \ + void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + +UNARY_OP(not, ~) + +BINARY_OP(add, +) +BINARY_OP(sub, -) +BINARY_OP(and, &) +BINARY_OP(or, |) +BINARY_OP(xor, ^) + +SHIFT_U(right1, >>, 1) +SHIFT_U(right2, >>, 2) +SHIFT_U(right5, >>, 5) +SHIFT_U(rightn, >>, c) + +SHIFT_S(right1, >>, 1) +SHIFT_S(right2, >>, 2) +SHIFT_S(right5, >>, 5) +SHIFT_S(rightn, >>, c) + +/* { dg-final {scan-assembler-times "vmvn" 0} } */ +/* { dg-final {scan-assembler-times "vadd" 0} } */ +/* { dg-final {scan-assembler-times "vsub" 0} } */ +/* { dg-final {scan-assembler-times "vand" 0} } */ +/* { dg-final {scan-assembler-times "vorr" 0} } */ +/* { dg-final {scan-assembler-times "veor" 0} } */ +/* { dg-final {scan-assembler-times "vshr" 0} } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c new file mode 100644 index 000000000..6ee13af01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void neon_internal_error(int *dst, int *src) +{ + uint16x8x4_t sval; + + sval = vld4q_u16((void *)src); + vst4q_u16((void *)dst,sval); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c new file mode 100644 index 000000000..40f1bba36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20) +#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1) +#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A) + +#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) + +void +bar (uint32_t *ptr, int y) +{ + uint32x2x3_t MANY (SETUP); + int *x = __builtin_alloca (y); + int z[0x1000]; + foo (x, z); + MANY (MODIFY); + foo (x, z); + MANY (STORE); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c new file mode 100644 index 000000000..f3e4f335e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O -g" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n) +{ + float32x4x4_t a5, a6, a7, a8, a9; + int i; + + a5 = *src; + a6 = *src; + a7 = *src; + a8 = *src; + a9 = *src; + while (n--) + { + for (i = 0; i < 8; i++) + { + float32x4x4_t a0, a1, a2, a3, a4; + + a0 = *src; + a1 = *src; + a2 = *src; + a3 = *src; + a4 = *src; + *src = a0; + *dest = a0.val[0]; + *dest = a0.val[3]; + *src = a1; + *dest = a1.val[0]; + *dest = a1.val[3]; + *src = a2; + *dest = a2.val[0]; + *dest = a2.val[3]; + *src = a3; + *dest = a3.val[0]; + *dest = a3.val[3]; + *src = a4; + *dest = a4.val[0]; + *dest = a4.val[3]; + } + *src = a5; + *dest = a5.val[0]; + *dest = a5.val[3]; + *src = a6; + *dest = a6.val[0]; + *dest = a6.val[3]; + *src = a7; + *dest = a7.val[0]; + *dest = a7.val[3]; + *src = a8; + *dest = a8.val[0]; + *dest = a8.val[3]; + *src = a9; + *dest = a9.val[0]; + *dest = a9.val[3]; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c new file mode 100644 index 000000000..cd92d7d33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-fno-omit-frame-pointer -mapcs-frame -O" } +/* { dg-add-options arm_neon } */ + +extern void abort (void); + +float data; + +void __attribute__((noinline, noclone)) bar (float f) +{ + data = f; +} + +float __attribute__((noinline, noclone)) foo (float f) +{ + int error_reported = 0; + + void __attribute__((noinline, noclone)) + nested (int a, int b, int c, int d, float f0, float f1, float f2, float f3) + { + float e; + + if (f3 > f2) + e = f3; + else + e = f2; + + if (f0 - f1 > e) + { + error_reported = a + b + c + d; + bar (f0); + bar (e); + } + } + + nested (1, 2, 3, 4, 1.0, 1.0, 3.5, 4.2); + return f + (float)error_reported; +} + +#define PI 3.1415927f + +int main (void) +{ + if (foo (PI) != PI) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c new file mode 100644 index 000000000..91dde6a20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void neon_internal_error(int32x4_t *dst, char *src) +{ + *dst = *(int32x4_t *)(src+1008); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c new file mode 100644 index 000000000..c63aa0496 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + + +void +_op_blend_p_caa_dp(unsigned *s, unsigned* e, unsigned *d, unsigned c) { + while (d < e) { + *d = ( (((((*s) >> 8) & 0x00ff00ff) * (c)) & 0xff00ff00) + (((((*s) & 0x00ff00ff) * (c)) >> 8) & 0x00ff00ff) ); + d++; + s++; + } +} + +/* These constants should be emitted as immediates rather than loaded from memory. */ + +/* { dg-final { scan-assembler-not "(\\.d?word|mov(w|t))" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c new file mode 100644 index 000000000..9cf86dd05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c @@ -0,0 +1,101 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb -march=armv7-a" } */ +/* { dg-add-options arm_neon } */ +/* { dg-prune-output "switch .* conflicts with" } */ + +#include <arm_neon.h> +#include <stddef.h> + +void * +memset (DST, C, LENGTH) + void *DST; + int C; + size_t LENGTH; +{ + void* DST0 = DST; + unsigned char C_BYTE = C; + + + if (__builtin_expect(LENGTH < 4, 1)) { + size_t i = 0; + while (i < LENGTH) { + ((char*)DST)[i] = C_BYTE; + i++; + } + return DST; + } + + const char* DST_end = (char*)DST + LENGTH; + + + while ((uintptr_t)DST % 4 != 0) { + *(char*) (DST++) = C_BYTE; + } + + + uint32_t C_SHORTWORD = (uint32_t)(unsigned char)(C_BYTE) * 0x01010101; + + + if (__builtin_expect(DST_end - (char*)DST >= 16, 0)) { + while ((uintptr_t)DST % 16 != 0) { + *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD; + DST += 4; + } + + + uint8x16_t C_WORD = vdupq_n_u8(C_BYTE); + + + + + + size_t i = 0; + LENGTH = DST_end - (char*)DST; + while (i + 16 * 16 <= LENGTH) { + *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 4))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 5))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 6))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 7))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 8))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 9))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 10))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 11))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 12))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 13))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 14))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 15))) = C_WORD; + i += 16 * 16; + } + while (i + 16 * 4 <= LENGTH) { + *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD; + *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD; + i += 16 * 4; + } + while (i + 16 <= LENGTH) { + *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD; + i += 16; + } + DST += i; + } + + while (4 <= DST_end - (char*)DST) { + *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD; + DST += 4; + } + + + while ((char*)DST < DST_end) { + *((char*)DST) = C_BYTE; + DST++; + } + + return DST0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c new file mode 100644 index 000000000..284a1d8ad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c @@ -0,0 +1,21 @@ +/* Test the `vadd_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL; + + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c new file mode 100644 index 000000000..05bda8b04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c @@ -0,0 +1,21 @@ +/* Test the `vadd_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL; + + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c new file mode 100644 index 000000000..8b6975db6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c @@ -0,0 +1,21 @@ +/* Test the `vand_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c new file mode 100644 index 000000000..a8ec3a28b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c @@ -0,0 +1,21 @@ +/* Test the `vand_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c new file mode 100644 index 000000000..ec3438bae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c @@ -0,0 +1,21 @@ +/* Test the `vbic_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); + + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c new file mode 100644 index 000000000..a0c1b85b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c @@ -0,0 +1,21 @@ +/* Test the `vbic_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); + + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c new file mode 100644 index 000000000..21a6a78a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" +#include <stdio.h> + +extern void abort (void); + +int +main (void) +{ + uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff, + ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 }; + int i, j; + + for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i) + { + for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j) + { + uint64_t a1 = args[i]; + uint64_t a2 = args[j]; + uint64_t res = vceq_p64 (vreinterpret_p64_u64 (a1), + vreinterpret_p64_u64 (a2)); + uint64_t exp = (a1 == a2) ? ~0x0 : 0x0; + + if (res != exp) + { + fprintf (stderr, "vceq_p64 (a1= %lx, a2= %lx)" + " returned %lx, expected %lx\n", + a1, a2, res, exp); + abort (); + } + } + } + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c new file mode 100644 index 000000000..8e9f37851 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define MAX(a, b) (a > b ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = MAX (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c new file mode 100644 index 000000000..c8306e364 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define LTGT(a, b) (__builtin_islessgreater (a, b) ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = LTGT (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler-times "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c new file mode 100644 index 000000000..3bb67d3af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define UNORD(a, b) (__builtin_isunordered (a, b) ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = UNORD (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c new file mode 100644 index 000000000..41799a25c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +float32x4_t out_float32x4_t; +void test_vdupq_nf32 (void) +{ + out_float32x4_t = vdupq_n_f32 (0.0); +} + +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c new file mode 100644 index 000000000..a06b0647a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x12000000); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c new file mode 100644 index 000000000..07d08896a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t out_uint16x8_t; +void test_vdupq_nu16 (void) +{ + out_uint16x8_t = vdupq_n_u16 (0x12); +} + +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c new file mode 100644 index 000000000..27b418682 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t out_uint16x8_t; +void test_vdupq_nu16 (void) +{ + out_uint16x8_t = vdupq_n_u16 (0x1200); +} + +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c new file mode 100644 index 000000000..4d38bc088 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t out_uint16x8_t; +void test_vdupq_nu16 (void) +{ + out_uint16x8_t = vdupq_n_u16 (~0x12); +} + +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c new file mode 100644 index 000000000..a16659fda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t out_uint16x8_t; +void test_vdupq_nu16 (void) +{ + out_uint16x8_t = vdupq_n_u16 (~0x1200); +} + +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c new file mode 100644 index 000000000..84a6fe04f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint8x16_t out_uint8x16_t; +void test_vdupq_nu8 (void) +{ + out_uint8x16_t = vdupq_n_u8 (0x12); +} + +/* { dg-final { scan-assembler "vmov\.i8\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c new file mode 100644 index 000000000..70bec0336 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x12ff); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c new file mode 100644 index 000000000..e0283f1fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x12ffff); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c new file mode 100644 index 000000000..7dcf85d39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x12ff); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c new file mode 100644 index 000000000..09804373f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x12ffff); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c new file mode 100644 index 000000000..f9e6a72ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +float32x4_t out_float32x4_t; +void test_vdupq_nf32 (void) +{ + out_float32x4_t = vdupq_n_f32 (0.125); +} + +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c new file mode 100644 index 000000000..d40731643 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x12); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c new file mode 100644 index 000000000..bc1be079f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x1200); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c new file mode 100644 index 000000000..9b04f16d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x120000); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c new file mode 100644 index 000000000..0889b80af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (0x12000000); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c new file mode 100644 index 000000000..f7b1dc861 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x12); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c new file mode 100644 index 000000000..9d494c355 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x1200); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c new file mode 100644 index 000000000..799e95ed9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c @@ -0,0 +1,17 @@ +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint32x4_t out_uint32x4_t; +void test_vdupq_nu32 (void) +{ + out_uint32x4_t = vdupq_n_u32 (~0x120000); +} + +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c new file mode 100644 index 000000000..da24eaca6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_lanes64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c new file mode 100644 index 000000000..cc19ea512 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_laneu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c new file mode 100644 index 000000000..79b4d4eb6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c new file mode 100644 index 000000000..ef6f47fd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c @@ -0,0 +1,22 @@ +/* Test the `vdupq_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c new file mode 100644 index 000000000..589ea2293 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x1_t = vdup_n_s64 (arg0_int64_t); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c new file mode 100644 index 000000000..8bed5a0c7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c new file mode 100644 index 000000000..59d5baa35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c @@ -0,0 +1,21 @@ +/* Test the `veor_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c new file mode 100644 index 000000000..b7ff77af0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c @@ -0,0 +1,21 @@ +/* Test the `veor_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c new file mode 100644 index 000000000..3d6c28cca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c @@ -0,0 +1,340 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm_little_endian } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +#include <stdlib.h> +#include <stdio.h> + +uint8x8_t +tst_vext_u8 (uint8x8_t __a, uint8x8_t __b) +{ + uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9}; + + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint8x8_t +tst_vext_u8_rotate (uint8x8_t __a) +{ + uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x4_t +tst_vext_u16 (uint16x4_t __a, uint16x4_t __b) +{ + uint16x4_t __mask1 = {2, 3, 4, 5}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint16x4_t +tst_vext_u16_rotate (uint16x4_t __a) +{ + uint16x4_t __mask1 = {2, 3, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint32x2_t +tst_vext_u32 (uint32x2_t __a, uint32x2_t __b) +{ + uint32x2_t __mask1 = {1, 2}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +/* This one is mapped into vrev64.32. */ +uint32x2_t +tst_vext_u32_rotate (uint32x2_t __a) +{ + uint32x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x16_t +tst_vextq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint8x16_t +tst_vextq_u8_rotate (uint8x16_t __a) +{ + uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 0, 1, 2, 3}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x8_t +tst_vextq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint16x8_t +tst_vextq_u16_rotate (uint16x8_t __a) +{ + uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint32x4_t +tst_vextq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + uint32x4_t __mask1 = {1, 2, 3, 4}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint32x4_t +tst_vextq_u32_rotate (uint32x4_t __a) +{ + uint32x4_t __mask1 = {1, 2, 3, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint64x2_t +tst_vextq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + uint64x2_t __mask1 = {1, 2}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint64x2_t +tst_vextq_u64_rotate (uint64x2_t __a) +{ + uint64x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +int main (void) +{ + uint8_t arr_u8x8[] = {0, 1, 2, 3, 4, 5, 6, 7}; + uint8_t arr2_u8x8[] = {8, 9, 10, 11, 12, 13, 14, 15}; + uint16_t arr_u16x4[] = {0, 1, 2, 3}; + uint16_t arr2_u16x4[] = {4, 5, 6, 7}; + uint32_t arr_u32x2[] = {0, 1}; + uint32_t arr2_u32x2[] = {2, 3}; + uint8_t arr_u8x16[] = {0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15}; + uint8_t arr2_u8x16[] = {16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31}; + uint16_t arr_u16x8[] = {0, 1, 2, 3, 4, 5, 6, 7}; + uint16_t arr2_u16x8[] = {8, 9, 10, 11, 12, 13, 14, 15}; + uint32_t arr_u32x4[] = {0, 1, 2, 3}; + uint32_t arr2_u32x4[] = {4, 5, 6, 7}; + uint64_t arr_u64x2[] = {0, 1}; + uint64_t arr2_u64x2[] = {2, 3}; + + uint8_t expected_u8x8[] = {2, 3, 4, 5, 6, 7, 8, 9}; + uint8_t expected_rot_u8x8[] = {2, 3, 4, 5, 6, 7, 0, 1}; + uint16_t expected_u16x4[] = {2, 3, 4, 5}; + uint16_t expected_rot_u16x4[] = {2, 3, 0, 1}; + uint32_t expected_u32x2[] = {1, 2}; + uint32_t expected_rot_u32x2[] = {1, 0}; + uint8_t expected_u8x16[] = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19}; + uint8_t expected_rot_u8x16[] = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 0, 1, 2, 3,}; + uint16_t expected_u16x8[] = {2, 3, 4, 5, 6, 7, 8, 9}; + uint16_t expected_rot_u16x8[] = {2, 3, 4, 5, 6, 7, 0, 1}; + uint32_t expected_u32x4[] = {1, 2, 3, 4}; + uint32_t expected_rot_u32x4[] = {1, 2, 3, 0}; + uint64_t expected_u64x2[] = {1, 2}; + uint64_t expected_rot_u64x2[] = {1, 0}; + + uint8x8_t vec_u8x8 = vld1_u8 (arr_u8x8); + uint8x8_t vec2_u8x8 = vld1_u8 (arr2_u8x8); + uint16x4_t vec_u16x4 = vld1_u16 (arr_u16x4); + uint16x4_t vec2_u16x4 = vld1_u16 (arr2_u16x4); + uint32x2_t vec_u32x2 = vld1_u32 (arr_u32x2); + uint32x2_t vec2_u32x2 = vld1_u32 (arr2_u32x2); + uint8x16_t vec_u8x16 = vld1q_u8 (arr_u8x16); + uint8x16_t vec2_u8x16 = vld1q_u8 (arr2_u8x16); + uint16x8_t vec_u16x8 = vld1q_u16 (arr_u16x8); + uint16x8_t vec2_u16x8 = vld1q_u16 (arr2_u16x8); + uint32x4_t vec_u32x4 = vld1q_u32 (arr_u32x4); + uint32x4_t vec2_u32x4 = vld1q_u32 (arr2_u32x4); + uint64x2_t vec_u64x2 = vld1q_u64 (arr_u64x2); + uint64x2_t vec2_u64x2 = vld1q_u64 (arr2_u64x2); + + uint8x8_t result_u8x8; + uint16x4_t result_u16x4; + uint32x2_t result_u32x2; + uint8x16_t result_u8x16; + uint16x8_t result_u16x8; + uint32x4_t result_u32x4; + uint64x2_t result_u64x2; + + union {uint8x8_t v; uint8_t buf[8];} mem_u8x8; + union {uint16x4_t v; uint16_t buf[4];} mem_u16x4; + union {uint32x2_t v; uint32_t buf[2];} mem_u32x2; + union {uint8x16_t v; uint8_t buf[16];} mem_u8x16; + union {uint16x8_t v; uint16_t buf[8];} mem_u16x8; + union {uint32x4_t v; uint32_t buf[4];} mem_u32x4; + union {uint64x2_t v; uint64_t buf[2];} mem_u64x2; + + int i; + + result_u8x8 = tst_vext_u8 (vec_u8x8, vec2_u8x8); + vst1_u8 (mem_u8x8.buf, result_u8x8); + + for (i=0; i<8; i++) + if (mem_u8x8.buf[i] != expected_u8x8[i]) + { + printf ("tst_vext_u8[%d]=%d expected %d\n", + i, mem_u8x8.buf[i], expected_u8x8[i]); + abort (); + } + + result_u8x8 = tst_vext_u8_rotate (vec_u8x8); + vst1_u8 (mem_u8x8.buf, result_u8x8); + + for (i=0; i<8; i++) + if (mem_u8x8.buf[i] != expected_rot_u8x8[i]) + { + printf ("tst_vext_u8_rotate[%d]=%d expected %d\n", + i, mem_u8x8.buf[i], expected_rot_u8x8[i]); + abort (); + } + + + result_u16x4 = tst_vext_u16 (vec_u16x4, vec2_u16x4); + vst1_u16 (mem_u16x4.buf, result_u16x4); + + for (i=0; i<4; i++) + if (mem_u16x4.buf[i] != expected_u16x4[i]) + { + printf ("tst_vext_u16[%d]=%d expected %d\n", + i, mem_u16x4.buf[i], expected_u16x4[i]); + abort (); + } + + result_u16x4 = tst_vext_u16_rotate (vec_u16x4); + vst1_u16 (mem_u16x4.buf, result_u16x4); + + for (i=0; i<4; i++) + if (mem_u16x4.buf[i] != expected_rot_u16x4[i]) + { + printf ("tst_vext_u16_rotate[%d]=%d expected %d\n", + i, mem_u16x4.buf[i], expected_rot_u16x4[i]); + abort (); + } + + + result_u32x2 = tst_vext_u32 (vec_u32x2, vec2_u32x2); + vst1_u32 (mem_u32x2.buf, result_u32x2); + + for (i=0; i<2; i++) + if (mem_u32x2.buf[i] != expected_u32x2[i]) + { + printf ("tst_vext_u32[%d]=%d expected %d\n", + i, mem_u32x2.buf[i], expected_u32x2[i]); + abort (); + } + + result_u32x2 = tst_vext_u32_rotate (vec_u32x2); + vst1_u32 (mem_u32x2.buf, result_u32x2); + + for (i=0; i<2; i++) + if (mem_u32x2.buf[i] != expected_rot_u32x2[i]) + { + printf ("tst_vext_u32_rotate[%d]=%d expected %d\n", + i, mem_u32x2.buf[i], expected_rot_u32x2[i]); + abort (); + } + + + result_u8x16 = tst_vextq_u8 (vec_u8x16, vec2_u8x16); + vst1q_u8 (mem_u8x16.buf, result_u8x16); + + for (i=0; i<16; i++) + if (mem_u8x16.buf[i] != expected_u8x16[i]) + { + printf ("tst_vextq_u8[%d]=%d expected %d\n", + i, mem_u8x16.buf[i], expected_u8x16[i]); + abort (); + } + + result_u8x16 = tst_vextq_u8_rotate (vec_u8x16); + vst1q_u8 (mem_u8x16.buf, result_u8x16); + + for (i=0; i<16; i++) + if (mem_u8x16.buf[i] != expected_rot_u8x16[i]) + { + printf ("tst_vextq_u8_rotate[%d]=%d expected %d\n", + i, mem_u8x16.buf[i], expected_rot_u8x16[i]); + abort (); + } + + result_u16x8 = tst_vextq_u16 (vec_u16x8, vec2_u16x8); + vst1q_u16 (mem_u16x8.buf, result_u16x8); + + for (i=0; i<8; i++) + if (mem_u16x8.buf[i] != expected_u16x8[i]) + { + printf ("tst_vextq_u16[%d]=%d expected %d\n", + i, mem_u16x8.buf[i], expected_u16x8[i]); + abort (); + } + + result_u16x8 = tst_vextq_u16_rotate (vec_u16x8); + vst1q_u16 (mem_u16x8.buf, result_u16x8); + + for (i=0; i<8; i++) + if (mem_u16x8.buf[i] != expected_rot_u16x8[i]) + { + printf ("tst_vextq_u16_rotate[%d]=%d expected %d\n", + i, mem_u16x8.buf[i], expected_rot_u16x8[i]); + abort (); + } + + result_u32x4 = tst_vextq_u32 (vec_u32x4, vec2_u32x4); + vst1q_u32 (mem_u32x4.buf, result_u32x4); + + for (i=0; i<4; i++) + if (mem_u32x4.buf[i] != expected_u32x4[i]) + { + printf ("tst_vextq_u32[%d]=%d expected %d\n", + i, mem_u32x4.buf[i], expected_u32x4[i]); + abort (); + } + + result_u32x4 = tst_vextq_u32_rotate (vec_u32x4); + vst1q_u32 (mem_u32x4.buf, result_u32x4); + + for (i=0; i<4; i++) + if (mem_u32x4.buf[i] != expected_rot_u32x4[i]) + { + printf ("tst_vextq_u32_rotate[%d]=%d expected %d\n", + i, mem_u32x4.buf[i], expected_rot_u32x4[i]); + abort (); + } + + result_u64x2 = tst_vextq_u64 (vec_u64x2, vec2_u64x2); + vst1q_u64 (mem_u64x2.buf, result_u64x2); + + for (i=0; i<2; i++) + if (mem_u64x2.buf[i] != expected_u64x2[i]) + { + printf ("tst_vextq_u64[%d]=%lld expected %lld\n", + i, mem_u64x2.buf[i], expected_u64x2[i]); + abort (); + } + + result_u64x2 = tst_vextq_u64_rotate (vec_u64x2); + vst1q_u64 (mem_u64x2.buf, result_u64x2); + + for (i=0; i<2; i++) + if (mem_u64x2.buf[i] != expected_rot_u64x2[i]) + { + printf ("tst_vextq_u64_rotate[%d]=%lld expected %lld\n", + i, mem_u64x2.buf[i], expected_rot_u64x2[i]); + abort (); + } + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c new file mode 100644 index 000000000..4a012a996 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c @@ -0,0 +1,115 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm_little_endian } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint8x8_t +tst_vext_u8 (uint8x8_t __a, uint8x8_t __b) +{ + uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9}; + + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint8x8_t +tst_vext_u8_rotate (uint8x8_t __a) +{ + uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x4_t +tst_vext_u16 (uint16x4_t __a, uint16x4_t __b) +{ + uint16x4_t __mask1 = {2, 3, 4, 5}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint16x4_t +tst_vext_u16_rotate (uint16x4_t __a) +{ + uint16x4_t __mask1 = {2, 3, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint32x2_t +tst_vext_u32 (uint32x2_t __a, uint32x2_t __b) +{ + uint32x2_t __mask1 = {1, 2}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +/* This one is mapped into vrev64.32. */ +uint32x2_t +tst_vext_u32_rotate (uint32x2_t __a) +{ + uint32x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x16_t +tst_vextq_u8 (uint8x16_t __a, uint8x16_t __b) +{ + uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint8x16_t +tst_vextq_u8_rotate (uint8x16_t __a) +{ + uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 0, 1, 2, 3}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x8_t +tst_vextq_u16 (uint16x8_t __a, uint16x8_t __b) +{ + uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint16x8_t +tst_vextq_u16_rotate (uint16x8_t __a) +{ + uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint32x4_t +tst_vextq_u32 (uint32x4_t __a, uint32x4_t __b) +{ + uint32x4_t __mask1 = {1, 2, 3, 4}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint32x4_t +tst_vextq_u32_rotate (uint32x4_t __a) +{ + uint32x4_t __mask1 = {1, 2, 3, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint64x2_t +tst_vextq_u64 (uint64x2_t __a, uint64x2_t __b) +{ + uint64x2_t __mask1 = {1, 2}; + return __builtin_shuffle ( __a, __b, __mask1) ; +} + +uint64x2_t +tst_vextq_u64_rotate (uint64x2_t __a) +{ + uint64x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +/* { dg-final {scan-assembler-times "vext\.8\\t" 4} } */ +/* { dg-final {scan-assembler-times "vext\.16\\t" 4} } */ +/* { dg-final {scan-assembler-times "vext\.32\\t" 3} } */ +/* { dg-final {scan-assembler-times "vrev64\.32\\t" 1} } */ +/* { dg-final {scan-assembler-times "vext\.64\\t" 2} } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c new file mode 100644 index 000000000..a003a8274 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-add-options arm_neonv2 } */ +/* { dg-final { scan-assembler "vfma\\.f32\[ \]+\[dDqQ]" } } */ + +/* Verify that VFMA is used. */ +void f1(int n, float a, float x[], float y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = a * x[i] + y[i]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c new file mode 100644 index 000000000..8cefd8a85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-add-options arm_neonv2 } */ +/* { dg-final { scan-assembler "vfms\\.f32\[ \]+\[dDqQ]" } } */ + +/* Verify that VFMS is used. */ +void f1(int n, float a, float x[], float y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = a * -x[i] + y[i]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c new file mode 100644 index 000000000..5891e6619 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vget_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64_t out_int64_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; + + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); + if (out_int64_t != (int64_t)arg0_int64x1_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c new file mode 100644 index 000000000..b0ce070d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vget_lane_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64_t out_uint64_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; + + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); + if (out_uint64_t != (uint64_t)arg0_uint64x1_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c new file mode 100644 index 000000000..f6bf6911d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint8x16_t +foo (uint8_t *a, uint8x16_t b) +{ + vst1q_lane_u8 (a, b, 14); + return vld1q_lane_u8 (a + 0x100, b, 15); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c new file mode 100644 index 000000000..cf8396643 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c @@ -0,0 +1,24 @@ +/* Test the `vld1q_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t input[2] = {(int64x1_t)0x0123456776543210LL, + (int64x1_t)0x89abcdeffedcba90LL}; + int64x1_t output[2] = {0, 0}; + int64x2_t var = vld1q_dup_s64((int64_t *)input); + + vst1q_s64((int64_t *)output, var); + if (output[0] != (int64x1_t)0x0123456776543210LL) + abort(); + if (output[1] != (int64x1_t)0x0123456776543210LL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c new file mode 100644 index 000000000..0cc5c8826 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint32_t buffer[12]; + +void __attribute__((noinline)) +foo (uint32_t *a) +{ + uint32x4x3_t x; + + x = vld3q_u32 (a); + x.val[0] = vaddq_u32 (x.val[0], x.val[1]); + vst3q_u32 (a, x); +} + +int +main (void) +{ + buffer[0] = 1; + buffer[1] = 2; + foo (buffer); + return buffer[0] != 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c new file mode 100644 index 000000000..e66637168 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, unsigned int x[], unsigned int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] >> 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c new file mode 100644 index 000000000..c60c014e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c @@ -0,0 +1,11 @@ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-add-options arm_neon } */ +/* { dg-final { scan-assembler "vmla\\.i32" } } */ + +/* Verify that VMLA is used. */ +void f1(int n, int a, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = a * x[i] + y[i]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c new file mode 100644 index 000000000..89ee82b0f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c @@ -0,0 +1,11 @@ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-add-options arm_neon } */ +/* { dg-final { scan-assembler "vmls\\.i32" } } */ + +/* Verify that VMLS is used. */ +void f1(int n, int a, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = y[i] - a * x[i]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c new file mode 100644 index 000000000..5a8abdce0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c @@ -0,0 +1,22 @@ +/* Test the `vmovq_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x2_t out_int64x2_t = {0, 0}; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) + abort(); + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c new file mode 100644 index 000000000..8012fc175 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c @@ -0,0 +1,23 @@ +/* Test the `vmovq_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x2_t out_uint64x2_t = {0, 0}; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) + abort(); + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) + abort(); + return 0; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c new file mode 100644 index 000000000..c125f4a24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; + + out_int64x1_t = vmov_n_s64 (arg0_int64_t); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c new file mode 100644 index 000000000..71ecaed13 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; + + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c new file mode 100644 index 000000000..6f2d20b6d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) +{ + int i; + for (i = 0; i < 9; i++) + c[i] = b[i] | (~a[i]); +} +void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) +{ + int i; + for (i = 0; i < 9; i++) + c[i] = b[i] & (~a[i]); +} + +/* { dg-final { scan-assembler "vorn\\t" } } */ +/* { dg-final { scan-assembler "vbic\\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c new file mode 100644 index 000000000..364dbd190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c @@ -0,0 +1,21 @@ +/* Test the `vorn_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); + + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c new file mode 100644 index 000000000..b35286846 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c @@ -0,0 +1,21 @@ +/* Test the `vorn_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); + + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c new file mode 100644 index 000000000..90ced9e9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c @@ -0,0 +1,21 @@ +/* Test the `vorr_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; + + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c new file mode 100644 index 000000000..5b44afb07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c @@ -0,0 +1,21 @@ +/* Test the `vorr_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; + + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c new file mode 100644 index 000000000..10f41bc32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c @@ -0,0 +1,105 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x4_t +tst_vrev642_u16 (uint16x4_t __a) +{ + uint16x4_t __rv; + uint16x4_t __mask1 = { 3, 2, 1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x8_t +tst_vrev64q2_u16 (uint16x8_t __a) +{ + uint16x8_t __rv; + uint16x8_t __mask1 = {3, 2, 1, 0, 7, 6, 5, 4 }; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x8_t +tst_vrev642_u8 (uint8x8_t __a) +{ + uint8x8_t __rv; + uint8x8_t __mask1 = { 7, 6, 5, 4, 3, 2, 1, 0}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint8x16_t +tst_vrev64q2_u8 (uint8x16_t __a) +{ + uint8x16_t __rv; + uint8x16_t __mask1 = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}; + return __builtin_shuffle ( __a, __mask1) ; + +} + +uint32x2_t +tst_vrev642_u32 (uint32x2_t __a) +{ + uint32x2_t __rv; + uint32x2_t __mask1 = {1, 0}; + return __builtin_shuffle ( __a, __mask1) ; + +} + +uint32x4_t +tst_vrev64q2_u32 (uint32x4_t __a) +{ + uint32x4_t __rv; + uint32x4_t __mask1 = {1, 0, 3, 2}; + return __builtin_shuffle ( __a, __mask1) ; +} + +uint16x4_t +tst_vrev322_u16 (uint16x4_t __a) +{ + uint16x4_t __mask1 = { 1, 0, 3, 2 }; + return __builtin_shuffle (__a, __mask1); +} + +uint16x8_t +tst_vrev32q2_u16 (uint16x8_t __a) +{ + uint16x8_t __mask1 = { 1, 0, 3, 2, 5, 4, 7, 6 }; + return __builtin_shuffle (__a, __mask1); +} + +uint8x8_t +tst_vrev322_u8 (uint8x8_t __a) +{ + uint8x8_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4}; + return __builtin_shuffle (__a, __mask1); +} + +uint8x16_t +tst_vrev32q2_u8 (uint8x16_t __a) +{ + uint8x16_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}; + return __builtin_shuffle (__a, __mask1); +} + +uint8x8_t +tst_vrev162_u8 (uint8x8_t __a) +{ + uint8x8_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6}; + return __builtin_shuffle (__a, __mask); +} + +uint8x16_t +tst_vrev16q2_u8 (uint8x16_t __a) +{ + uint8x16_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}; + return __builtin_shuffle (__a, __mask); +} + +/* { dg-final {scan-assembler-times "vrev32\.16\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev32\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev16\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.8\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.32\\t" 2} } */ +/* { dg-final {scan-assembler-times "vrev64\.16\\t" 2} } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c new file mode 100644 index 000000000..101139327 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c @@ -0,0 +1,21 @@ +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64_t arg0_int64_t = 0xf00f00f00LL; + int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; + + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + if ((int64_t)out_int64x1_t != arg0_int64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c new file mode 100644 index 000000000..51d38fd1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c @@ -0,0 +1,24 @@ +/* Test the `vset_lane_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> +#include <string.h> + +int8_t x_init[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; +int8_t y_init[8] = { 1, 2, 3, 16, 5, 6, 7, 8 }; + +int main (void) +{ + int8x8_t x = vld1_s8 (x_init); + int8x8_t y = vld1_s8 (y_init); + + x = vset_lane_s8 (16, x, 3); + if (memcmp (&x, &y, sizeof (x)) != 0) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c new file mode 100644 index 000000000..cafc26076 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c @@ -0,0 +1,21 @@ +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64_t arg0_uint64_t = 0xf00f00f00LL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; + + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c new file mode 100644 index 000000000..913d5959b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] << 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c new file mode 100644 index 000000000..82a3c5cfb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */ + +/* Verify that VSHR immediate is used. */ +void f1(int n, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] >> 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c new file mode 100644 index 000000000..a3bee6cb5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint32_t buffer[64]; + +void __attribute__((noinline)) +foo (uint32_t *a) +{ + uint32x4x3_t x; + + x = vld3q_u32 (a); + a[35] = 1; + vst3q_lane_u32 (a + 32, x, 1); +} + +int +main (void) +{ + foo (buffer); + return buffer[35] != 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c new file mode 100644 index 000000000..239470041 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c @@ -0,0 +1,21 @@ +/* Test the `vsub_s64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + int64x1_t out_int64x1_t = 0; + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL; + int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL; + + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c new file mode 100644 index 000000000..0162e206e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c @@ -0,0 +1,21 @@ +/* Test the `vsub_u64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main (void) +{ + uint64x1_t out_uint64x1_t = 0; + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL; + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL; + + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c new file mode 100644 index 000000000..3a0b117c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" +#include <stdio.h> + +extern void abort (void); + +int +main (void) +{ + uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff, + ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 }; + int i, j; + + for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i) + { + for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j) + { + uint64_t a1 = args[i]; + uint64_t a2 = args[j]; + uint64_t res = vtst_p64 (vreinterpret_p64_u64 (a1), + vreinterpret_p64_u64 (a2)); + uint64_t exp = (a1 & a2) ? ~0x0 : 0x0; + + if (res != exp) + { + fprintf (stderr, "vtst_p64 (a1= %lx, a2= %lx)" + " returned %lx, expected %lx\n", + a1, a2, res, exp); + abort (); + } + } + } + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp new file mode 100644 index 000000000..746429dad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c new file mode 100644 index 000000000..f91f800a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c @@ -0,0 +1,48 @@ +/* Check that NEON polynomial vector types are suitably incompatible with + integer vector types of the same layout. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void s64_8 (int8x8_t a) {} +void u64_8 (uint8x8_t a) {} +void p64_8 (poly8x8_t a) {} +void s64_16 (int16x4_t a) {} +void u64_16 (uint16x4_t a) {} +void p64_16 (poly16x4_t a) {} + +void s128_8 (int8x16_t a) {} +void u128_8 (uint8x16_t a) {} +void p128_8 (poly8x16_t a) {} +void s128_16 (int16x8_t a) {} +void u128_16 (uint16x8_t a) {} +void p128_16 (poly16x8_t a) {} + +void foo () +{ + poly8x8_t v64_8; + poly16x4_t v64_16; + poly8x16_t v128_8; + poly16x8_t v128_16; + + s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */ + /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */ + u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */ + p64_8 (v64_8); + + s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */ + u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */ + p64_16 (v64_16); + + s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */ + u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */ + p128_8 (v128_8); + + s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */ + u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */ + p128_16 (v128_16); +} +/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c new file mode 100644 index 000000000..71cbb055f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c @@ -0,0 +1,84 @@ +/* Test the vector comparison intrinsics when comparing to immediate zero. + */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +#define GEN_TEST(T, D, C, R) \ + R test_##C##_##T (T a) { return C (a, D (0)); } + +#define GEN_DOUBLE_TESTS(S, T, C) \ + GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \ + GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) + +#define GEN_QUAD_TESTS(S, T, C) \ + GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \ + GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) + +#define GEN_COND_TESTS(C) \ + GEN_DOUBLE_TESTS (8, int8x8_t, C) \ + GEN_DOUBLE_TESTS (16, int16x4_t, C) \ + GEN_DOUBLE_TESTS (32, int32x2_t, C) \ + GEN_QUAD_TESTS (8, int8x16_t, C) \ + GEN_QUAD_TESTS (16, int16x8_t, C) \ + GEN_QUAD_TESTS (32, int32x4_t, C) + +GEN_COND_TESTS(vcgt) +GEN_COND_TESTS(vcge) +GEN_COND_TESTS(vclt) +GEN_COND_TESTS(vcle) +GEN_COND_TESTS(vceq) + +/* Scan for expected outputs. */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ +/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */ + +/* And ensure we don't have unexpected output too. */ +/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */ + +/* Tidy up. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c new file mode 100644 index 000000000..8a8032d01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c new file mode 100644 index 000000000..45b577631 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c new file mode 100644 index 000000000..4e564ee10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c new file mode 100644 index 000000000..f036e0438 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c new file mode 100644 index 000000000..f9fbb869d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c new file mode 100644 index 000000000..853ab7fcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vRaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c new file mode 100644 index 000000000..1be084ede --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c new file mode 100644 index 000000000..acc6c0176 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c new file mode 100644 index 000000000..bfac186e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c new file mode 100644 index 000000000..10dcdfe12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c new file mode 100644 index 000000000..9c6178135 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c new file mode 100644 index 000000000..ac8488498 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c new file mode 100644 index 000000000..a1207e2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c new file mode 100644 index 000000000..758572982 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c new file mode 100644 index 000000000..c6048c2e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c @@ -0,0 +1,21 @@ +/* Test the `vRhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c new file mode 100644 index 000000000..41e03fe6d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c new file mode 100644 index 000000000..f0cdae6d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c new file mode 100644 index 000000000..278496f28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vRhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c new file mode 100644 index 000000000..622cd3843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c new file mode 100644 index 000000000..9d6c8b849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c new file mode 100644 index 000000000..d9f1accae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c new file mode 100644 index 000000000..695e9e17f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c new file mode 100644 index 000000000..1abf88844 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c new file mode 100644 index 000000000..ee517d83b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c new file mode 100644 index 000000000..ec46e7632 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c new file mode 100644 index 000000000..3abdefcd8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c new file mode 100644 index 000000000..5d13fac3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c @@ -0,0 +1,21 @@ +/* Test the `vRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c new file mode 100644 index 000000000..71ed3401f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c @@ -0,0 +1,21 @@ +/* Test the `vRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c new file mode 100644 index 000000000..c6e20c0dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c @@ -0,0 +1,21 @@ +/* Test the `vRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c new file mode 100644 index 000000000..b4cc42739 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c @@ -0,0 +1,21 @@ +/* Test the `vRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c new file mode 100644 index 000000000..42c77250c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c new file mode 100644 index 000000000..dfc5da7f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c new file mode 100644 index 000000000..030b5eed3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c new file mode 100644 index 000000000..2e091b39b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c new file mode 100644 index 000000000..f844a5bfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c new file mode 100644 index 000000000..a651bf484 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c new file mode 100644 index 000000000..2e78282d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c new file mode 100644 index 000000000..376fcf1d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c new file mode 100644 index 000000000..ae1555dcf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c new file mode 100644 index 000000000..18ec347c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c new file mode 100644 index 000000000..370ae502f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c new file mode 100644 index 000000000..5c5149ed0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c new file mode 100644 index 000000000..3045dddee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c new file mode 100644 index 000000000..2c3c12665 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c new file mode 100644 index 000000000..182c56b86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c new file mode 100644 index 000000000..1e41c26be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c new file mode 100644 index 000000000..c34b54e22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c new file mode 100644 index 000000000..c07863ec1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c new file mode 100644 index 000000000..910d7de54 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c new file mode 100644 index 000000000..25b5a6b5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vRshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c new file mode 100644 index 000000000..966e6c78e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c new file mode 100644 index 000000000..6227223e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c new file mode 100644 index 000000000..d219e9482 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c new file mode 100644 index 000000000..9f59e8c3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c new file mode 100644 index 000000000..d7904ea56 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c new file mode 100644 index 000000000..33d390157 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c new file mode 100644 index 000000000..cb7c469a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c new file mode 100644 index 000000000..3ac2e316e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c new file mode 100644 index 000000000..d0b6a9272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c new file mode 100644 index 000000000..af402f4f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c new file mode 100644 index 000000000..b8c0fbf1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c new file mode 100644 index 000000000..7bec98340 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c new file mode 100644 index 000000000..167a27c4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c new file mode 100644 index 000000000..14a6251fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vRsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c new file mode 100644 index 000000000..31d6f0ca3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c new file mode 100644 index 000000000..43fa61aac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c new file mode 100644 index 000000000..1b28f926a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c new file mode 100644 index 000000000..fc810c2cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c new file mode 100644 index 000000000..d951b266b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c new file mode 100644 index 000000000..f7f74c3c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c new file mode 100644 index 000000000..713c7bb1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c new file mode 100644 index 000000000..4b19bd846 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vRsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c new file mode 100644 index 000000000..8ba5a2075 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c new file mode 100644 index 000000000..26fa452c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c new file mode 100644 index 000000000..ed990790f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c new file mode 100644 index 000000000..b5e7b28ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c new file mode 100644 index 000000000..5275c97b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c new file mode 100644 index 000000000..3951ff0c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vRsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vRsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c new file mode 100644 index 000000000..4fe8aa303 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c new file mode 100644 index 000000000..0e2b06fdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c new file mode 100644 index 000000000..679805ad6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c @@ -0,0 +1,22 @@ +/* Test the `vabaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c new file mode 100644 index 000000000..87e5f2232 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c new file mode 100644 index 000000000..91ee45dfa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c new file mode 100644 index 000000000..f4adb3272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c @@ -0,0 +1,22 @@ +/* Test the `vabaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c new file mode 100644 index 000000000..14f8aa0d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c @@ -0,0 +1,22 @@ +/* Test the `vabals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c new file mode 100644 index 000000000..980b27e6d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c @@ -0,0 +1,22 @@ +/* Test the `vabals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c new file mode 100644 index 000000000..85dcb40b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c @@ -0,0 +1,22 @@ +/* Test the `vabals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c new file mode 100644 index 000000000..9cf105ee3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c @@ -0,0 +1,22 @@ +/* Test the `vabalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c new file mode 100644 index 000000000..dc9925f58 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c @@ -0,0 +1,22 @@ +/* Test the `vabalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c new file mode 100644 index 000000000..464e2cdad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c @@ -0,0 +1,22 @@ +/* Test the `vabalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c new file mode 100644 index 000000000..21f5adbdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c @@ -0,0 +1,22 @@ +/* Test the `vabas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c new file mode 100644 index 000000000..f9a41481e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c @@ -0,0 +1,22 @@ +/* Test the `vabas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c new file mode 100644 index 000000000..609680a05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c @@ -0,0 +1,22 @@ +/* Test the `vabas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c new file mode 100644 index 000000000..0896900fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c @@ -0,0 +1,22 @@ +/* Test the `vabau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c new file mode 100644 index 000000000..4f4f25abd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c @@ -0,0 +1,22 @@ +/* Test the `vabau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c new file mode 100644 index 000000000..91dfc1a83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c @@ -0,0 +1,22 @@ +/* Test the `vabau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c new file mode 100644 index 000000000..50c1acc63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c new file mode 100644 index 000000000..7ef3f2edd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c new file mode 100644 index 000000000..673b01f2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c new file mode 100644 index 000000000..5d24d228f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c @@ -0,0 +1,21 @@ +/* Test the `vabdQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c new file mode 100644 index 000000000..222384e1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c new file mode 100644 index 000000000..ef5716b69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c new file mode 100644 index 000000000..065a5f3be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c new file mode 100644 index 000000000..8fc0be271 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c @@ -0,0 +1,21 @@ +/* Test the `vabdf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c new file mode 100644 index 000000000..e9df745b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c @@ -0,0 +1,21 @@ +/* Test the `vabdls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c new file mode 100644 index 000000000..b4ad32735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c @@ -0,0 +1,21 @@ +/* Test the `vabdls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c new file mode 100644 index 000000000..75ca12502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c @@ -0,0 +1,21 @@ +/* Test the `vabdls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c new file mode 100644 index 000000000..692962ede --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c new file mode 100644 index 000000000..f5a7ef691 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c new file mode 100644 index 000000000..221729ae6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c new file mode 100644 index 000000000..2d76a286d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c @@ -0,0 +1,21 @@ +/* Test the `vabds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c new file mode 100644 index 000000000..9ca6e5d8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c @@ -0,0 +1,21 @@ +/* Test the `vabds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c new file mode 100644 index 000000000..561687047 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c @@ -0,0 +1,21 @@ +/* Test the `vabds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c new file mode 100644 index 000000000..e23873494 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c @@ -0,0 +1,21 @@ +/* Test the `vabdu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c new file mode 100644 index 000000000..61871dda4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c @@ -0,0 +1,21 @@ +/* Test the `vabdu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c new file mode 100644 index 000000000..bff9f9cf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c @@ -0,0 +1,21 @@ +/* Test the `vabdu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabdu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c new file mode 100644 index 000000000..36e145d08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c @@ -0,0 +1,20 @@ +/* Test the `vabsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vabsq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c new file mode 100644 index 000000000..befade576 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c new file mode 100644 index 000000000..8d1270012 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c new file mode 100644 index 000000000..a69d7a89e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c new file mode 100644 index 000000000..e60dd896d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c @@ -0,0 +1,20 @@ +/* Test the `vabsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vabs_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c new file mode 100644 index 000000000..9cc1ab561 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c @@ -0,0 +1,20 @@ +/* Test the `vabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c new file mode 100644 index 000000000..5f3c6353e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c @@ -0,0 +1,20 @@ +/* Test the `vabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c new file mode 100644 index 000000000..05ae5241a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c @@ -0,0 +1,20 @@ +/* Test the `vabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c new file mode 100644 index 000000000..fb856385d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c new file mode 100644 index 000000000..839af2433 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c new file mode 100644 index 000000000..f93a83221 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c new file mode 100644 index 000000000..fdc99171a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c new file mode 100644 index 000000000..49fe47812 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c new file mode 100644 index 000000000..2f6ac31a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c new file mode 100644 index 000000000..3c279b4ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c new file mode 100644 index 000000000..c525a85d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c new file mode 100644 index 000000000..975dfa37c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c new file mode 100644 index 000000000..15364b77c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c @@ -0,0 +1,21 @@ +/* Test the `vaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c new file mode 100644 index 000000000..d39d14a27 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c new file mode 100644 index 000000000..52d622164 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c new file mode 100644 index 000000000..cb593a2ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c @@ -0,0 +1,21 @@ +/* Test the `vaddhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c new file mode 100644 index 000000000..59d311fa0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c new file mode 100644 index 000000000..570b8855b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c new file mode 100644 index 000000000..2156254e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vaddhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c new file mode 100644 index 000000000..0ee3e4908 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c @@ -0,0 +1,21 @@ +/* Test the `vaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c new file mode 100644 index 000000000..3cd0978cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c @@ -0,0 +1,21 @@ +/* Test the `vaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c new file mode 100644 index 000000000..50e5197ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c @@ -0,0 +1,21 @@ +/* Test the `vaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c new file mode 100644 index 000000000..671fc9250 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c new file mode 100644 index 000000000..5a69ba320 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c new file mode 100644 index 000000000..723b45e80 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c new file mode 100644 index 000000000..4f2250e8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c @@ -0,0 +1,21 @@ +/* Test the `vadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c new file mode 100644 index 000000000..bc030289d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c @@ -0,0 +1,21 @@ +/* Test the `vadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c new file mode 100644 index 000000000..fb17e0ea3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c @@ -0,0 +1,20 @@ +/* Test the `vadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c new file mode 100644 index 000000000..e928b1250 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c @@ -0,0 +1,21 @@ +/* Test the `vadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c new file mode 100644 index 000000000..9564df38e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c new file mode 100644 index 000000000..2bc009e3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c new file mode 100644 index 000000000..18fc500b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c @@ -0,0 +1,20 @@ +/* Test the `vaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c new file mode 100644 index 000000000..625931b3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c new file mode 100644 index 000000000..b99025334 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c @@ -0,0 +1,21 @@ +/* Test the `vaddws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c new file mode 100644 index 000000000..447b8919b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c @@ -0,0 +1,21 @@ +/* Test the `vaddws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c new file mode 100644 index 000000000..f604c1ebf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c @@ -0,0 +1,21 @@ +/* Test the `vaddws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c new file mode 100644 index 000000000..f374bef96 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c new file mode 100644 index 000000000..211f79897 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c new file mode 100644 index 000000000..ae9601608 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c @@ -0,0 +1,21 @@ +/* Test the `vaddwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vaddwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c new file mode 100644 index 000000000..87c030442 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c @@ -0,0 +1,21 @@ +/* Test the `vandQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c new file mode 100644 index 000000000..3ae1a5218 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c @@ -0,0 +1,21 @@ +/* Test the `vandQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c new file mode 100644 index 000000000..cca486875 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c @@ -0,0 +1,21 @@ +/* Test the `vandQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c new file mode 100644 index 000000000..4d0ce17cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c @@ -0,0 +1,21 @@ +/* Test the `vandQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c new file mode 100644 index 000000000..ff7d646a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c @@ -0,0 +1,21 @@ +/* Test the `vandQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c new file mode 100644 index 000000000..a99a525b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c @@ -0,0 +1,21 @@ +/* Test the `vandQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c new file mode 100644 index 000000000..2484dd04c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c @@ -0,0 +1,21 @@ +/* Test the `vandQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c new file mode 100644 index 000000000..c20979fcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c @@ -0,0 +1,21 @@ +/* Test the `vandQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c new file mode 100644 index 000000000..dbb2c622f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c @@ -0,0 +1,21 @@ +/* Test the `vands16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c new file mode 100644 index 000000000..61c0c4113 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c @@ -0,0 +1,21 @@ +/* Test the `vands32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c new file mode 100644 index 000000000..13e18fb0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c @@ -0,0 +1,20 @@ +/* Test the `vands64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c new file mode 100644 index 000000000..526a50072 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c @@ -0,0 +1,21 @@ +/* Test the `vands8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vands8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c new file mode 100644 index 000000000..5c998856f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c @@ -0,0 +1,21 @@ +/* Test the `vandu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c new file mode 100644 index 000000000..8a936e673 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c @@ -0,0 +1,21 @@ +/* Test the `vandu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c new file mode 100644 index 000000000..d9ddf847a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c @@ -0,0 +1,20 @@ +/* Test the `vandu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c new file mode 100644 index 000000000..728c5a6d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c @@ -0,0 +1,21 @@ +/* Test the `vandu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vandu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c new file mode 100644 index 000000000..e15a260ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c new file mode 100644 index 000000000..f376bf077 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c new file mode 100644 index 000000000..87049f129 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c new file mode 100644 index 000000000..4f64e8817 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c @@ -0,0 +1,21 @@ +/* Test the `vbicQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c new file mode 100644 index 000000000..f92f9b384 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c new file mode 100644 index 000000000..06d10da23 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c new file mode 100644 index 000000000..7cd63c035 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c new file mode 100644 index 000000000..3f44418d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c @@ -0,0 +1,21 @@ +/* Test the `vbicQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c new file mode 100644 index 000000000..943e30534 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c @@ -0,0 +1,21 @@ +/* Test the `vbics16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c new file mode 100644 index 000000000..30df639e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c @@ -0,0 +1,21 @@ +/* Test the `vbics32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c new file mode 100644 index 000000000..379db45f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c @@ -0,0 +1,20 @@ +/* Test the `vbics64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c new file mode 100644 index 000000000..3b4bc8a8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c @@ -0,0 +1,21 @@ +/* Test the `vbics8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbics8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c new file mode 100644 index 000000000..e9952bc52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c @@ -0,0 +1,21 @@ +/* Test the `vbicu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c new file mode 100644 index 000000000..9334f403f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c @@ -0,0 +1,21 @@ +/* Test the `vbicu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c new file mode 100644 index 000000000..c276d65eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c @@ -0,0 +1,20 @@ +/* Test the `vbicu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c new file mode 100644 index 000000000..5e42c5237 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c @@ -0,0 +1,21 @@ +/* Test the `vbicu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbicu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c new file mode 100644 index 000000000..33bc0257e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQf32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c new file mode 100644 index 000000000..06db6555d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQp16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + poly16x8_t arg1_poly16x8_t; + poly16x8_t arg2_poly16x8_t; + + out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c new file mode 100644 index 000000000..519ee370d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vbslQp64 (void) +{ + poly64x2_t out_poly64x2_t; + uint64x2_t arg0_uint64x2_t; + poly64x2_t arg1_poly64x2_t; + poly64x2_t arg2_poly64x2_t; + + out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c new file mode 100644 index 000000000..52d498b8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQp8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + poly8x16_t arg1_poly8x16_t; + poly8x16_t arg2_poly8x16_t; + + out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c new file mode 100644 index 000000000..f8f090f52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c new file mode 100644 index 000000000..194ecdb35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c new file mode 100644 index 000000000..cba963da0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + int64x2_t arg2_int64x2_t; + + out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c new file mode 100644 index 000000000..fe8a64c5d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQs8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c new file mode 100644 index 000000000..121ce1edc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c new file mode 100644 index 000000000..dc213f1a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c new file mode 100644 index 000000000..6635e652f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + uint64x2_t arg2_uint64x2_t; + + out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c new file mode 100644 index 000000000..0fc6eb820 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c @@ -0,0 +1,22 @@ +/* Test the `vbslQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c new file mode 100644 index 000000000..ea8750da5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c @@ -0,0 +1,22 @@ +/* Test the `vbslf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslf32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c new file mode 100644 index 000000000..632fea22f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c @@ -0,0 +1,22 @@ +/* Test the `vbslp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslp16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + poly16x4_t arg1_poly16x4_t; + poly16x4_t arg2_poly16x4_t; + + out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c new file mode 100644 index 000000000..51929274d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c @@ -0,0 +1,22 @@ +/* Test the `vbslp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vbslp64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64x1_t arg0_uint64x1_t; + poly64x1_t arg1_poly64x1_t; + poly64x1_t arg2_poly64x1_t; + + out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c new file mode 100644 index 000000000..a867a3b12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c @@ -0,0 +1,22 @@ +/* Test the `vbslp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslp8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + poly8x8_t arg1_poly8x8_t; + poly8x8_t arg2_poly8x8_t; + + out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c new file mode 100644 index 000000000..849b8ff85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c @@ -0,0 +1,22 @@ +/* Test the `vbsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c new file mode 100644 index 000000000..734560180 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c @@ -0,0 +1,22 @@ +/* Test the `vbsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c new file mode 100644 index 000000000..79516cd89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c @@ -0,0 +1,22 @@ +/* Test the `vbsls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + int64x1_t arg2_int64x1_t; + + out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c new file mode 100644 index 000000000..7cfd379b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c @@ -0,0 +1,22 @@ +/* Test the `vbsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbsls8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c new file mode 100644 index 000000000..aef15fa6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c @@ -0,0 +1,22 @@ +/* Test the `vbslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c new file mode 100644 index 000000000..e04e349ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c @@ -0,0 +1,22 @@ +/* Test the `vbslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c new file mode 100644 index 000000000..a4a53af2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c @@ -0,0 +1,22 @@ +/* Test the `vbslu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + uint64x1_t arg2_uint64x1_t; + + out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c new file mode 100644 index 000000000..154ea961d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c @@ -0,0 +1,22 @@ +/* Test the `vbslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vbslu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c new file mode 100644 index 000000000..8b5995525 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcageQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcageQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c new file mode 100644 index 000000000..0d45e320e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c @@ -0,0 +1,21 @@ +/* Test the `vcagef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c new file mode 100644 index 000000000..cef77b38c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcagtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c new file mode 100644 index 000000000..89b875927 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c @@ -0,0 +1,21 @@ +/* Test the `vcagtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcagtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c new file mode 100644 index 000000000..8cfef154d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c new file mode 100644 index 000000000..1101fde68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c @@ -0,0 +1,21 @@ +/* Test the `vcalef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcalef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c new file mode 100644 index 000000000..1d2cf7445 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c new file mode 100644 index 000000000..6a8a8171e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c @@ -0,0 +1,21 @@ +/* Test the `vcaltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcaltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c new file mode 100644 index 000000000..14ad3e7dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c new file mode 100644 index 000000000..80a8f6233 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c new file mode 100644 index 000000000..843bfe0ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c new file mode 100644 index 000000000..f25faa5ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c new file mode 100644 index 000000000..77bda24d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c new file mode 100644 index 000000000..c6293f285 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c new file mode 100644 index 000000000..7090033be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c new file mode 100644 index 000000000..3ff24d546 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c @@ -0,0 +1,21 @@ +/* Test the `vceqQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c new file mode 100644 index 000000000..b150b32c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c @@ -0,0 +1,21 @@ +/* Test the `vceqf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c new file mode 100644 index 000000000..2e4e608d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c @@ -0,0 +1,21 @@ +/* Test the `vceqp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c new file mode 100644 index 000000000..3cf450228 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c @@ -0,0 +1,21 @@ +/* Test the `vceqs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c new file mode 100644 index 000000000..989484130 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c @@ -0,0 +1,21 @@ +/* Test the `vceqs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c new file mode 100644 index 000000000..825214ae4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c @@ -0,0 +1,21 @@ +/* Test the `vceqs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vceqs8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c new file mode 100644 index 000000000..b7dd5450d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c @@ -0,0 +1,21 @@ +/* Test the `vcequ16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c new file mode 100644 index 000000000..7864cfdf8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c @@ -0,0 +1,21 @@ +/* Test the `vcequ32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c new file mode 100644 index 000000000..8b8b26fba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c @@ -0,0 +1,21 @@ +/* Test the `vcequ8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcequ8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c new file mode 100644 index 000000000..b0eb53cfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c new file mode 100644 index 000000000..2ef989ac1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c new file mode 100644 index 000000000..2bef01abb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c new file mode 100644 index 000000000..15083d35e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c new file mode 100644 index 000000000..59c609b65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c new file mode 100644 index 000000000..fa4d67cf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c new file mode 100644 index 000000000..39dee295c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c new file mode 100644 index 000000000..797f43f6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c @@ -0,0 +1,21 @@ +/* Test the `vcgef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c new file mode 100644 index 000000000..52984c796 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c @@ -0,0 +1,21 @@ +/* Test the `vcges16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c new file mode 100644 index 000000000..935bde799 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c @@ -0,0 +1,21 @@ +/* Test the `vcges32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c new file mode 100644 index 000000000..15abad3fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c @@ -0,0 +1,21 @@ +/* Test the `vcges8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcges8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c new file mode 100644 index 000000000..ec96ebc74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c new file mode 100644 index 000000000..12c67bf7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c new file mode 100644 index 000000000..5457b91a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgeu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgeu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c new file mode 100644 index 000000000..9f6e6dc2d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c new file mode 100644 index 000000000..b733e6ffa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c new file mode 100644 index 000000000..eae07ad12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c new file mode 100644 index 000000000..2f82a9539 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c new file mode 100644 index 000000000..080a7af7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c new file mode 100644 index 000000000..0dfb361b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c new file mode 100644 index 000000000..0643e22e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c new file mode 100644 index 000000000..833bf1f55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c new file mode 100644 index 000000000..141df1061 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c @@ -0,0 +1,21 @@ +/* Test the `vcgts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c new file mode 100644 index 000000000..6350041d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c @@ -0,0 +1,21 @@ +/* Test the `vcgts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c new file mode 100644 index 000000000..1ad43968a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c @@ -0,0 +1,21 @@ +/* Test the `vcgts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c new file mode 100644 index 000000000..e3b2c80c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c new file mode 100644 index 000000000..60e6a9f1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c new file mode 100644 index 000000000..858647548 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c @@ -0,0 +1,21 @@ +/* Test the `vcgtu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcgtu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c new file mode 100644 index 000000000..770da7b04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c new file mode 100644 index 000000000..f4f69e2b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c new file mode 100644 index 000000000..49d6cc0f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c new file mode 100644 index 000000000..32447e67a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcleQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c new file mode 100644 index 000000000..3c8ae5217 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c new file mode 100644 index 000000000..e2556e38e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c new file mode 100644 index 000000000..48e3ee239 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcleQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c new file mode 100644 index 000000000..88fa76483 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c @@ -0,0 +1,21 @@ +/* Test the `vclef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclef32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c new file mode 100644 index 000000000..885c5d510 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c @@ -0,0 +1,21 @@ +/* Test the `vcles16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c new file mode 100644 index 000000000..5bbd0d2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c @@ -0,0 +1,21 @@ +/* Test the `vcles32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c new file mode 100644 index 000000000..e247608db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c @@ -0,0 +1,21 @@ +/* Test the `vcles8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcles8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c new file mode 100644 index 000000000..6fcacbadd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c @@ -0,0 +1,21 @@ +/* Test the `vcleu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c new file mode 100644 index 000000000..568f56f99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c @@ -0,0 +1,21 @@ +/* Test the `vcleu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c new file mode 100644 index 000000000..81884bf72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c @@ -0,0 +1,21 @@ +/* Test the `vcleu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcleu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c new file mode 100644 index 000000000..22009dce0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c new file mode 100644 index 000000000..a4e2d70c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c new file mode 100644 index 000000000..91394e198 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vclsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c new file mode 100644 index 000000000..c98508412 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c @@ -0,0 +1,20 @@ +/* Test the `vclss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vcls_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c new file mode 100644 index 000000000..4f3e16f88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c @@ -0,0 +1,20 @@ +/* Test the `vclss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vcls_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c new file mode 100644 index 000000000..3c363745f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c @@ -0,0 +1,20 @@ +/* Test the `vclss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcls_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c new file mode 100644 index 000000000..1616849a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQf32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c new file mode 100644 index 000000000..794d2c4b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c new file mode 100644 index 000000000..871519b14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c new file mode 100644 index 000000000..41d32111f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c @@ -0,0 +1,21 @@ +/* Test the `vcltQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c new file mode 100644 index 000000000..209bc3d0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c new file mode 100644 index 000000000..797c62a81 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c new file mode 100644 index 000000000..5a067fedf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c @@ -0,0 +1,21 @@ +/* Test the `vcltQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c new file mode 100644 index 000000000..82ef84fb6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c @@ -0,0 +1,21 @@ +/* Test the `vcltf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltf32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c new file mode 100644 index 000000000..b6aaeabb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c @@ -0,0 +1,21 @@ +/* Test the `vclts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c new file mode 100644 index 000000000..cb66ca98e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c @@ -0,0 +1,21 @@ +/* Test the `vclts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c new file mode 100644 index 000000000..60bbf636c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c @@ -0,0 +1,21 @@ +/* Test the `vclts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c new file mode 100644 index 000000000..e5d2918cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c @@ -0,0 +1,21 @@ +/* Test the `vcltu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c new file mode 100644 index 000000000..936e6b867 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c @@ -0,0 +1,21 @@ +/* Test the `vcltu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c new file mode 100644 index 000000000..ab73e1f18 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c @@ -0,0 +1,21 @@ +/* Test the `vcltu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcltu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c new file mode 100644 index 000000000..24df7b676 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vclzq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c new file mode 100644 index 000000000..1e01ee9e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vclzq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c new file mode 100644 index 000000000..80e40fd86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c @@ -0,0 +1,20 @@ +/* Test the `vclzQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vclzq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c new file mode 100644 index 000000000..2b023fa24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c new file mode 100644 index 000000000..529cbcf58 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c new file mode 100644 index 000000000..2be4915ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c @@ -0,0 +1,20 @@ +/* Test the `vclzQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c new file mode 100644 index 000000000..b024559f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c @@ -0,0 +1,20 @@ +/* Test the `vclzs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vclz_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c new file mode 100644 index 000000000..b01e429c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c @@ -0,0 +1,20 @@ +/* Test the `vclzs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vclz_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c new file mode 100644 index 000000000..b23be0c1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c @@ -0,0 +1,20 @@ +/* Test the `vclzs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vclz_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c new file mode 100644 index 000000000..4f2516326 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c @@ -0,0 +1,20 @@ +/* Test the `vclzu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c new file mode 100644 index 000000000..4dd898345 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c @@ -0,0 +1,20 @@ +/* Test the `vclzu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c new file mode 100644 index 000000000..4bfe49878 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c @@ -0,0 +1,20 @@ +/* Test the `vclzu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vclzu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c new file mode 100644 index 000000000..15a4f7154 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c new file mode 100644 index 000000000..fb6511903 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vcntq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c new file mode 100644 index 000000000..dea80786b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c @@ -0,0 +1,20 @@ +/* Test the `vcntQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c new file mode 100644 index 000000000..39e0d1100 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c @@ -0,0 +1,20 @@ +/* Test the `vcntp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c new file mode 100644 index 000000000..89ae7b7b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c @@ -0,0 +1,20 @@ +/* Test the `vcnts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcnts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vcnt_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c new file mode 100644 index 000000000..9a5f2f045 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c @@ -0,0 +1,20 @@ +/* Test the `vcntu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcntu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c new file mode 100644 index 000000000..a177288dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c @@ -0,0 +1,20 @@ +/* Test the `vcombinef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c new file mode 100644 index 000000000..79b4440b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c new file mode 100644 index 000000000..d5e156bdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vcombinep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c new file mode 100644 index 000000000..0fa1af6df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c @@ -0,0 +1,20 @@ +/* Test the `vcombinep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombinep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c new file mode 100644 index 000000000..9799f99b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c @@ -0,0 +1,20 @@ +/* Test the `vcombines16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c new file mode 100644 index 000000000..d68676c3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c @@ -0,0 +1,20 @@ +/* Test the `vcombines32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c new file mode 100644 index 000000000..389941540 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c @@ -0,0 +1,20 @@ +/* Test the `vcombines64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c new file mode 100644 index 000000000..b3c8d3a7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c @@ -0,0 +1,20 @@ +/* Test the `vcombines8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombines8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c new file mode 100644 index 000000000..f35528b6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c new file mode 100644 index 000000000..9c10e8597 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c new file mode 100644 index 000000000..fac517b48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c new file mode 100644 index 000000000..808a9f299 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c @@ -0,0 +1,20 @@ +/* Test the `vcombineu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcombineu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c new file mode 100644 index 000000000..68fe67e50 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c @@ -0,0 +1,19 @@ +/* Test the `vcreatef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatef32 (void) +{ + float32x2_t out_float32x2_t; + uint64_t arg0_uint64_t; + + out_float32x2_t = vcreate_f32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c new file mode 100644 index 000000000..b02247259 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatep16 (void) +{ + poly16x4_t out_poly16x4_t; + uint64_t arg0_uint64_t; + + out_poly16x4_t = vcreate_p16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c new file mode 100644 index 000000000..7aedb73fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vcreatep64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64_t arg0_uint64_t; + + out_poly64x1_t = vcreate_p64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c new file mode 100644 index 000000000..7a3f607dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c @@ -0,0 +1,19 @@ +/* Test the `vcreatep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreatep8 (void) +{ + poly8x8_t out_poly8x8_t; + uint64_t arg0_uint64_t; + + out_poly8x8_t = vcreate_p8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c new file mode 100644 index 000000000..2adfeb31e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c @@ -0,0 +1,19 @@ +/* Test the `vcreates16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates16 (void) +{ + int16x4_t out_int16x4_t; + uint64_t arg0_uint64_t; + + out_int16x4_t = vcreate_s16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c new file mode 100644 index 000000000..4212dcba5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c @@ -0,0 +1,19 @@ +/* Test the `vcreates32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates32 (void) +{ + int32x2_t out_int32x2_t; + uint64_t arg0_uint64_t; + + out_int32x2_t = vcreate_s32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c new file mode 100644 index 000000000..77e4a51b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c @@ -0,0 +1,19 @@ +/* Test the `vcreates64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates64 (void) +{ + int64x1_t out_int64x1_t; + uint64_t arg0_uint64_t; + + out_int64x1_t = vcreate_s64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c new file mode 100644 index 000000000..0c0d546aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c @@ -0,0 +1,19 @@ +/* Test the `vcreates8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreates8 (void) +{ + int8x8_t out_int8x8_t; + uint64_t arg0_uint64_t; + + out_int8x8_t = vcreate_s8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c new file mode 100644 index 000000000..d8004802b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint64_t arg0_uint64_t; + + out_uint16x4_t = vcreate_u16 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c new file mode 100644 index 000000000..42d72adc3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint64_t arg0_uint64_t; + + out_uint32x2_t = vcreate_u32 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c new file mode 100644 index 000000000..5b0b37865 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vcreate_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c new file mode 100644 index 000000000..ea4114617 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c @@ -0,0 +1,19 @@ +/* Test the `vcreateu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcreateu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint64_t arg0_uint64_t; + + out_uint8x8_t = vcreate_u8 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c new file mode 100644 index 000000000..85916e770 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c new file mode 100644 index 000000000..ab20ff0ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c new file mode 100644 index 000000000..76ce86a0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_ns32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c new file mode 100644 index 000000000..16de37fe1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQ_nu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c new file mode 100644 index 000000000..1160edeab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c new file mode 100644 index 000000000..285e1dd89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c new file mode 100644 index 000000000..562137430 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c new file mode 100644 index 000000000..f2ea8f541 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c new file mode 100644 index 000000000..403fe621c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c new file mode 100644 index 000000000..dc344a3ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c new file mode 100644 index 000000000..b50b20e01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_ns32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_ns32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c new file mode 100644 index 000000000..b003f0097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvt_nu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvt_nu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c new file mode 100644 index 000000000..6675596d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vcvtf16_f32 (void) +{ + float16x4_t out_float16x4_t; + float32x4_t arg0_float32x4_t; + + out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f16.f32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c new file mode 100644 index 000000000..dd0ce1702 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_f16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vcvtf32_f16 (void) +{ + float32x4_t out_float32x4_t; + float16x4_t arg0_float16x4_t; + + out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.f16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c new file mode 100644 index 000000000..e0ca9b062 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c new file mode 100644 index 000000000..b3b44bedf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c new file mode 100644 index 000000000..b626fbf74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvts32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvts32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c new file mode 100644 index 000000000..8c86d47af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c @@ -0,0 +1,20 @@ +/* Test the `vcvtu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vcvtu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c new file mode 100644 index 000000000..8593d871a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x2_t arg0_float32x2_t; + + out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c new file mode 100644 index 000000000..b48966b76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c new file mode 100644 index 000000000..6211413c7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x1_t arg0_poly64x1_t; + + out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c new file mode 100644 index 000000000..ebe7a0da5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c new file mode 100644 index 000000000..dae7cb568 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x4_t arg0_int16x4_t; + + out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c new file mode 100644 index 000000000..4ef5cb789 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x2_t arg0_int32x2_t; + + out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c new file mode 100644 index 000000000..9c41050e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x1_t arg0_int64x1_t; + + out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c new file mode 100644 index 000000000..428dfc404 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x8_t arg0_int8x8_t; + + out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c new file mode 100644 index 000000000..840e6e2b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c new file mode 100644 index 000000000..76f3c756f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c new file mode 100644 index 000000000..8a6487135 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c new file mode 100644 index 000000000..c4886e62d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c new file mode 100644 index 000000000..5f7305aca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vdupq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c new file mode 100644 index 000000000..bd73329cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c new file mode 100644 index 000000000..68a1d746b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdupQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64_t arg0_poly64_t; + + out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c new file mode 100644 index 000000000..7c90d560d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c new file mode 100644 index 000000000..de837d919 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vdupq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c new file mode 100644 index 000000000..00f175cec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vdupq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c new file mode 100644 index 000000000..ab749a7bb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c new file mode 100644 index 000000000..3794d6eb1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vdupq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c new file mode 100644 index 000000000..fed6ea227 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c new file mode 100644 index 000000000..5b96fbcdd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c new file mode 100644 index 000000000..0ddb72dec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vdupQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c new file mode 100644 index 000000000..a490472fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vdupQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdupQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c new file mode 100644 index 000000000..495f189bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c new file mode 100644 index 000000000..f951fac35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c new file mode 100644 index 000000000..ab263f170 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdup_lanep64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c new file mode 100644 index 000000000..dad99e4fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c new file mode 100644 index 000000000..046d440ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c new file mode 100644 index 000000000..f249a626a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c new file mode 100644 index 000000000..628140fd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c new file mode 100644 index 000000000..9ca250152 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c new file mode 100644 index 000000000..1b3dd02a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c new file mode 100644 index 000000000..520757873 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c new file mode 100644 index 000000000..a9de614c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c new file mode 100644 index 000000000..5687c0b47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c new file mode 100644 index 000000000..ba99fdce5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vdup_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c new file mode 100644 index 000000000..55bca29b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c new file mode 100644 index 000000000..3b6b7ec31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vdup_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64_t arg0_poly64_t; + + out_poly64x1_t = vdup_n_p64 (arg0_poly64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c new file mode 100644 index 000000000..80d29e860 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c new file mode 100644 index 000000000..4d1ea6a6e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vdup_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c new file mode 100644 index 000000000..9fb1fc289 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vdup_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c new file mode 100644 index 000000000..033f1b474 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vdup_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c new file mode 100644 index 000000000..eba462c79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vdup_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c new file mode 100644 index 000000000..24015e592 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c new file mode 100644 index 000000000..78374d42a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c new file mode 100644 index 000000000..6888125c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vdup_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c new file mode 100644 index 000000000..ee35ff37b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vdup_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vdup_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c new file mode 100644 index 000000000..f31d9bfab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c new file mode 100644 index 000000000..f3f01c65e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */ +/* { dg-add-options arm_neon } */ + +#define N 32 + +int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float fa[N]; +int ia[N]; + +int convert() +{ + int i; + + /* int -> float */ + for (i = 0; i < N; i++) + fa[i] = (float) ib[i]; + + /* float -> int */ + for (i = 0; i < N; i++) + ia[i] = (int) fa[i]; + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c new file mode 100644 index 000000000..a0428bee7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c @@ -0,0 +1,21 @@ +/* Test the `veorQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c new file mode 100644 index 000000000..7b24ea477 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c @@ -0,0 +1,21 @@ +/* Test the `veorQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c new file mode 100644 index 000000000..fd023171a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c @@ -0,0 +1,21 @@ +/* Test the `veorQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c new file mode 100644 index 000000000..17da85c6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c @@ -0,0 +1,21 @@ +/* Test the `veorQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c new file mode 100644 index 000000000..d2865e9fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c @@ -0,0 +1,21 @@ +/* Test the `veorQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c new file mode 100644 index 000000000..76370677d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c @@ -0,0 +1,21 @@ +/* Test the `veorQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c new file mode 100644 index 000000000..156b07b34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c @@ -0,0 +1,21 @@ +/* Test the `veorQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c new file mode 100644 index 000000000..b3ff98343 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c @@ -0,0 +1,21 @@ +/* Test the `veorQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veorQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c new file mode 100644 index 000000000..8af437edf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c @@ -0,0 +1,21 @@ +/* Test the `veors16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c new file mode 100644 index 000000000..105780393 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c @@ -0,0 +1,21 @@ +/* Test the `veors32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c new file mode 100644 index 000000000..2781be1b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c @@ -0,0 +1,20 @@ +/* Test the `veors64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c new file mode 100644 index 000000000..cda05c7e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c @@ -0,0 +1,21 @@ +/* Test the `veors8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veors8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c new file mode 100644 index 000000000..d89d87302 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c @@ -0,0 +1,21 @@ +/* Test the `veoru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c new file mode 100644 index 000000000..7804a8c16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c @@ -0,0 +1,21 @@ +/* Test the `veoru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c new file mode 100644 index 000000000..19d081489 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c @@ -0,0 +1,20 @@ +/* Test the `veoru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c new file mode 100644 index 000000000..aad32de44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c @@ -0,0 +1,21 @@ +/* Test the `veoru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_veoru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c new file mode 100644 index 000000000..92597f9bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c @@ -0,0 +1,21 @@ +/* Test the `vextQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c new file mode 100644 index 000000000..546da6990 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c @@ -0,0 +1,21 @@ +/* Test the `vextQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c new file mode 100644 index 000000000..bc5e08aa7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c @@ -0,0 +1,21 @@ +/* Test the `vextQp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vextQp64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c new file mode 100644 index 000000000..f9273c2d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c @@ -0,0 +1,21 @@ +/* Test the `vextQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c new file mode 100644 index 000000000..d95ff2976 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c @@ -0,0 +1,21 @@ +/* Test the `vextQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c new file mode 100644 index 000000000..b6824ff6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c @@ -0,0 +1,21 @@ +/* Test the `vextQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c new file mode 100644 index 000000000..226aa207f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c @@ -0,0 +1,21 @@ +/* Test the `vextQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c new file mode 100644 index 000000000..274279a2d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c @@ -0,0 +1,21 @@ +/* Test the `vextQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c new file mode 100644 index 000000000..36fcb5273 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c @@ -0,0 +1,21 @@ +/* Test the `vextQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c new file mode 100644 index 000000000..082592a0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c @@ -0,0 +1,21 @@ +/* Test the `vextQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c new file mode 100644 index 000000000..ac496db0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c @@ -0,0 +1,21 @@ +/* Test the `vextQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c new file mode 100644 index 000000000..e77b9a2e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c @@ -0,0 +1,21 @@ +/* Test the `vextQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c new file mode 100644 index 000000000..5f7ef947c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c @@ -0,0 +1,21 @@ +/* Test the `vextf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c new file mode 100644 index 000000000..f1e176efb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c @@ -0,0 +1,21 @@ +/* Test the `vextp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c new file mode 100644 index 000000000..aa1e91f59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c @@ -0,0 +1,21 @@ +/* Test the `vextp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vextp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c new file mode 100644 index 000000000..feb2fdd07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c @@ -0,0 +1,21 @@ +/* Test the `vextp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c new file mode 100644 index 000000000..1d3eb7980 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c @@ -0,0 +1,21 @@ +/* Test the `vexts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c new file mode 100644 index 000000000..e83a0de6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c @@ -0,0 +1,21 @@ +/* Test the `vexts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c new file mode 100644 index 000000000..e594beca5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c @@ -0,0 +1,21 @@ +/* Test the `vexts64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c new file mode 100644 index 000000000..0575bd349 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c @@ -0,0 +1,21 @@ +/* Test the `vexts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vexts8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c new file mode 100644 index 000000000..b94afdf61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c @@ -0,0 +1,21 @@ +/* Test the `vextu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); +} + +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c new file mode 100644 index 000000000..39bdf31ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c @@ -0,0 +1,21 @@ +/* Test the `vextu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); +} + +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c new file mode 100644 index 000000000..17afbd751 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c @@ -0,0 +1,21 @@ +/* Test the `vextu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c new file mode 100644 index 000000000..5176a7201 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c @@ -0,0 +1,21 @@ +/* Test the `vextu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vextu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); +} + +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c new file mode 100644 index 000000000..d400163a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmaQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmaQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c new file mode 100644 index 000000000..988328dd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c new file mode 100644 index 000000000..247a8edfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c new file mode 100644 index 000000000..7f9e8570d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c @@ -0,0 +1,22 @@ +/* Test the `vfmsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neonv2_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neonv2 } */ + +#include "arm_neon.h" + +void test_vfmsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c new file mode 100644 index 000000000..5c772c04c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c @@ -0,0 +1,28 @@ +/* Check that NEON vector shifts support immediate values == size. /* + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +uint16x8_t test_vshll_n_u8 (uint8x8_t a) +{ + return vshll_n_u8(a, 8); +} + +uint32x4_t test_vshll_n_u16 (uint16x4_t a) +{ + return vshll_n_u16(a, 16); +} + +uint64x2_t test_vshll_n_u32 (uint32x2_t a) +{ + return vshll_n_u32(a, 32); +} + +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c new file mode 100644 index 000000000..54e04c50a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanef32 (void) +{ + float32_t out_float32_t; + float32x4_t arg0_float32x4_t; + + out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c new file mode 100644 index 000000000..cfb5447bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c new file mode 100644 index 000000000..7325dd744 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c new file mode 100644 index 000000000..f992d17a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes16 (void) +{ + int16_t out_int16_t; + int16x8_t arg0_int16x8_t; + + out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c new file mode 100644 index 000000000..36cb88ff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes32 (void) +{ + int32_t out_int32_t; + int32x4_t arg0_int32x4_t; + + out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c new file mode 100644 index 000000000..e3d3c178e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes64 (void) +{ + register int64_t out_int64_t asm ("r0"); + int64x2_t arg0_int64x2_t; + + out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c new file mode 100644 index 000000000..7ce2cc651 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_lanes8 (void) +{ + int8_t out_int8_t; + int8x16_t arg0_int8x16_t; + + out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c new file mode 100644 index 000000000..d44f05f2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c new file mode 100644 index 000000000..3004f503c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c new file mode 100644 index 000000000..3426e4694 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu64 (void) +{ + register uint64_t out_uint64_t asm ("r0"); + uint64x2_t arg0_uint64x2_t; + + out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c new file mode 100644 index 000000000..57528f2f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vgetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vgetQ_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c new file mode 100644 index 000000000..60f935e97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highf32 (void) +{ + float32x2_t out_float32x2_t; + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_high_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c new file mode 100644 index 000000000..660b83e34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highp16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c new file mode 100644 index 000000000..f2b1b7a9e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vget_highp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x2_t arg0_poly64x2_t; + + out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c new file mode 100644 index 000000000..e9519606e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c new file mode 100644 index 000000000..ca4e7706e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs16 (void) +{ + int16x4_t out_int16x4_t; + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_high_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c new file mode 100644 index 000000000..77ead1ac8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs32 (void) +{ + int32x2_t out_int32x2_t; + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_high_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c new file mode 100644 index 000000000..cb6a48480 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_high_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c new file mode 100644 index 000000000..ec249f823 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highs8 (void) +{ + int8x8_t out_int8x8_t; + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_high_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c new file mode 100644 index 000000000..263a920aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c new file mode 100644 index 000000000..4797a132e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c new file mode 100644 index 000000000..899309f1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c new file mode 100644 index 000000000..a0c689736 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c @@ -0,0 +1,19 @@ +/* Test the `vget_highu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_highu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c new file mode 100644 index 000000000..908adeb70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanef32 (void) +{ + float32_t out_float32_t; + float32x2_t arg0_float32x2_t; + + out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c new file mode 100644 index 000000000..0dcf90b57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanep16 (void) +{ + poly16_t out_poly16_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c new file mode 100644 index 000000000..22b06bdf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanep8 (void) +{ + poly8_t out_poly8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c new file mode 100644 index 000000000..4a86bf465 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes16 (void) +{ + int16_t out_int16_t; + int16x4_t arg0_int16x4_t; + + out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c new file mode 100644 index 000000000..8559da7ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes32 (void) +{ + int32_t out_int32_t; + int32x2_t arg0_int32x2_t; + + out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c new file mode 100644 index 000000000..5dc99424f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes64 (void) +{ + int64_t out_int64_t; + int64x1_t arg0_int64x1_t; + + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c new file mode 100644 index 000000000..be6110408 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lanes8 (void) +{ + int8_t out_int8_t; + int8x8_t arg0_int8x8_t; + + out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c new file mode 100644 index 000000000..66f645e32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu16 (void) +{ + uint16_t out_uint16_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c new file mode 100644 index 000000000..b19de8d28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu32 (void) +{ + uint32_t out_uint32_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c new file mode 100644 index 000000000..496a057fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu64 (void) +{ + uint64_t out_uint64_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c new file mode 100644 index 000000000..1affae83a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vget_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_laneu8 (void) +{ + uint8_t out_uint8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c new file mode 100644 index 000000000..81982d438 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowf32 (void) +{ + register float32x2_t out_float32x2_t asm ("d18"); + float32x4_t arg0_float32x4_t; + + out_float32x2_t = vget_low_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c new file mode 100644 index 000000000..395461196 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowp16 (void) +{ + register poly16x4_t out_poly16x4_t asm ("d18"); + poly16x8_t arg0_poly16x8_t; + + out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c new file mode 100644 index 000000000..94cd3a8ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vget_lowp64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x2_t arg0_poly64x2_t; + + out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c new file mode 100644 index 000000000..e4bf2f1d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowp8 (void) +{ + register poly8x8_t out_poly8x8_t asm ("d18"); + poly8x16_t arg0_poly8x16_t; + + out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c new file mode 100644 index 000000000..d2a07c63e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows16 (void) +{ + register int16x4_t out_int16x4_t asm ("d18"); + int16x8_t arg0_int16x8_t; + + out_int16x4_t = vget_low_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c new file mode 100644 index 000000000..4278e2bcb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows32 (void) +{ + register int32x2_t out_int32x2_t asm ("d18"); + int32x4_t arg0_int32x4_t; + + out_int32x2_t = vget_low_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c new file mode 100644 index 000000000..53d26e7e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lows64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows64 (void) +{ + int64x1_t out_int64x1_t; + int64x2_t arg0_int64x2_t; + + out_int64x1_t = vget_low_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c new file mode 100644 index 000000000..a4ad63371 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lows8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lows8 (void) +{ + register int8x8_t out_int8x8_t asm ("d18"); + int8x16_t arg0_int8x16_t; + + out_int8x8_t = vget_low_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c new file mode 100644 index 000000000..c9e0a51a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu16 (void) +{ + register uint16x4_t out_uint16x4_t asm ("d18"); + uint16x8_t arg0_uint16x8_t; + + out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c new file mode 100644 index 000000000..841a619cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu32 (void) +{ + register uint32x2_t out_uint32x2_t asm ("d18"); + uint32x4_t arg0_uint32x4_t; + + out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c new file mode 100644 index 000000000..ab2b42c2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c @@ -0,0 +1,19 @@ +/* Test the `vget_lowu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c new file mode 100644 index 000000000..fd2537bbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c @@ -0,0 +1,20 @@ +/* Test the `vget_lowu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vget_lowu8 (void) +{ + register uint8x8_t out_uint8x8_t asm ("d18"); + uint8x16_t arg0_uint8x16_t; + + out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c new file mode 100644 index 000000000..2bd30cd1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c new file mode 100644 index 000000000..04bbf03bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c new file mode 100644 index 000000000..86c3db518 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c new file mode 100644 index 000000000..75aae10e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c new file mode 100644 index 000000000..c7ec45a2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c new file mode 100644 index 000000000..8668d141b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c new file mode 100644 index 000000000..61344cff5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c @@ -0,0 +1,21 @@ +/* Test the `vhadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c new file mode 100644 index 000000000..03d090292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c @@ -0,0 +1,21 @@ +/* Test the `vhadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c new file mode 100644 index 000000000..90e79daa7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c @@ -0,0 +1,21 @@ +/* Test the `vhadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c new file mode 100644 index 000000000..971778b78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c new file mode 100644 index 000000000..70865fad0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c new file mode 100644 index 000000000..b541b87d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vhaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c new file mode 100644 index 000000000..5647c6297 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c new file mode 100644 index 000000000..44e780e01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c new file mode 100644 index 000000000..8162a1014 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c new file mode 100644 index 000000000..1a84876ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c new file mode 100644 index 000000000..ae52afd29 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c new file mode 100644 index 000000000..ef43a4f3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c new file mode 100644 index 000000000..786c8d389 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c new file mode 100644 index 000000000..4c7e9c8b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c new file mode 100644 index 000000000..c8c1ada08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c new file mode 100644 index 000000000..bf83c7ce0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c new file mode 100644 index 000000000..f224eaf07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c new file mode 100644 index 000000000..fe145a9b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vhsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vhsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c new file mode 100644 index 000000000..fa9cf20f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c new file mode 100644 index 000000000..4e8303825 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c new file mode 100644 index 000000000..2d504c163 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp64 (void) +{ + poly64x2_t out_poly64x2_t; + + out_poly64x2_t = vld1q_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c new file mode 100644 index 000000000..70fb89885 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c new file mode 100644 index 000000000..1fedcf94d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c new file mode 100644 index 000000000..2abd4e447 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c new file mode 100644 index 000000000..4fceee82e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c new file mode 100644 index 000000000..e431a5cf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dups8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c new file mode 100644 index 000000000..6da756774 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c new file mode 100644 index 000000000..8e400bd25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c new file mode 100644 index 000000000..ef0a3828c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c new file mode 100644 index 000000000..b1e540d70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Q_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_dupu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c new file mode 100644 index 000000000..8c7689edb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c new file mode 100644 index 000000000..163c2a7a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c new file mode 100644 index 000000000..d19267a4f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c new file mode 100644 index 000000000..7f7a22eba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c new file mode 100644 index 000000000..0d56492c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c new file mode 100644 index 000000000..3c5869fcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c new file mode 100644 index 000000000..154583b67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c new file mode 100644 index 000000000..a6aa3f804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c new file mode 100644 index 000000000..1653dd31c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c new file mode 100644 index 000000000..034e24d52 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c new file mode 100644 index 000000000..ff92e91fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c new file mode 100644 index 000000000..be338f187 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Q_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c new file mode 100644 index 000000000..d792148d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qf32 (void) +{ + float32x4_t out_float32x4_t; + + out_float32x4_t = vld1q_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c new file mode 100644 index 000000000..84bceb557 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + + out_poly16x8_t = vld1q_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c new file mode 100644 index 000000000..99ef87673 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1Qp64 (void) +{ + poly64x2_t out_poly64x2_t; + + out_poly64x2_t = vld1q_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c new file mode 100644 index 000000000..e756b1bc7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + + out_poly8x16_t = vld1q_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c new file mode 100644 index 000000000..aaa29e982 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs16 (void) +{ + int16x8_t out_int16x8_t; + + out_int16x8_t = vld1q_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c new file mode 100644 index 000000000..14bc4221e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs32 (void) +{ + int32x4_t out_int32x4_t; + + out_int32x4_t = vld1q_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c new file mode 100644 index 000000000..093aee61a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs64 (void) +{ + int64x2_t out_int64x2_t; + + out_int64x2_t = vld1q_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c new file mode 100644 index 000000000..d4fffd0a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qs8 (void) +{ + int8x16_t out_int8x16_t; + + out_int8x16_t = vld1q_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c new file mode 100644 index 000000000..267f7d15b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + + out_uint16x8_t = vld1q_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c new file mode 100644 index 000000000..53ccab0c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + + out_uint32x4_t = vld1q_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c new file mode 100644 index 000000000..56b0dbd3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu64 (void) +{ + uint64x2_t out_uint64x2_t; + + out_uint64x2_t = vld1q_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c new file mode 100644 index 000000000..d68fc89ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + + out_uint8x16_t = vld1q_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c new file mode 100644 index 000000000..6f8435b36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupf32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c new file mode 100644 index 000000000..1287b471b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupp16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c new file mode 100644 index 000000000..f2b05c5d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1_dupp64 (void) +{ + poly64x1_t out_poly64x1_t; + + out_poly64x1_t = vld1_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c new file mode 100644 index 000000000..8fde64553 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupp8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c new file mode 100644 index 000000000..084f89e06 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c new file mode 100644 index 000000000..ba6697a4c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c new file mode 100644 index 000000000..410ee6fcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c new file mode 100644 index 000000000..18b21b527 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dups8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c new file mode 100644 index 000000000..1d893cd3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c new file mode 100644 index 000000000..f64084640 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c new file mode 100644 index 000000000..17be90a0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c new file mode 100644 index 000000000..5811f25fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld1_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_dupu8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c new file mode 100644 index 000000000..6165897ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c new file mode 100644 index 000000000..feecf1baa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c new file mode 100644 index 000000000..cf09f6cd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1_lanep64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c new file mode 100644 index 000000000..0d1729936 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c new file mode 100644 index 000000000..26272410e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c new file mode 100644 index 000000000..39575d456 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c new file mode 100644 index 000000000..1216405bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c new file mode 100644 index 000000000..7c763fd90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c new file mode 100644 index 000000000..9d2c45ed9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c new file mode 100644 index 000000000..3a7f3eec9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c new file mode 100644 index 000000000..b9e5d2042 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c new file mode 100644 index 000000000..7e4835afe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c new file mode 100644 index 000000000..2d90ac559 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c @@ -0,0 +1,19 @@ +/* Test the `vld1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1f32 (void) +{ + float32x2_t out_float32x2_t; + + out_float32x2_t = vld1_f32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c new file mode 100644 index 000000000..62aa89e8a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c @@ -0,0 +1,19 @@ +/* Test the `vld1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1p16 (void) +{ + poly16x4_t out_poly16x4_t; + + out_poly16x4_t = vld1_p16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c new file mode 100644 index 000000000..9f182d441 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c @@ -0,0 +1,19 @@ +/* Test the `vld1p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld1p64 (void) +{ + poly64x1_t out_poly64x1_t; + + out_poly64x1_t = vld1_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c new file mode 100644 index 000000000..60e47c2d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c @@ -0,0 +1,19 @@ +/* Test the `vld1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1p8 (void) +{ + poly8x8_t out_poly8x8_t; + + out_poly8x8_t = vld1_p8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c new file mode 100644 index 000000000..1d4cf525f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c @@ -0,0 +1,19 @@ +/* Test the `vld1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s16 (void) +{ + int16x4_t out_int16x4_t; + + out_int16x4_t = vld1_s16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c new file mode 100644 index 000000000..7af67c383 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c @@ -0,0 +1,19 @@ +/* Test the `vld1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s32 (void) +{ + int32x2_t out_int32x2_t; + + out_int32x2_t = vld1_s32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c new file mode 100644 index 000000000..dadb9de22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c @@ -0,0 +1,19 @@ +/* Test the `vld1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s64 (void) +{ + int64x1_t out_int64x1_t; + + out_int64x1_t = vld1_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c new file mode 100644 index 000000000..c27ebcd06 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c @@ -0,0 +1,19 @@ +/* Test the `vld1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1s8 (void) +{ + int8x8_t out_int8x8_t; + + out_int8x8_t = vld1_s8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c new file mode 100644 index 000000000..f973d6ec5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c @@ -0,0 +1,19 @@ +/* Test the `vld1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u16 (void) +{ + uint16x4_t out_uint16x4_t; + + out_uint16x4_t = vld1_u16 (0); +} + +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c new file mode 100644 index 000000000..4b455b292 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c @@ -0,0 +1,19 @@ +/* Test the `vld1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u32 (void) +{ + uint32x2_t out_uint32x2_t; + + out_uint32x2_t = vld1_u32 (0); +} + +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c new file mode 100644 index 000000000..1504215d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c @@ -0,0 +1,19 @@ +/* Test the `vld1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u64 (void) +{ + uint64x1_t out_uint64x1_t; + + out_uint64x1_t = vld1_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c new file mode 100644 index 000000000..600d03518 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c @@ -0,0 +1,19 @@ +/* Test the `vld1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld1u8 (void) +{ + uint8x8_t out_uint8x8_t; + + out_uint8x8_t = vld1_u8 (0); +} + +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c new file mode 100644 index 000000000..9afbbecf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanef32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4x2_t arg1_float32x4x2_t; + + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c new file mode 100644 index 000000000..e1b85aad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanep16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8x2_t arg1_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c new file mode 100644 index 000000000..467c02b64 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8x2_t arg1_int16x8x2_t; + + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c new file mode 100644 index 000000000..5f9c4a8b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_lanes32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4x2_t arg1_int32x4x2_t; + + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c new file mode 100644 index 000000000..851572917 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8x2_t arg1_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c new file mode 100644 index 000000000..65ec23a6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Q_laneu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4x2_t arg1_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c new file mode 100644 index 000000000..afde42c20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + + out_float32x4x2_t = vld2q_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c new file mode 100644 index 000000000..f74004628 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + + out_poly16x8x2_t = vld2q_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c new file mode 100644 index 000000000..9e4ff25f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + + out_poly8x16x2_t = vld2q_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c new file mode 100644 index 000000000..97c8a2c5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + + out_int16x8x2_t = vld2q_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c new file mode 100644 index 000000000..cd03e17d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + + out_int32x4x2_t = vld2q_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c new file mode 100644 index 000000000..b33a5a8f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + + out_int8x16x2_t = vld2q_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c new file mode 100644 index 000000000..76169af56 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + + out_uint16x8x2_t = vld2q_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c new file mode 100644 index 000000000..347e164bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + + out_uint32x4x2_t = vld2q_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c new file mode 100644 index 000000000..3b738a7ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2Qu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + + out_uint8x16x2_t = vld2q_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c new file mode 100644 index 000000000..54fbd3da9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c new file mode 100644 index 000000000..b5ec4e227 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c new file mode 100644 index 000000000..0531a732d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld2_dupp64 (void) +{ + poly64x1x2_t out_poly64x1x2_t; + + out_poly64x1x2_t = vld2_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c new file mode 100644 index 000000000..2ad81b53a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c new file mode 100644 index 000000000..43b245d3d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c new file mode 100644 index 000000000..51e4fc8e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c new file mode 100644 index 000000000..644db84ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c new file mode 100644 index 000000000..015923392 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dups8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c new file mode 100644 index 000000000..85bbc4681 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c new file mode 100644 index 000000000..3549fde1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c new file mode 100644 index 000000000..a830f8310 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c new file mode 100644 index 000000000..c3763c8f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld2_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_dupu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c new file mode 100644 index 000000000..f60279efd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanef32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2x2_t arg1_float32x2x2_t; + + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c new file mode 100644 index 000000000..0d7f415b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanep16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4x2_t arg1_poly16x4x2_t; + + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c new file mode 100644 index 000000000..8174e7bee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanep8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8x2_t arg1_poly8x8x2_t; + + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c new file mode 100644 index 000000000..5a1eb54bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4x2_t arg1_int16x4x2_t; + + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c new file mode 100644 index 000000000..a663c52ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2x2_t arg1_int32x2x2_t; + + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c new file mode 100644 index 000000000..073ba5417 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_lanes8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8x2_t arg1_int8x8x2_t; + + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c new file mode 100644 index 000000000..7250b562e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4x2_t arg1_uint16x4x2_t; + + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c new file mode 100644 index 000000000..9a46c65d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2x2_t arg1_uint32x2x2_t; + + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c new file mode 100644 index 000000000..ba2007109 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2_laneu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8x2_t arg1_uint8x8x2_t; + + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c new file mode 100644 index 000000000..c790de941 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c @@ -0,0 +1,19 @@ +/* Test the `vld2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2f32 (void) +{ + float32x2x2_t out_float32x2x2_t; + + out_float32x2x2_t = vld2_f32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c new file mode 100644 index 000000000..4c4338cfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c @@ -0,0 +1,19 @@ +/* Test the `vld2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2p16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + + out_poly16x4x2_t = vld2_p16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c new file mode 100644 index 000000000..0a39b37f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c @@ -0,0 +1,19 @@ +/* Test the `vld2p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld2p64 (void) +{ + poly64x1x2_t out_poly64x1x2_t; + + out_poly64x1x2_t = vld2_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c new file mode 100644 index 000000000..d319c22e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c @@ -0,0 +1,19 @@ +/* Test the `vld2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2p8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + + out_poly8x8x2_t = vld2_p8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c new file mode 100644 index 000000000..f725d79de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c @@ -0,0 +1,19 @@ +/* Test the `vld2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s16 (void) +{ + int16x4x2_t out_int16x4x2_t; + + out_int16x4x2_t = vld2_s16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c new file mode 100644 index 000000000..3f417eeee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c @@ -0,0 +1,19 @@ +/* Test the `vld2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s32 (void) +{ + int32x2x2_t out_int32x2x2_t; + + out_int32x2x2_t = vld2_s32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c new file mode 100644 index 000000000..b9900893f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c @@ -0,0 +1,19 @@ +/* Test the `vld2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s64 (void) +{ + int64x1x2_t out_int64x1x2_t; + + out_int64x1x2_t = vld2_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c new file mode 100644 index 000000000..1df9eee6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c @@ -0,0 +1,19 @@ +/* Test the `vld2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2s8 (void) +{ + int8x8x2_t out_int8x8x2_t; + + out_int8x8x2_t = vld2_s8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c new file mode 100644 index 000000000..7440e0c08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c @@ -0,0 +1,19 @@ +/* Test the `vld2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + + out_uint16x4x2_t = vld2_u16 (0); +} + +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c new file mode 100644 index 000000000..940fd7497 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c @@ -0,0 +1,19 @@ +/* Test the `vld2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + + out_uint32x2x2_t = vld2_u32 (0); +} + +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c new file mode 100644 index 000000000..35c046a0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c @@ -0,0 +1,19 @@ +/* Test the `vld2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u64 (void) +{ + uint64x1x2_t out_uint64x1x2_t; + + out_uint64x1x2_t = vld2_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c new file mode 100644 index 000000000..2231e26c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c @@ -0,0 +1,19 @@ +/* Test the `vld2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld2u8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + + out_uint8x8x2_t = vld2_u8 (0); +} + +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c new file mode 100644 index 000000000..6bdc1e14a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanef32 (void) +{ + float32x4x3_t out_float32x4x3_t; + float32x4x3_t arg1_float32x4x3_t; + + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c new file mode 100644 index 000000000..12b3be0ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanep16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + poly16x8x3_t arg1_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c new file mode 100644 index 000000000..8ed21e3d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes16 (void) +{ + int16x8x3_t out_int16x8x3_t; + int16x8x3_t arg1_int16x8x3_t; + + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c new file mode 100644 index 000000000..af0118da0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_lanes32 (void) +{ + int32x4x3_t out_int32x4x3_t; + int32x4x3_t arg1_int32x4x3_t; + + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c new file mode 100644 index 000000000..7880b98e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + uint16x8x3_t arg1_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c new file mode 100644 index 000000000..0b1bce5c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Q_laneu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + uint32x4x3_t arg1_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c new file mode 100644 index 000000000..6f16d9d87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qf32 (void) +{ + float32x4x3_t out_float32x4x3_t; + + out_float32x4x3_t = vld3q_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c new file mode 100644 index 000000000..ff4ef8653 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qp16 (void) +{ + poly16x8x3_t out_poly16x8x3_t; + + out_poly16x8x3_t = vld3q_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c new file mode 100644 index 000000000..a23749378 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qp8 (void) +{ + poly8x16x3_t out_poly8x16x3_t; + + out_poly8x16x3_t = vld3q_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c new file mode 100644 index 000000000..cfa01367f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs16 (void) +{ + int16x8x3_t out_int16x8x3_t; + + out_int16x8x3_t = vld3q_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c new file mode 100644 index 000000000..e1721ef3d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs32 (void) +{ + int32x4x3_t out_int32x4x3_t; + + out_int32x4x3_t = vld3q_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c new file mode 100644 index 000000000..9f762ca6f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qs8 (void) +{ + int8x16x3_t out_int8x16x3_t; + + out_int8x16x3_t = vld3q_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c new file mode 100644 index 000000000..a2308729f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu16 (void) +{ + uint16x8x3_t out_uint16x8x3_t; + + out_uint16x8x3_t = vld3q_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c new file mode 100644 index 000000000..21f20f880 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu32 (void) +{ + uint32x4x3_t out_uint32x4x3_t; + + out_uint32x4x3_t = vld3q_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c new file mode 100644 index 000000000..7cbcc4690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3Qu8 (void) +{ + uint8x16x3_t out_uint8x16x3_t; + + out_uint8x16x3_t = vld3q_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c new file mode 100644 index 000000000..542336971 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupf32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c new file mode 100644 index 000000000..6c08c8343 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupp16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c new file mode 100644 index 000000000..23bf88aa6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld3_dupp64 (void) +{ + poly64x1x3_t out_poly64x1x3_t; + + out_poly64x1x3_t = vld3_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c new file mode 100644 index 000000000..fd4a6603f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupp8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c new file mode 100644 index 000000000..4c11e7ef8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c new file mode 100644 index 000000000..b500c24a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c new file mode 100644 index 000000000..cf11f5c1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c new file mode 100644 index 000000000..4f0c8300d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dups8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c new file mode 100644 index 000000000..57e3597bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c new file mode 100644 index 000000000..e4abde4f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c new file mode 100644 index 000000000..a91712623 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c new file mode 100644 index 000000000..842618785 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld3_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_dupu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c new file mode 100644 index 000000000..ccbe45f00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanef32 (void) +{ + float32x2x3_t out_float32x2x3_t; + float32x2x3_t arg1_float32x2x3_t; + + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c new file mode 100644 index 000000000..94b4ce421 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanep16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + poly16x4x3_t arg1_poly16x4x3_t; + + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c new file mode 100644 index 000000000..12b0786bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanep8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + poly8x8x3_t arg1_poly8x8x3_t; + + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c new file mode 100644 index 000000000..5ab744fc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes16 (void) +{ + int16x4x3_t out_int16x4x3_t; + int16x4x3_t arg1_int16x4x3_t; + + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c new file mode 100644 index 000000000..168f3f363 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes32 (void) +{ + int32x2x3_t out_int32x2x3_t; + int32x2x3_t arg1_int32x2x3_t; + + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c new file mode 100644 index 000000000..9d0d1a4b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_lanes8 (void) +{ + int8x8x3_t out_int8x8x3_t; + int8x8x3_t arg1_int8x8x3_t; + + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c new file mode 100644 index 000000000..baf97a98a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + uint16x4x3_t arg1_uint16x4x3_t; + + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c new file mode 100644 index 000000000..05d7107f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + uint32x2x3_t arg1_uint32x2x3_t; + + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c new file mode 100644 index 000000000..af7556350 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3_laneu8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + uint8x8x3_t arg1_uint8x8x3_t; + + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c new file mode 100644 index 000000000..120f834d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c @@ -0,0 +1,19 @@ +/* Test the `vld3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3f32 (void) +{ + float32x2x3_t out_float32x2x3_t; + + out_float32x2x3_t = vld3_f32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c new file mode 100644 index 000000000..2c47f5e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c @@ -0,0 +1,19 @@ +/* Test the `vld3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3p16 (void) +{ + poly16x4x3_t out_poly16x4x3_t; + + out_poly16x4x3_t = vld3_p16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c new file mode 100644 index 000000000..cc7992892 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c @@ -0,0 +1,19 @@ +/* Test the `vld3p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld3p64 (void) +{ + poly64x1x3_t out_poly64x1x3_t; + + out_poly64x1x3_t = vld3_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c new file mode 100644 index 000000000..77c2462e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c @@ -0,0 +1,19 @@ +/* Test the `vld3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3p8 (void) +{ + poly8x8x3_t out_poly8x8x3_t; + + out_poly8x8x3_t = vld3_p8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c new file mode 100644 index 000000000..355ede8c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c @@ -0,0 +1,19 @@ +/* Test the `vld3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s16 (void) +{ + int16x4x3_t out_int16x4x3_t; + + out_int16x4x3_t = vld3_s16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c new file mode 100644 index 000000000..8d18a8843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c @@ -0,0 +1,19 @@ +/* Test the `vld3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s32 (void) +{ + int32x2x3_t out_int32x2x3_t; + + out_int32x2x3_t = vld3_s32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c new file mode 100644 index 000000000..67bb3568f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c @@ -0,0 +1,19 @@ +/* Test the `vld3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s64 (void) +{ + int64x1x3_t out_int64x1x3_t; + + out_int64x1x3_t = vld3_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c new file mode 100644 index 000000000..1be5d11bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c @@ -0,0 +1,19 @@ +/* Test the `vld3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3s8 (void) +{ + int8x8x3_t out_int8x8x3_t; + + out_int8x8x3_t = vld3_s8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c new file mode 100644 index 000000000..4db18f049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c @@ -0,0 +1,19 @@ +/* Test the `vld3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u16 (void) +{ + uint16x4x3_t out_uint16x4x3_t; + + out_uint16x4x3_t = vld3_u16 (0); +} + +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c new file mode 100644 index 000000000..82c10ff16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c @@ -0,0 +1,19 @@ +/* Test the `vld3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u32 (void) +{ + uint32x2x3_t out_uint32x2x3_t; + + out_uint32x2x3_t = vld3_u32 (0); +} + +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c new file mode 100644 index 000000000..bca1df48f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c @@ -0,0 +1,19 @@ +/* Test the `vld3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u64 (void) +{ + uint64x1x3_t out_uint64x1x3_t; + + out_uint64x1x3_t = vld3_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c new file mode 100644 index 000000000..c8ac20af1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c @@ -0,0 +1,19 @@ +/* Test the `vld3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld3u8 (void) +{ + uint8x8x3_t out_uint8x8x3_t; + + out_uint8x8x3_t = vld3_u8 (0); +} + +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c new file mode 100644 index 000000000..5c2499cdc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanef32 (void) +{ + float32x4x4_t out_float32x4x4_t; + float32x4x4_t arg1_float32x4x4_t; + + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c new file mode 100644 index 000000000..1d2d84e63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanep16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + poly16x8x4_t arg1_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c new file mode 100644 index 000000000..df23d281c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes16 (void) +{ + int16x8x4_t out_int16x8x4_t; + int16x8x4_t arg1_int16x8x4_t; + + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c new file mode 100644 index 000000000..db1daff7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_lanes32 (void) +{ + int32x4x4_t out_int32x4x4_t; + int32x4x4_t arg1_int32x4x4_t; + + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c new file mode 100644 index 000000000..e2da0ea27 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + uint16x8x4_t arg1_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c new file mode 100644 index 000000000..d2960ecfc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Q_laneu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + uint32x4x4_t arg1_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c new file mode 100644 index 000000000..0a6e7e6be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qf32 (void) +{ + float32x4x4_t out_float32x4x4_t; + + out_float32x4x4_t = vld4q_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c new file mode 100644 index 000000000..5d902f531 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qp16 (void) +{ + poly16x8x4_t out_poly16x8x4_t; + + out_poly16x8x4_t = vld4q_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c new file mode 100644 index 000000000..e6d66b048 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qp8 (void) +{ + poly8x16x4_t out_poly8x16x4_t; + + out_poly8x16x4_t = vld4q_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c new file mode 100644 index 000000000..04394215d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs16 (void) +{ + int16x8x4_t out_int16x8x4_t; + + out_int16x8x4_t = vld4q_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c new file mode 100644 index 000000000..4101fa1bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs32 (void) +{ + int32x4x4_t out_int32x4x4_t; + + out_int32x4x4_t = vld4q_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c new file mode 100644 index 000000000..9e74f1e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qs8 (void) +{ + int8x16x4_t out_int8x16x4_t; + + out_int8x16x4_t = vld4q_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c new file mode 100644 index 000000000..6b84331f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu16 (void) +{ + uint16x8x4_t out_uint16x8x4_t; + + out_uint16x8x4_t = vld4q_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c new file mode 100644 index 000000000..55f7e93e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu32 (void) +{ + uint32x4x4_t out_uint32x4x4_t; + + out_uint32x4x4_t = vld4q_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c new file mode 100644 index 000000000..9c766c127 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vld4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4Qu8 (void) +{ + uint8x16x4_t out_uint8x16x4_t; + + out_uint8x16x4_t = vld4q_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c new file mode 100644 index 000000000..5315db2d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupf32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_dup_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c new file mode 100644 index 000000000..7ed8224cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupp16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_dup_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c new file mode 100644 index 000000000..bb15964af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld4_dupp64 (void) +{ + poly64x1x4_t out_poly64x1x4_t; + + out_poly64x1x4_t = vld4_dup_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c new file mode 100644 index 000000000..ca1f8fa98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupp8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_dup_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c new file mode 100644 index 000000000..43dab8f2e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_dup_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c new file mode 100644 index 000000000..183e3e9ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_dup_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c new file mode 100644 index 000000000..f4c50493a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_dup_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c new file mode 100644 index 000000000..3a4684a09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dups8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dups8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_dup_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c new file mode 100644 index 000000000..a436cf092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_dup_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c new file mode 100644 index 000000000..6836abd69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_dup_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c new file mode 100644 index 000000000..244eb6188 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_dup_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c new file mode 100644 index 000000000..33c787517 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c @@ -0,0 +1,19 @@ +/* Test the `vld4_dupu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_dupu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_dup_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c new file mode 100644 index 000000000..0fc0ab5fc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanef32 (void) +{ + float32x2x4_t out_float32x2x4_t; + float32x2x4_t arg1_float32x2x4_t; + + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c new file mode 100644 index 000000000..b7407ade1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanep16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + poly16x4x4_t arg1_poly16x4x4_t; + + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c new file mode 100644 index 000000000..7e084106d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanep8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + poly8x8x4_t arg1_poly8x8x4_t; + + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c new file mode 100644 index 000000000..0dc653c5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes16 (void) +{ + int16x4x4_t out_int16x4x4_t; + int16x4x4_t arg1_int16x4x4_t; + + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c new file mode 100644 index 000000000..a3bdaf234 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes32 (void) +{ + int32x2x4_t out_int32x2x4_t; + int32x2x4_t arg1_int32x2x4_t; + + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c new file mode 100644 index 000000000..8555220fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_lanes8 (void) +{ + int8x8x4_t out_int8x8x4_t; + int8x8x4_t arg1_int8x8x4_t; + + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c new file mode 100644 index 000000000..4a417f744 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + uint16x4x4_t arg1_uint16x4x4_t; + + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c new file mode 100644 index 000000000..c1e013a9f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + uint32x2x4_t arg1_uint32x2x4_t; + + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c new file mode 100644 index 000000000..31dcf8ae6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vld4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4_laneu8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + uint8x8x4_t arg1_uint8x8x4_t; + + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c new file mode 100644 index 000000000..aa755c0f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c @@ -0,0 +1,19 @@ +/* Test the `vld4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4f32 (void) +{ + float32x2x4_t out_float32x2x4_t; + + out_float32x2x4_t = vld4_f32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c new file mode 100644 index 000000000..e0300e8b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c @@ -0,0 +1,19 @@ +/* Test the `vld4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4p16 (void) +{ + poly16x4x4_t out_poly16x4x4_t; + + out_poly16x4x4_t = vld4_p16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c new file mode 100644 index 000000000..b11fb9384 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c @@ -0,0 +1,19 @@ +/* Test the `vld4p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vld4p64 (void) +{ + poly64x1x4_t out_poly64x1x4_t; + + out_poly64x1x4_t = vld4_p64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c new file mode 100644 index 000000000..7fbb29cf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c @@ -0,0 +1,19 @@ +/* Test the `vld4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4p8 (void) +{ + poly8x8x4_t out_poly8x8x4_t; + + out_poly8x8x4_t = vld4_p8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c new file mode 100644 index 000000000..a5ef07b20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c @@ -0,0 +1,19 @@ +/* Test the `vld4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s16 (void) +{ + int16x4x4_t out_int16x4x4_t; + + out_int16x4x4_t = vld4_s16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c new file mode 100644 index 000000000..08b929475 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c @@ -0,0 +1,19 @@ +/* Test the `vld4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s32 (void) +{ + int32x2x4_t out_int32x2x4_t; + + out_int32x2x4_t = vld4_s32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c new file mode 100644 index 000000000..99ea54803 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c @@ -0,0 +1,19 @@ +/* Test the `vld4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s64 (void) +{ + int64x1x4_t out_int64x1x4_t; + + out_int64x1x4_t = vld4_s64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c new file mode 100644 index 000000000..c9574671e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c @@ -0,0 +1,19 @@ +/* Test the `vld4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4s8 (void) +{ + int8x8x4_t out_int8x8x4_t; + + out_int8x8x4_t = vld4_s8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c new file mode 100644 index 000000000..4dea8af02 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c @@ -0,0 +1,19 @@ +/* Test the `vld4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u16 (void) +{ + uint16x4x4_t out_uint16x4x4_t; + + out_uint16x4x4_t = vld4_u16 (0); +} + +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c new file mode 100644 index 000000000..aee222589 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c @@ -0,0 +1,19 @@ +/* Test the `vld4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u32 (void) +{ + uint32x2x4_t out_uint32x2x4_t; + + out_uint32x2x4_t = vld4_u32 (0); +} + +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c new file mode 100644 index 000000000..2e8575406 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c @@ -0,0 +1,19 @@ +/* Test the `vld4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u64 (void) +{ + uint64x1x4_t out_uint64x1x4_t; + + out_uint64x1x4_t = vld4_u64 (0); +} + +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c new file mode 100644 index 000000000..ec1d9f9c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c @@ -0,0 +1,19 @@ +/* Test the `vld4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vld4u8 (void) +{ + uint8x8x4_t out_uint8x8x4_t; + + out_uint8x8x4_t = vld4_u8 (0); +} + +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c new file mode 100644 index 000000000..83a2f44d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c new file mode 100644 index 000000000..c8edb7bd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c new file mode 100644 index 000000000..d40f05ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c new file mode 100644 index 000000000..55fdce62b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c new file mode 100644 index 000000000..587a7f1c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c new file mode 100644 index 000000000..dbbe70cc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c new file mode 100644 index 000000000..f785ac8d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c new file mode 100644 index 000000000..ab8cacc3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c new file mode 100644 index 000000000..047d77b49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c new file mode 100644 index 000000000..43ff8874b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c new file mode 100644 index 000000000..54cec995f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c new file mode 100644 index 000000000..8970ba591 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c new file mode 100644 index 000000000..e7094cdff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c new file mode 100644 index 000000000..4e68c3426 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c @@ -0,0 +1,21 @@ +/* Test the `vmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c new file mode 100644 index 000000000..c1a93c6f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c @@ -0,0 +1,21 @@ +/* Test the `vminQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c new file mode 100644 index 000000000..889bd4175 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c @@ -0,0 +1,21 @@ +/* Test the `vminQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c new file mode 100644 index 000000000..dd92bcc49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c @@ -0,0 +1,21 @@ +/* Test the `vminQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c new file mode 100644 index 000000000..dc62e26d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c @@ -0,0 +1,21 @@ +/* Test the `vminQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c new file mode 100644 index 000000000..8b32ee617 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c @@ -0,0 +1,21 @@ +/* Test the `vminQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c new file mode 100644 index 000000000..bc2bb6a32 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c @@ -0,0 +1,21 @@ +/* Test the `vminQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c new file mode 100644 index 000000000..4f7c5c63d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c @@ -0,0 +1,21 @@ +/* Test the `vminQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c new file mode 100644 index 000000000..4b69eb92f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c @@ -0,0 +1,21 @@ +/* Test the `vminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c new file mode 100644 index 000000000..33d080c73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c @@ -0,0 +1,21 @@ +/* Test the `vmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c new file mode 100644 index 000000000..ba9920272 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c @@ -0,0 +1,21 @@ +/* Test the `vmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c new file mode 100644 index 000000000..956729db5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c @@ -0,0 +1,21 @@ +/* Test the `vmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c new file mode 100644 index 000000000..eba01626f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c @@ -0,0 +1,21 @@ +/* Test the `vminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c new file mode 100644 index 000000000..079c4ca71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c @@ -0,0 +1,21 @@ +/* Test the `vminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c new file mode 100644 index 000000000..0a2241821 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c @@ -0,0 +1,21 @@ +/* Test the `vminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c new file mode 100644 index 000000000..594c1ebdc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c new file mode 100644 index 000000000..151943896 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c new file mode 100644 index 000000000..7ba19cb74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c new file mode 100644 index 000000000..d8885876a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c new file mode 100644 index 000000000..e96e9a7ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c new file mode 100644 index 000000000..3e4057913 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c new file mode 100644 index 000000000..28e0d462d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c new file mode 100644 index 000000000..9b5ecf73b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c new file mode 100644 index 000000000..94481f947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c new file mode 100644 index 000000000..3b1926ab9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c new file mode 100644 index 000000000..336d56967 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c new file mode 100644 index 000000000..339db8763 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c new file mode 100644 index 000000000..579b2921d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c new file mode 100644 index 000000000..f0e5b60e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c new file mode 100644 index 000000000..246df1d8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c new file mode 100644 index 000000000..3108c90b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c new file mode 100644 index 000000000..b87b44872 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlaQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c new file mode 100644 index 000000000..8d68f1c79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c new file mode 100644 index 000000000..a426e1138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c new file mode 100644 index 000000000..998c06bdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c new file mode 100644 index 000000000..9274af803 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c new file mode 100644 index 000000000..17e96cb82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c new file mode 100644 index 000000000..3a707c7d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c new file mode 100644 index 000000000..04f2493f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c new file mode 100644 index 000000000..464c09450 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c new file mode 100644 index 000000000..b2eb2ed11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c new file mode 100644 index 000000000..6f11e99a5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmla_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmla_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c new file mode 100644 index 000000000..8b1ac6a97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c new file mode 100644 index 000000000..61f3c7ba9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c new file mode 100644 index 000000000..d7348de60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c new file mode 100644 index 000000000..93fc8bf55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c new file mode 100644 index 000000000..12103d125 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c new file mode 100644 index 000000000..968aef746 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c new file mode 100644 index 000000000..d4b3e46be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c new file mode 100644 index 000000000..9bec57879 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c new file mode 100644 index 000000000..4fadfe94f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlal_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlal_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c new file mode 100644 index 000000000..a62162000 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c @@ -0,0 +1,22 @@ +/* Test the `vmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c new file mode 100644 index 000000000..e64db5959 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c @@ -0,0 +1,22 @@ +/* Test the `vmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c new file mode 100644 index 000000000..22f4bdbed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c @@ -0,0 +1,22 @@ +/* Test the `vmlals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlals8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c new file mode 100644 index 000000000..874fd87b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c new file mode 100644 index 000000000..593c06b45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c new file mode 100644 index 000000000..efb4312cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlalu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c new file mode 100644 index 000000000..b37272b89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c @@ -0,0 +1,22 @@ +/* Test the `vmlas16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c new file mode 100644 index 000000000..65c2e9af2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c @@ -0,0 +1,22 @@ +/* Test the `vmlas32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c new file mode 100644 index 000000000..fcb1fd38d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c @@ -0,0 +1,22 @@ +/* Test the `vmlas8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlas8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c new file mode 100644 index 000000000..c1dceab97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c @@ -0,0 +1,22 @@ +/* Test the `vmlau16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c new file mode 100644 index 000000000..6acbea572 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c @@ -0,0 +1,22 @@ +/* Test the `vmlau32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c new file mode 100644 index 000000000..9fc36666b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c @@ -0,0 +1,22 @@ +/* Test the `vmlau8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlau8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c new file mode 100644 index 000000000..64ef449a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x2_t arg2_float32x2_t; + + out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c new file mode 100644 index 000000000..3788e7f82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x4_t arg2_int16x4_t; + + out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c new file mode 100644 index 000000000..952638079 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x2_t arg2_int32x2_t; + + out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c new file mode 100644 index 000000000..a176265ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c new file mode 100644 index 000000000..094b9fd17 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c new file mode 100644 index 000000000..292a32874 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32_t arg2_float32_t; + + out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c new file mode 100644 index 000000000..02da0712a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16_t arg2_int16_t; + + out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c new file mode 100644 index 000000000..b09aaec97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32_t arg2_int32_t; + + out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c new file mode 100644 index 000000000..a42471171 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16_t arg2_uint16_t; + + out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c new file mode 100644 index 000000000..b84ff6f6e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32_t arg2_uint32_t; + + out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c new file mode 100644 index 000000000..af2ca68fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + float32x4_t arg2_float32x4_t; + + out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c new file mode 100644 index 000000000..4c83d9f31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + int16x8_t arg2_int16x8_t; + + out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c new file mode 100644 index 000000000..575ae0c39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + int32x4_t arg2_int32x4_t; + + out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c new file mode 100644 index 000000000..227ad9b21 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + int8x16_t arg2_int8x16_t; + + out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c new file mode 100644 index 000000000..9d785da73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + uint16x8_t arg2_uint16x8_t; + + out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c new file mode 100644 index 000000000..55a56a0de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + uint32x4_t arg2_uint32x4_t; + + out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c new file mode 100644 index 000000000..fc589718e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + uint8x16_t arg2_uint8x16_t; + + out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c new file mode 100644 index 000000000..f4b9c306c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c new file mode 100644 index 000000000..827178e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c new file mode 100644 index 000000000..5e226c1db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c new file mode 100644 index 000000000..dbc1e8bba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c new file mode 100644 index 000000000..7e6406ec0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c new file mode 100644 index 000000000..fca965b90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32_t arg2_float32_t; + + out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c new file mode 100644 index 000000000..712cfbb8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c new file mode 100644 index 000000000..6d977ec22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c new file mode 100644 index 000000000..772d3f97c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c new file mode 100644 index 000000000..4f1368d78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmls_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmls_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c new file mode 100644 index 000000000..2f44ee0ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + float32x2_t arg2_float32x2_t; + + out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c new file mode 100644 index 000000000..b36355acf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c new file mode 100644 index 000000000..dfab11895 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c new file mode 100644 index 000000000..aff34beac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c new file mode 100644 index 000000000..c9738747d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c new file mode 100644 index 000000000..22a045515 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c new file mode 100644 index 000000000..83370fdc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c new file mode 100644 index 000000000..232f7fe74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16_t arg2_uint16_t; + + out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c new file mode 100644 index 000000000..b64226659 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsl_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32_t arg2_uint32_t; + + out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c new file mode 100644 index 000000000..6ec259efe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c new file mode 100644 index 000000000..b7dd71427 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c new file mode 100644 index 000000000..ca6960bc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsls8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c new file mode 100644 index 000000000..47cbfb32a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c new file mode 100644 index 000000000..9765e5139 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c new file mode 100644 index 000000000..dcb55162b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlslu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlslu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c new file mode 100644 index 000000000..5655a1584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c @@ -0,0 +1,22 @@ +/* Test the `vmlss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c new file mode 100644 index 000000000..1a467dcd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c @@ -0,0 +1,22 @@ +/* Test the `vmlss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c new file mode 100644 index 000000000..db95bdc47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c @@ -0,0 +1,22 @@ +/* Test the `vmlss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c new file mode 100644 index 000000000..dfb918b6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + uint16x4_t arg2_uint16x4_t; + + out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c new file mode 100644 index 000000000..0afbc089f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + uint32x2_t arg2_uint32x2_t; + + out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c new file mode 100644 index 000000000..4da7a41d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c @@ -0,0 +1,22 @@ +/* Test the `vmlsu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmlsu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c new file mode 100644 index 000000000..751910996 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + + out_float32x4_t = vmovq_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c new file mode 100644 index 000000000..48361e99e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + + out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c new file mode 100644 index 000000000..a3de68fde --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + + out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c new file mode 100644 index 000000000..1cec77735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + + out_int16x8_t = vmovq_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c new file mode 100644 index 000000000..59178b799 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + + out_int32x4_t = vmovq_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c new file mode 100644 index 000000000..35936cbd4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c new file mode 100644 index 000000000..e6883aed5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + + out_int8x16_t = vmovq_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c new file mode 100644 index 000000000..66b459a74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + + out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c new file mode 100644 index 000000000..958bb97f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + + out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c new file mode 100644 index 000000000..e373a1218 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vmovQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c new file mode 100644 index 000000000..53120a8dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vmovQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + + out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c new file mode 100644 index 000000000..589911947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + + out_float32x2_t = vmov_n_f32 (arg0_float32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c new file mode 100644 index 000000000..02c906c10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + + out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c new file mode 100644 index 000000000..afd6b46f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + + out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c new file mode 100644 index 000000000..7691e1f4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + + out_int16x4_t = vmov_n_s16 (arg0_int16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c new file mode 100644 index 000000000..b1454ca29 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + + out_int32x2_t = vmov_n_s32 (arg0_int32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c new file mode 100644 index 000000000..7b0112828 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + + out_int64x1_t = vmov_n_s64 (arg0_int64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c new file mode 100644 index 000000000..46a5dc8f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + + out_int8x8_t = vmov_n_s8 (arg0_int8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c new file mode 100644 index 000000000..00ad860b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + + out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); +} + +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c new file mode 100644 index 000000000..c8424c204 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + + out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); +} + +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c new file mode 100644 index 000000000..b9613e06f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c @@ -0,0 +1,19 @@ +/* Test the `vmov_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c new file mode 100644 index 000000000..38d80bcd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vmov_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmov_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + + out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); +} + +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c new file mode 100644 index 000000000..31d5ef14a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c @@ -0,0 +1,20 @@ +/* Test the `vmovls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vmovl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c new file mode 100644 index 000000000..0d95e2eb9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c @@ -0,0 +1,20 @@ +/* Test the `vmovls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vmovl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c new file mode 100644 index 000000000..b27db8300 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c @@ -0,0 +1,20 @@ +/* Test the `vmovls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vmovl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c new file mode 100644 index 000000000..acca55af2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c new file mode 100644 index 000000000..f1eee8ee0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c new file mode 100644 index 000000000..2bf08e1e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c @@ -0,0 +1,20 @@ +/* Test the `vmovlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovlu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c new file mode 100644 index 000000000..abd648bda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c @@ -0,0 +1,20 @@ +/* Test the `vmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c new file mode 100644 index 000000000..82c1c3714 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c @@ -0,0 +1,20 @@ +/* Test the `vmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c new file mode 100644 index 000000000..091bddc2a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c @@ -0,0 +1,20 @@ +/* Test the `vmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c new file mode 100644 index 000000000..85fca5f57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c new file mode 100644 index 000000000..6bdf0d453 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c new file mode 100644 index 000000000..41019fb7d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c @@ -0,0 +1,20 @@ +/* Test the `vmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c new file mode 100644 index 000000000..cc4651be0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x2_t arg1_float32x2_t; + + out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c new file mode 100644 index 000000000..e4620490d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c new file mode 100644 index 000000000..0e0e52734 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c new file mode 100644 index 000000000..d8897a599 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c new file mode 100644 index 000000000..f336710cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c new file mode 100644 index 000000000..e37e9ae40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32_t arg1_float32_t; + + out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c new file mode 100644 index 000000000..ff81b43ee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c new file mode 100644 index 000000000..714bef43a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c new file mode 100644 index 000000000..ef05b9378 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16_t arg1_uint16_t; + + out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c new file mode 100644 index 000000000..2af6d757a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32_t arg1_uint32_t; + + out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c new file mode 100644 index 000000000..3e9ceb056 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c new file mode 100644 index 000000000..fe19f13da --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c new file mode 100644 index 000000000..5d4ac7b1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c new file mode 100644 index 000000000..3f8027270 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c new file mode 100644 index 000000000..8e49dbcf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c new file mode 100644 index 000000000..e73bc6dd0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c new file mode 100644 index 000000000..d041a0d8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c new file mode 100644 index 000000000..75b3c67d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c @@ -0,0 +1,21 @@ +/* Test the `vmulQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c new file mode 100644 index 000000000..967117975 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c new file mode 100644 index 000000000..b1a089274 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c new file mode 100644 index 000000000..dce5e9a94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c new file mode 100644 index 000000000..d73a2514d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c new file mode 100644 index 000000000..c77268bca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c new file mode 100644 index 000000000..8f7522402 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32_t arg1_float32_t; + + out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c new file mode 100644 index 000000000..cf24912d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c new file mode 100644 index 000000000..9c0a35e53 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c new file mode 100644 index 000000000..5d2c60b48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c new file mode 100644 index 000000000..9957837e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmul_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmul_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c new file mode 100644 index 000000000..7081b2f07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c @@ -0,0 +1,21 @@ +/* Test the `vmulf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c new file mode 100644 index 000000000..4467bca7e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c new file mode 100644 index 000000000..db1655faa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c new file mode 100644 index 000000000..c723df2ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_laneu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c new file mode 100644 index 000000000..adea5cc3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_laneu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c new file mode 100644 index 000000000..9de27deb9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c new file mode 100644 index 000000000..0fe16d16f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c new file mode 100644 index 000000000..b3e9c1932 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vmull_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16_t arg1_uint16_t; + + out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c new file mode 100644 index 000000000..6cf18d24a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vmull_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmull_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32_t arg1_uint32_t; + + out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c new file mode 100644 index 000000000..72c288392 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c @@ -0,0 +1,21 @@ +/* Test the `vmullp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullp8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c new file mode 100644 index 000000000..cb7327886 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c @@ -0,0 +1,21 @@ +/* Test the `vmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c new file mode 100644 index 000000000..816f3abc0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c @@ -0,0 +1,21 @@ +/* Test the `vmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c new file mode 100644 index 000000000..4c0d2b4aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c @@ -0,0 +1,21 @@ +/* Test the `vmulls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c new file mode 100644 index 000000000..8dad8be65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c @@ -0,0 +1,21 @@ +/* Test the `vmullu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c new file mode 100644 index 000000000..6010fa92c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c @@ -0,0 +1,21 @@ +/* Test the `vmullu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c new file mode 100644 index 000000000..05eb05ac3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c @@ -0,0 +1,21 @@ +/* Test the `vmullu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmullu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c new file mode 100644 index 000000000..3a9857271 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c @@ -0,0 +1,21 @@ +/* Test the `vmulp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c new file mode 100644 index 000000000..b2ac4c8c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c @@ -0,0 +1,21 @@ +/* Test the `vmuls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c new file mode 100644 index 000000000..7cac98d82 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c @@ -0,0 +1,21 @@ +/* Test the `vmuls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c new file mode 100644 index 000000000..08fd311ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c @@ -0,0 +1,21 @@ +/* Test the `vmuls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmuls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c new file mode 100644 index 000000000..141d72fbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c @@ -0,0 +1,21 @@ +/* Test the `vmulu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c new file mode 100644 index 000000000..5c36ffb9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c @@ -0,0 +1,21 @@ +/* Test the `vmulu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c new file mode 100644 index 000000000..51d4a1708 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c @@ -0,0 +1,21 @@ +/* Test the `vmulu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmulu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c new file mode 100644 index 000000000..47d50b64f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c new file mode 100644 index 000000000..e60488447 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c new file mode 100644 index 000000000..ccad86944 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c new file mode 100644 index 000000000..164907c7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c new file mode 100644 index 000000000..ce18a4907 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c new file mode 100644 index 000000000..34795c776 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c new file mode 100644 index 000000000..d93aa36b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c new file mode 100644 index 000000000..46e3cf910 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnp8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c new file mode 100644 index 000000000..8464b2b95 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c @@ -0,0 +1,20 @@ +/* Test the `vmvns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vmvn_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c new file mode 100644 index 000000000..7a4dd9a79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c @@ -0,0 +1,20 @@ +/* Test the `vmvns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vmvn_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c new file mode 100644 index 000000000..c09872092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c @@ -0,0 +1,20 @@ +/* Test the `vmvns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vmvn_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c new file mode 100644 index 000000000..ab600a0a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c new file mode 100644 index 000000000..df2bd4b5a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c new file mode 100644 index 000000000..729ab71c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c @@ -0,0 +1,20 @@ +/* Test the `vmvnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vmvnu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c new file mode 100644 index 000000000..c1e116913 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c @@ -0,0 +1,20 @@ +/* Test the `vnegQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vnegq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c new file mode 100644 index 000000000..c8b149789 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c new file mode 100644 index 000000000..e8b3e925c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c new file mode 100644 index 000000000..4e8e80d31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c @@ -0,0 +1,20 @@ +/* Test the `vnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c new file mode 100644 index 000000000..82e95399f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c @@ -0,0 +1,20 @@ +/* Test the `vnegf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vneg_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c new file mode 100644 index 000000000..ff2315180 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c @@ -0,0 +1,20 @@ +/* Test the `vnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c new file mode 100644 index 000000000..82108678e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c @@ -0,0 +1,20 @@ +/* Test the `vnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c new file mode 100644 index 000000000..952e34010 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c @@ -0,0 +1,20 @@ +/* Test the `vnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c new file mode 100644 index 000000000..519da3ccc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c @@ -0,0 +1,21 @@ +/* Test the `vornQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c new file mode 100644 index 000000000..cec659911 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c @@ -0,0 +1,21 @@ +/* Test the `vornQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c new file mode 100644 index 000000000..05166ba4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c @@ -0,0 +1,21 @@ +/* Test the `vornQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c new file mode 100644 index 000000000..99982aefd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c @@ -0,0 +1,21 @@ +/* Test the `vornQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c new file mode 100644 index 000000000..761e72d7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c @@ -0,0 +1,21 @@ +/* Test the `vornQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c new file mode 100644 index 000000000..18a968539 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c @@ -0,0 +1,21 @@ +/* Test the `vornQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c new file mode 100644 index 000000000..84c9f895d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c @@ -0,0 +1,21 @@ +/* Test the `vornQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c new file mode 100644 index 000000000..ffe6766d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c @@ -0,0 +1,21 @@ +/* Test the `vornQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c new file mode 100644 index 000000000..b860142dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c @@ -0,0 +1,21 @@ +/* Test the `vorns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c new file mode 100644 index 000000000..826e0d288 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c @@ -0,0 +1,21 @@ +/* Test the `vorns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c new file mode 100644 index 000000000..d7b8e60d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c @@ -0,0 +1,20 @@ +/* Test the `vorns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c new file mode 100644 index 000000000..c71a6bb0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c @@ -0,0 +1,21 @@ +/* Test the `vorns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c new file mode 100644 index 000000000..d4983eebf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c @@ -0,0 +1,21 @@ +/* Test the `vornu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c new file mode 100644 index 000000000..aba68841a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c @@ -0,0 +1,21 @@ +/* Test the `vornu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c new file mode 100644 index 000000000..6fb3a9502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c @@ -0,0 +1,20 @@ +/* Test the `vornu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c new file mode 100644 index 000000000..6fdb7331c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c @@ -0,0 +1,21 @@ +/* Test the `vornu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vornu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c new file mode 100644 index 000000000..20ae7342e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c new file mode 100644 index 000000000..ba42dccd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c new file mode 100644 index 000000000..f46e7c16e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c new file mode 100644 index 000000000..d58607c84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c @@ -0,0 +1,21 @@ +/* Test the `vorrQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c new file mode 100644 index 000000000..ce29c4ad7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c new file mode 100644 index 000000000..8b1a64845 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c new file mode 100644 index 000000000..55cf57ae5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c new file mode 100644 index 000000000..7be85fc43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c @@ -0,0 +1,21 @@ +/* Test the `vorrQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c new file mode 100644 index 000000000..8e942cc1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c @@ -0,0 +1,21 @@ +/* Test the `vorrs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c new file mode 100644 index 000000000..f940a6530 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c @@ -0,0 +1,21 @@ +/* Test the `vorrs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c new file mode 100644 index 000000000..a1c7e5ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c @@ -0,0 +1,20 @@ +/* Test the `vorrs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c new file mode 100644 index 000000000..2d6b70cbe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c @@ -0,0 +1,21 @@ +/* Test the `vorrs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorrs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c new file mode 100644 index 000000000..5d50d7aad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c @@ -0,0 +1,21 @@ +/* Test the `vorru16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c new file mode 100644 index 000000000..60c847649 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c @@ -0,0 +1,21 @@ +/* Test the `vorru32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c new file mode 100644 index 000000000..1991b0215 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c @@ -0,0 +1,20 @@ +/* Test the `vorru64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c new file mode 100644 index 000000000..e47d465e5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c @@ -0,0 +1,21 @@ +/* Test the `vorru8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vorru8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c new file mode 100644 index 000000000..35dcdbbad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x8_t arg1_int16x8_t; + + out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c new file mode 100644 index 000000000..a82551a28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x4_t arg1_int32x4_t; + + out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c new file mode 100644 index 000000000..182ea46c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQs8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x16_t arg1_int8x16_t; + + out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c new file mode 100644 index 000000000..c9f7833d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x8_t arg1_uint16x8_t; + + out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c new file mode 100644 index 000000000..80cf323ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x4_t arg1_uint32x4_t; + + out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c new file mode 100644 index 000000000..8e1dac223 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c new file mode 100644 index 000000000..88c3cb179 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c @@ -0,0 +1,21 @@ +/* Test the `vpadals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals16 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int16x4_t arg1_int16x4_t; + + out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c new file mode 100644 index 000000000..95897f5cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c @@ -0,0 +1,21 @@ +/* Test the `vpadals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals32 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int32x2_t arg1_int32x2_t; + + out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c new file mode 100644 index 000000000..3cc18459d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c @@ -0,0 +1,21 @@ +/* Test the `vpadals8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadals8 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int8x8_t arg1_int8x8_t; + + out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c new file mode 100644 index 000000000..280e4d611 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c new file mode 100644 index 000000000..1792b43d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c new file mode 100644 index 000000000..f3fb6b031 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c @@ -0,0 +1,21 @@ +/* Test the `vpadalu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadalu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c new file mode 100644 index 000000000..f08c8506a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c @@ -0,0 +1,21 @@ +/* Test the `vpaddf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c new file mode 100644 index 000000000..b3fc9aa13 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c new file mode 100644 index 000000000..00399e804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c new file mode 100644 index 000000000..09191ab3f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQs8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c new file mode 100644 index 000000000..d65754b0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c new file mode 100644 index 000000000..b93bfd3f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c new file mode 100644 index 000000000..15f8a18a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlQu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c new file mode 100644 index 000000000..57d93b50d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c new file mode 100644 index 000000000..5abb48994 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c new file mode 100644 index 000000000..0107bfa1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddls8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c new file mode 100644 index 000000000..01c1fac9e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c new file mode 100644 index 000000000..6c47b0582 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c new file mode 100644 index 000000000..47fbc738a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c @@ -0,0 +1,20 @@ +/* Test the `vpaddlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddlu8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c new file mode 100644 index 000000000..6d9ad1afd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c @@ -0,0 +1,21 @@ +/* Test the `vpadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c new file mode 100644 index 000000000..36d8aad1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c @@ -0,0 +1,21 @@ +/* Test the `vpadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c new file mode 100644 index 000000000..ea6bcae85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c @@ -0,0 +1,21 @@ +/* Test the `vpadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c new file mode 100644 index 000000000..1a19916e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c new file mode 100644 index 000000000..3bf215c71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c new file mode 100644 index 000000000..e1b6c5987 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vpaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c new file mode 100644 index 000000000..267fc3862 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c new file mode 100644 index 000000000..7476f2462 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c new file mode 100644 index 000000000..d2c3e81f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c new file mode 100644 index 000000000..c15c0b0a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c new file mode 100644 index 000000000..8fbad8694 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c new file mode 100644 index 000000000..2869fd339 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c new file mode 100644 index 000000000..75a29f27b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c @@ -0,0 +1,21 @@ +/* Test the `vpmaxu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmaxu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c new file mode 100644 index 000000000..59836f78f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c @@ -0,0 +1,21 @@ +/* Test the `vpminf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c new file mode 100644 index 000000000..14af72840 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c @@ -0,0 +1,21 @@ +/* Test the `vpmins16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c new file mode 100644 index 000000000..c34afbdff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c @@ -0,0 +1,21 @@ +/* Test the `vpmins32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c new file mode 100644 index 000000000..b0212ff90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c @@ -0,0 +1,21 @@ +/* Test the `vpmins8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpmins8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c new file mode 100644 index 000000000..a9fa87c7e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c @@ -0,0 +1,21 @@ +/* Test the `vpminu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c new file mode 100644 index 000000000..2c2cb75ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c @@ -0,0 +1,21 @@ +/* Test the `vpminu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c new file mode 100644 index 000000000..726fa72fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c @@ -0,0 +1,21 @@ +/* Test the `vpminu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vpminu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c new file mode 100644 index 000000000..75cbc0a2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c new file mode 100644 index 000000000..12978d383 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c new file mode 100644 index 000000000..55f9037f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c new file mode 100644 index 000000000..7323fe22a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c new file mode 100644 index 000000000..f6c3d1fdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c new file mode 100644 index 000000000..2801f4ffc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c new file mode 100644 index 000000000..3567a8ced --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c new file mode 100644 index 000000000..04d8fe750 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c new file mode 100644 index 000000000..1ab2c5ab6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c new file mode 100644 index 000000000..16a0de031 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c new file mode 100644 index 000000000..d27b4bce3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c new file mode 100644 index 000000000..e4dc0b90d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c new file mode 100644 index 000000000..ed3dc442a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c new file mode 100644 index 000000000..54bd77781 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c new file mode 100644 index 000000000..47dc81e8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c new file mode 100644 index 000000000..4bd258949 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c new file mode 100644 index 000000000..b150120eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c new file mode 100644 index 000000000..f38f38396 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c new file mode 100644 index 000000000..0c2da6d42 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c new file mode 100644 index 000000000..e2e515577 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c new file mode 100644 index 000000000..c0c456c34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c new file mode 100644 index 000000000..275150c86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c new file mode 100644 index 000000000..6e67b57d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c new file mode 100644 index 000000000..a81c9eaf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c new file mode 100644 index 000000000..2c2a7bfcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c new file mode 100644 index 000000000..65dd695fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c new file mode 100644 index 000000000..3757279e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c new file mode 100644 index 000000000..01565bba5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vqRshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c new file mode 100644 index 000000000..ff5902f6c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c new file mode 100644 index 000000000..7a01d6b7a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c new file mode 100644 index 000000000..ddb866280 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c new file mode 100644 index 000000000..5147ac90f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c new file mode 100644 index 000000000..8d682946b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c new file mode 100644 index 000000000..7f7eacba8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c new file mode 100644 index 000000000..547ffd1b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c new file mode 100644 index 000000000..a8f7904a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c new file mode 100644 index 000000000..fde62bcbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqRshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqRshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c new file mode 100644 index 000000000..a31b5cb51 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c new file mode 100644 index 000000000..3ef17b938 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c new file mode 100644 index 000000000..e4ddbb666 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqabsQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabsQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c new file mode 100644 index 000000000..9bcab766b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c @@ -0,0 +1,20 @@ +/* Test the `vqabss16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqabs_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c new file mode 100644 index 000000000..20ecb7eea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c @@ -0,0 +1,20 @@ +/* Test the `vqabss32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqabs_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c new file mode 100644 index 000000000..e4ee27ce6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c @@ -0,0 +1,20 @@ +/* Test the `vqabss8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqabss8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqabs_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c new file mode 100644 index 000000000..d5e1fc289 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c new file mode 100644 index 000000000..f408a3e04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c new file mode 100644 index 000000000..8f1a1a8b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c new file mode 100644 index 000000000..e94dc13d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c new file mode 100644 index 000000000..84f567748 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c new file mode 100644 index 000000000..5055627d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c new file mode 100644 index 000000000..cc3da0faa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c new file mode 100644 index 000000000..d64daf408 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c new file mode 100644 index 000000000..4a4df0be8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c @@ -0,0 +1,21 @@ +/* Test the `vqadds16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c new file mode 100644 index 000000000..b1a022fd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c @@ -0,0 +1,21 @@ +/* Test the `vqadds32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c new file mode 100644 index 000000000..48b4a6ebc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c @@ -0,0 +1,21 @@ +/* Test the `vqadds64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c new file mode 100644 index 000000000..3b408bc8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c @@ -0,0 +1,21 @@ +/* Test the `vqadds8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqadds8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c new file mode 100644 index 000000000..b3d720483 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c new file mode 100644 index 000000000..dbe9038a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c new file mode 100644 index 000000000..08230f833 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c new file mode 100644 index 000000000..c465022f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c @@ -0,0 +1,21 @@ +/* Test the `vqaddu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqaddu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c new file mode 100644 index 000000000..d2567c092 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c new file mode 100644 index 000000000..7a9cfe8bc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c new file mode 100644 index 000000000..43a096265 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c new file mode 100644 index 000000000..2031a60db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlal_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlal_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c new file mode 100644 index 000000000..6391a7988 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlals16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlals16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c new file mode 100644 index 000000000..e7ff0d849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlals32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlals32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c new file mode 100644 index 000000000..aa32c490b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c new file mode 100644 index 000000000..c88b81a5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c new file mode 100644 index 000000000..3981f508b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16_t arg2_int16_t; + + out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c new file mode 100644 index 000000000..36c200be8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsl_ns32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32_t arg2_int32_t; + + out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c new file mode 100644 index 000000000..06aeb8e14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsls16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + int16x4_t arg2_int16x4_t; + + out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c new file mode 100644 index 000000000..fac2fb654 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c @@ -0,0 +1,22 @@ +/* Test the `vqdmlsls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmlsls32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + int32x2_t arg2_int32x2_t; + + out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c new file mode 100644 index 000000000..70ee8a3f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x4_t arg1_int16x4_t; + + out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c new file mode 100644 index 000000000..ea74a9172 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x2_t arg1_int32x2_t; + + out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c new file mode 100644 index 000000000..10009f0d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16_t arg1_int16_t; + + out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c new file mode 100644 index 000000000..1884c9528 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32_t arg1_int32_t; + + out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c new file mode 100644 index 000000000..c9cacfc1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c new file mode 100644 index 000000000..ff6eb74e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c new file mode 100644 index 000000000..5b8e4c54e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c new file mode 100644 index 000000000..507bde891 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c new file mode 100644 index 000000000..e16030c2a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c new file mode 100644 index 000000000..be38f92ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulh_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulh_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c new file mode 100644 index 000000000..ef591cba6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c new file mode 100644 index 000000000..cb51f4be9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulhs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulhs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c new file mode 100644 index 000000000..f9476a2f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c new file mode 100644 index 000000000..2d5ee0064 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_lanes32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c new file mode 100644 index 000000000..1e980f1ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16_t arg1_int16_t; + + out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c new file mode 100644 index 000000000..947aa9635 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmull_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmull_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32_t arg1_int32_t; + + out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c new file mode 100644 index 000000000..72ba7c2ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c new file mode 100644 index 000000000..6a6b2e2d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c @@ -0,0 +1,21 @@ +/* Test the `vqdmulls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqdmulls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c new file mode 100644 index 000000000..8807b5909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c new file mode 100644 index 000000000..a921575e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c new file mode 100644 index 000000000..3c5285b11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c new file mode 100644 index 000000000..ce74646fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c new file mode 100644 index 000000000..74e1b8a08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c new file mode 100644 index 000000000..2e312505b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c new file mode 100644 index 000000000..845af1fa9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c new file mode 100644 index 000000000..6fa8d97a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c new file mode 100644 index 000000000..cb9b462b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c @@ -0,0 +1,20 @@ +/* Test the `vqmovuns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqmovuns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); +} + +/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c new file mode 100644 index 000000000..c5f523858 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c new file mode 100644 index 000000000..cc32b2138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c new file mode 100644 index 000000000..755847d0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c @@ -0,0 +1,20 @@ +/* Test the `vqnegQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c new file mode 100644 index 000000000..a05a1fc8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqneg_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c new file mode 100644 index 000000000..30c43ef5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqneg_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c new file mode 100644 index 000000000..d9f23ad83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c @@ -0,0 +1,20 @@ +/* Test the `vqnegs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqnegs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqneg_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c new file mode 100644 index 000000000..1383779fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c new file mode 100644 index 000000000..acafc1c28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c new file mode 100644 index 000000000..ec90a8866 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c new file mode 100644 index 000000000..e2a25e93d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c new file mode 100644 index 000000000..b01497d40 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c new file mode 100644 index 000000000..613d3dc66 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c new file mode 100644 index 000000000..1d9bea8b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c new file mode 100644 index 000000000..1f0e739b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c new file mode 100644 index 000000000..80f3644a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c new file mode 100644 index 000000000..6c5bd1606 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c new file mode 100644 index 000000000..6819d8286 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c new file mode 100644 index 000000000..27c5c1d26 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c new file mode 100644 index 000000000..163e02def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c new file mode 100644 index 000000000..b6f46d096 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c new file mode 100644 index 000000000..15ecce049 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c new file mode 100644 index 000000000..058095b36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c new file mode 100644 index 000000000..de81ba00e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c new file mode 100644 index 000000000..fac6fdb49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c new file mode 100644 index 000000000..0860a4463 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c new file mode 100644 index 000000000..4e49ad352 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c new file mode 100644 index 000000000..483aa8179 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c new file mode 100644 index 000000000..ad09efda2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c new file mode 100644 index 000000000..9abc96025 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c new file mode 100644 index 000000000..d02d6f7c8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vqshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c new file mode 100644 index 000000000..cf288a078 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c @@ -0,0 +1,21 @@ +/* Test the `vqshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c new file mode 100644 index 000000000..39e38bfc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c @@ -0,0 +1,21 @@ +/* Test the `vqshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c new file mode 100644 index 000000000..6057b3589 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c @@ -0,0 +1,21 @@ +/* Test the `vqshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c new file mode 100644 index 000000000..4d3332fd6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c @@ -0,0 +1,21 @@ +/* Test the `vqshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c new file mode 100644 index 000000000..cbae9aaec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c new file mode 100644 index 000000000..89ba48a23 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c new file mode 100644 index 000000000..df91fa9b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c new file mode 100644 index 000000000..f7ea9231b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vqshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c new file mode 100644 index 000000000..26feb6474 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c new file mode 100644 index 000000000..70a156d6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c new file mode 100644 index 000000000..bed332d60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c new file mode 100644 index 000000000..96e434752 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshluQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshluQ_ns8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c new file mode 100644 index 000000000..2ec926ee2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c new file mode 100644 index 000000000..b9c156ad0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c new file mode 100644 index 000000000..5003573d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c new file mode 100644 index 000000000..649588e97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vqshlu_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshlu_ns8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c new file mode 100644 index 000000000..4a0d5095b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c new file mode 100644 index 000000000..e9a10f6d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c new file mode 100644 index 000000000..32e9aef2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c new file mode 100644 index 000000000..6582d8fea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c new file mode 100644 index 000000000..39eef07f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c new file mode 100644 index 000000000..b479526ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c new file mode 100644 index 000000000..94d6b60e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x8_t arg0_int16x8_t; + + out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c new file mode 100644 index 000000000..9d04d51a5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x4_t arg0_int32x4_t; + + out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c new file mode 100644 index 000000000..37085e97c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vqshrun_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqshrun_ns64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x2_t arg0_int64x2_t; + + out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c new file mode 100644 index 000000000..72943b2e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c new file mode 100644 index 000000000..be37e9115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c new file mode 100644 index 000000000..019b0a696 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c new file mode 100644 index 000000000..a08c1404d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c new file mode 100644 index 000000000..979f7c173 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c new file mode 100644 index 000000000..b0de08699 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c new file mode 100644 index 000000000..e03c2b236 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c new file mode 100644 index 000000000..a447931a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c new file mode 100644 index 000000000..89a87e5b8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c new file mode 100644 index 000000000..fdc563c19 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c new file mode 100644 index 000000000..f8ba1ed00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c new file mode 100644 index 000000000..c16cb1a9b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c new file mode 100644 index 000000000..51b58df63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c new file mode 100644 index 000000000..799a3e38d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c new file mode 100644 index 000000000..673c8174b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c new file mode 100644 index 000000000..5a1eb44cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vqsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vqsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c new file mode 100644 index 000000000..d35cbd6e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c new file mode 100644 index 000000000..9f0949e0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c new file mode 100644 index 000000000..edd17ee47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c new file mode 100644 index 000000000..d59e810ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c @@ -0,0 +1,20 @@ +/* Test the `vrecpeu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpeu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c new file mode 100644 index 000000000..d3452e96e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c @@ -0,0 +1,21 @@ +/* Test the `vrecpsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c new file mode 100644 index 000000000..c8d885b07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c @@ -0,0 +1,21 @@ +/* Test the `vrecpsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrecpsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c new file mode 100644 index 000000000..91cac4df5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p128 (void) +{ + float32x4_t out_float32x4_t; + poly128_t arg0_poly128_t; + + out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c new file mode 100644 index 000000000..58049ac5b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p16 (void) +{ + float32x4_t out_float32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c new file mode 100644 index 000000000..96909f677 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p64 (void) +{ + float32x4_t out_float32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c new file mode 100644 index 000000000..fc5676001 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_p8 (void) +{ + float32x4_t out_float32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c new file mode 100644 index 000000000..dc2227fe2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s16 (void) +{ + float32x4_t out_float32x4_t; + int16x8_t arg0_int16x8_t; + + out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c new file mode 100644 index 000000000..d0781f467 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s32 (void) +{ + float32x4_t out_float32x4_t; + int32x4_t arg0_int32x4_t; + + out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c new file mode 100644 index 000000000..1528c711e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s64 (void) +{ + float32x4_t out_float32x4_t; + int64x2_t arg0_int64x2_t; + + out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c new file mode 100644 index 000000000..eb3a46bd4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_s8 (void) +{ + float32x4_t out_float32x4_t; + int8x16_t arg0_int8x16_t; + + out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c new file mode 100644 index 000000000..5562dfff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u16 (void) +{ + float32x4_t out_float32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c new file mode 100644 index 000000000..8b43c6693 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u32 (void) +{ + float32x4_t out_float32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c new file mode 100644 index 000000000..71e6a5f9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u64 (void) +{ + float32x4_t out_float32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c new file mode 100644 index 000000000..569316344 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQf32_u8 (void) +{ + float32x4_t out_float32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c new file mode 100644 index 000000000..aa7d2e7e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_f32 (void) +{ + poly128_t out_poly128_t; + float32x4_t arg0_float32x4_t; + + out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c new file mode 100644 index 000000000..94f2e9b4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p16 (void) +{ + poly128_t out_poly128_t; + poly16x8_t arg0_poly16x8_t; + + out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c new file mode 100644 index 000000000..d32007547 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p64 (void) +{ + poly128_t out_poly128_t; + poly64x2_t arg0_poly64x2_t; + + out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c new file mode 100644 index 000000000..112b0c6e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_p8 (void) +{ + poly128_t out_poly128_t; + poly8x16_t arg0_poly8x16_t; + + out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c new file mode 100644 index 000000000..4fa06b238 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s16 (void) +{ + poly128_t out_poly128_t; + int16x8_t arg0_int16x8_t; + + out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c new file mode 100644 index 000000000..5f17cb813 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s32 (void) +{ + poly128_t out_poly128_t; + int32x4_t arg0_int32x4_t; + + out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c new file mode 100644 index 000000000..9b83912b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s64 (void) +{ + poly128_t out_poly128_t; + int64x2_t arg0_int64x2_t; + + out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c new file mode 100644 index 000000000..49e8b74b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_s8 (void) +{ + poly128_t out_poly128_t; + int8x16_t arg0_int8x16_t; + + out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c new file mode 100644 index 000000000..d47429aeb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u16 (void) +{ + poly128_t out_poly128_t; + uint16x8_t arg0_uint16x8_t; + + out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c new file mode 100644 index 000000000..57abf79a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u32 (void) +{ + poly128_t out_poly128_t; + uint32x4_t arg0_uint32x4_t; + + out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c new file mode 100644 index 000000000..4d04daaaa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u64 (void) +{ + poly128_t out_poly128_t; + uint64x2_t arg0_uint64x2_t; + + out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c new file mode 100644 index 000000000..ba07bbc8a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp128_u8 (void) +{ + poly128_t out_poly128_t; + uint8x16_t arg0_uint8x16_t; + + out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c new file mode 100644 index 000000000..b94f8f6ae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_f32 (void) +{ + poly16x8_t out_poly16x8_t; + float32x4_t arg0_float32x4_t; + + out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c new file mode 100644 index 000000000..27d0d0afb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p128 (void) +{ + poly16x8_t out_poly16x8_t; + poly128_t arg0_poly128_t; + + out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c new file mode 100644 index 000000000..a0a3aaff4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p64 (void) +{ + poly16x8_t out_poly16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c new file mode 100644 index 000000000..d284b595c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_p8 (void) +{ + poly16x8_t out_poly16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c new file mode 100644 index 000000000..fedcfa8de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s16 (void) +{ + poly16x8_t out_poly16x8_t; + int16x8_t arg0_int16x8_t; + + out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c new file mode 100644 index 000000000..8c56fee74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s32 (void) +{ + poly16x8_t out_poly16x8_t; + int32x4_t arg0_int32x4_t; + + out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c new file mode 100644 index 000000000..03c391a73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s64 (void) +{ + poly16x8_t out_poly16x8_t; + int64x2_t arg0_int64x2_t; + + out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c new file mode 100644 index 000000000..11b6c915d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_s8 (void) +{ + poly16x8_t out_poly16x8_t; + int8x16_t arg0_int8x16_t; + + out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c new file mode 100644 index 000000000..80ba65f7c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u16 (void) +{ + poly16x8_t out_poly16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c new file mode 100644 index 000000000..f1c9aeb75 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u32 (void) +{ + poly16x8_t out_poly16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c new file mode 100644 index 000000000..c2365d1bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u64 (void) +{ + poly16x8_t out_poly16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c new file mode 100644 index 000000000..8333c2f16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp16_u8 (void) +{ + poly16x8_t out_poly16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c new file mode 100644 index 000000000..9f9b1a4ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_f32 (void) +{ + poly64x2_t out_poly64x2_t; + float32x4_t arg0_float32x4_t; + + out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c new file mode 100644 index 000000000..3f7129513 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p128 (void) +{ + poly64x2_t out_poly64x2_t; + poly128_t arg0_poly128_t; + + out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c new file mode 100644 index 000000000..897b7cd9d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p16 (void) +{ + poly64x2_t out_poly64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c new file mode 100644 index 000000000..772b268bf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_p8 (void) +{ + poly64x2_t out_poly64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c new file mode 100644 index 000000000..29f3f6c1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s16 (void) +{ + poly64x2_t out_poly64x2_t; + int16x8_t arg0_int16x8_t; + + out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c new file mode 100644 index 000000000..fae22f65e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s32 (void) +{ + poly64x2_t out_poly64x2_t; + int32x4_t arg0_int32x4_t; + + out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c new file mode 100644 index 000000000..8769bc8e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s64 (void) +{ + poly64x2_t out_poly64x2_t; + int64x2_t arg0_int64x2_t; + + out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c new file mode 100644 index 000000000..1163cc2b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_s8 (void) +{ + poly64x2_t out_poly64x2_t; + int8x16_t arg0_int8x16_t; + + out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c new file mode 100644 index 000000000..f2b53260e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u16 (void) +{ + poly64x2_t out_poly64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c new file mode 100644 index 000000000..6b6179ba4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u32 (void) +{ + poly64x2_t out_poly64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c new file mode 100644 index 000000000..655ffd4fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u64 (void) +{ + poly64x2_t out_poly64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c new file mode 100644 index 000000000..40b40dd11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp64_u8 (void) +{ + poly64x2_t out_poly64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c new file mode 100644 index 000000000..e27080efd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_f32 (void) +{ + poly8x16_t out_poly8x16_t; + float32x4_t arg0_float32x4_t; + + out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c new file mode 100644 index 000000000..b517a6fdf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p128 (void) +{ + poly8x16_t out_poly8x16_t; + poly128_t arg0_poly128_t; + + out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c new file mode 100644 index 000000000..86dd6a4a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p16 (void) +{ + poly8x16_t out_poly8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c new file mode 100644 index 000000000..9e70b8a07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_p64 (void) +{ + poly8x16_t out_poly8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c new file mode 100644 index 000000000..608e27293 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s16 (void) +{ + poly8x16_t out_poly8x16_t; + int16x8_t arg0_int16x8_t; + + out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c new file mode 100644 index 000000000..7900676d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s32 (void) +{ + poly8x16_t out_poly8x16_t; + int32x4_t arg0_int32x4_t; + + out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c new file mode 100644 index 000000000..27483dcf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s64 (void) +{ + poly8x16_t out_poly8x16_t; + int64x2_t arg0_int64x2_t; + + out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c new file mode 100644 index 000000000..d4be56f6a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_s8 (void) +{ + poly8x16_t out_poly8x16_t; + int8x16_t arg0_int8x16_t; + + out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c new file mode 100644 index 000000000..c00a55fe0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u16 (void) +{ + poly8x16_t out_poly8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c new file mode 100644 index 000000000..e5b580b44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u32 (void) +{ + poly8x16_t out_poly8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c new file mode 100644 index 000000000..5e80ed7d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u64 (void) +{ + poly8x16_t out_poly8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c new file mode 100644 index 000000000..321e8f8dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQp8_u8 (void) +{ + poly8x16_t out_poly8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c new file mode 100644 index 000000000..08d6b6afc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_f32 (void) +{ + int16x8_t out_int16x8_t; + float32x4_t arg0_float32x4_t; + + out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c new file mode 100644 index 000000000..77bfe3882 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p128 (void) +{ + int16x8_t out_int16x8_t; + poly128_t arg0_poly128_t; + + out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c new file mode 100644 index 000000000..1505b725e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p16 (void) +{ + int16x8_t out_int16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c new file mode 100644 index 000000000..41890f32a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p64 (void) +{ + int16x8_t out_int16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c new file mode 100644 index 000000000..48c54f212 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_p8 (void) +{ + int16x8_t out_int16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c new file mode 100644 index 000000000..15f54fa94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s32 (void) +{ + int16x8_t out_int16x8_t; + int32x4_t arg0_int32x4_t; + + out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c new file mode 100644 index 000000000..eb8e53516 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s64 (void) +{ + int16x8_t out_int16x8_t; + int64x2_t arg0_int64x2_t; + + out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c new file mode 100644 index 000000000..f353c9268 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_s8 (void) +{ + int16x8_t out_int16x8_t; + int8x16_t arg0_int8x16_t; + + out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c new file mode 100644 index 000000000..8ea96b7b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u16 (void) +{ + int16x8_t out_int16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c new file mode 100644 index 000000000..ac571b126 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u32 (void) +{ + int16x8_t out_int16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c new file mode 100644 index 000000000..73959abd9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u64 (void) +{ + int16x8_t out_int16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c new file mode 100644 index 000000000..45e85b131 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs16_u8 (void) +{ + int16x8_t out_int16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c new file mode 100644 index 000000000..795db0753 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_f32 (void) +{ + int32x4_t out_int32x4_t; + float32x4_t arg0_float32x4_t; + + out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c new file mode 100644 index 000000000..9a179ae3b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p128 (void) +{ + int32x4_t out_int32x4_t; + poly128_t arg0_poly128_t; + + out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c new file mode 100644 index 000000000..473c12350 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p16 (void) +{ + int32x4_t out_int32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c new file mode 100644 index 000000000..cc7ad95ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p64 (void) +{ + int32x4_t out_int32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c new file mode 100644 index 000000000..819e1d122 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_p8 (void) +{ + int32x4_t out_int32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c new file mode 100644 index 000000000..7d2b5a0b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s16 (void) +{ + int32x4_t out_int32x4_t; + int16x8_t arg0_int16x8_t; + + out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c new file mode 100644 index 000000000..8116033e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s64 (void) +{ + int32x4_t out_int32x4_t; + int64x2_t arg0_int64x2_t; + + out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c new file mode 100644 index 000000000..6786ddbfd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_s8 (void) +{ + int32x4_t out_int32x4_t; + int8x16_t arg0_int8x16_t; + + out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c new file mode 100644 index 000000000..104e22d68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u16 (void) +{ + int32x4_t out_int32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c new file mode 100644 index 000000000..8385fd8a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u32 (void) +{ + int32x4_t out_int32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c new file mode 100644 index 000000000..90b91a74a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u64 (void) +{ + int32x4_t out_int32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c new file mode 100644 index 000000000..60ad32a44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs32_u8 (void) +{ + int32x4_t out_int32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c new file mode 100644 index 000000000..212005fab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_f32 (void) +{ + int64x2_t out_int64x2_t; + float32x4_t arg0_float32x4_t; + + out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c new file mode 100644 index 000000000..adc1b9bbf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p128 (void) +{ + int64x2_t out_int64x2_t; + poly128_t arg0_poly128_t; + + out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c new file mode 100644 index 000000000..0003a1f72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p16 (void) +{ + int64x2_t out_int64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c new file mode 100644 index 000000000..89ab9ccb4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p64 (void) +{ + int64x2_t out_int64x2_t; + poly64x2_t arg0_poly64x2_t; + + out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c new file mode 100644 index 000000000..02d7174b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_p8 (void) +{ + int64x2_t out_int64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c new file mode 100644 index 000000000..26350eeb8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s16 (void) +{ + int64x2_t out_int64x2_t; + int16x8_t arg0_int16x8_t; + + out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c new file mode 100644 index 000000000..471db5cc2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s32 (void) +{ + int64x2_t out_int64x2_t; + int32x4_t arg0_int32x4_t; + + out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c new file mode 100644 index 000000000..903be8ff6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_s8 (void) +{ + int64x2_t out_int64x2_t; + int8x16_t arg0_int8x16_t; + + out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c new file mode 100644 index 000000000..cbb49098f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u16 (void) +{ + int64x2_t out_int64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c new file mode 100644 index 000000000..882cf77bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u32 (void) +{ + int64x2_t out_int64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c new file mode 100644 index 000000000..f9bc43ae4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u64 (void) +{ + int64x2_t out_int64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c new file mode 100644 index 000000000..3af2f0138 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs64_u8 (void) +{ + int64x2_t out_int64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c new file mode 100644 index 000000000..6a31442cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_f32 (void) +{ + int8x16_t out_int8x16_t; + float32x4_t arg0_float32x4_t; + + out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c new file mode 100644 index 000000000..d94090068 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p128 (void) +{ + int8x16_t out_int8x16_t; + poly128_t arg0_poly128_t; + + out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c new file mode 100644 index 000000000..6491c795a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p16 (void) +{ + int8x16_t out_int8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c new file mode 100644 index 000000000..a9adec387 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p64 (void) +{ + int8x16_t out_int8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c new file mode 100644 index 000000000..914321d55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_p8 (void) +{ + int8x16_t out_int8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c new file mode 100644 index 000000000..fee5e2723 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s16 (void) +{ + int8x16_t out_int8x16_t; + int16x8_t arg0_int16x8_t; + + out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c new file mode 100644 index 000000000..2bf941aa5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s32 (void) +{ + int8x16_t out_int8x16_t; + int32x4_t arg0_int32x4_t; + + out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c new file mode 100644 index 000000000..1e6557174 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_s64 (void) +{ + int8x16_t out_int8x16_t; + int64x2_t arg0_int64x2_t; + + out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c new file mode 100644 index 000000000..84b86eaae --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u16 (void) +{ + int8x16_t out_int8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c new file mode 100644 index 000000000..e5f85ccd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u32 (void) +{ + int8x16_t out_int8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c new file mode 100644 index 000000000..9f299b366 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u64 (void) +{ + int8x16_t out_int8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c new file mode 100644 index 000000000..f04a53733 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQs8_u8 (void) +{ + int8x16_t out_int8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c new file mode 100644 index 000000000..cb4a2e502 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_f32 (void) +{ + uint16x8_t out_uint16x8_t; + float32x4_t arg0_float32x4_t; + + out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c new file mode 100644 index 000000000..792609246 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p128 (void) +{ + uint16x8_t out_uint16x8_t; + poly128_t arg0_poly128_t; + + out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c new file mode 100644 index 000000000..5667d60c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p16 (void) +{ + uint16x8_t out_uint16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c new file mode 100644 index 000000000..7a9b538f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p64 (void) +{ + uint16x8_t out_uint16x8_t; + poly64x2_t arg0_poly64x2_t; + + out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c new file mode 100644 index 000000000..d45442d9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_p8 (void) +{ + uint16x8_t out_uint16x8_t; + poly8x16_t arg0_poly8x16_t; + + out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c new file mode 100644 index 000000000..9b6615909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + + out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c new file mode 100644 index 000000000..9a6d0f44a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s32 (void) +{ + uint16x8_t out_uint16x8_t; + int32x4_t arg0_int32x4_t; + + out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c new file mode 100644 index 000000000..c5a5378e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s64 (void) +{ + uint16x8_t out_uint16x8_t; + int64x2_t arg0_int64x2_t; + + out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c new file mode 100644 index 000000000..4ca22dceb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_s8 (void) +{ + uint16x8_t out_uint16x8_t; + int8x16_t arg0_int8x16_t; + + out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c new file mode 100644 index 000000000..516c94957 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u32 (void) +{ + uint16x8_t out_uint16x8_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c new file mode 100644 index 000000000..816da82c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u64 (void) +{ + uint16x8_t out_uint16x8_t; + uint64x2_t arg0_uint64x2_t; + + out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c new file mode 100644 index 000000000..ac5e98fa8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu16_u8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x16_t arg0_uint8x16_t; + + out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c new file mode 100644 index 000000000..7453f24b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_f32 (void) +{ + uint32x4_t out_uint32x4_t; + float32x4_t arg0_float32x4_t; + + out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c new file mode 100644 index 000000000..ce716b0ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p128 (void) +{ + uint32x4_t out_uint32x4_t; + poly128_t arg0_poly128_t; + + out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c new file mode 100644 index 000000000..27989c53c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p16 (void) +{ + uint32x4_t out_uint32x4_t; + poly16x8_t arg0_poly16x8_t; + + out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c new file mode 100644 index 000000000..a8b709e02 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p64 (void) +{ + uint32x4_t out_uint32x4_t; + poly64x2_t arg0_poly64x2_t; + + out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c new file mode 100644 index 000000000..2b3e01843 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_p8 (void) +{ + uint32x4_t out_uint32x4_t; + poly8x16_t arg0_poly8x16_t; + + out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c new file mode 100644 index 000000000..3a6f20f0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s16 (void) +{ + uint32x4_t out_uint32x4_t; + int16x8_t arg0_int16x8_t; + + out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c new file mode 100644 index 000000000..3079729aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + + out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c new file mode 100644 index 000000000..927cd3a60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s64 (void) +{ + uint32x4_t out_uint32x4_t; + int64x2_t arg0_int64x2_t; + + out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c new file mode 100644 index 000000000..5b546ccac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_s8 (void) +{ + uint32x4_t out_uint32x4_t; + int8x16_t arg0_int8x16_t; + + out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c new file mode 100644 index 000000000..055739e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x8_t arg0_uint16x8_t; + + out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c new file mode 100644 index 000000000..ddf51f8ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u64 (void) +{ + uint32x4_t out_uint32x4_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c new file mode 100644 index 000000000..2f860c193 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu32_u8 (void) +{ + uint32x4_t out_uint32x4_t; + uint8x16_t arg0_uint8x16_t; + + out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c new file mode 100644 index 000000000..5224dcf87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_f32 (void) +{ + uint64x2_t out_uint64x2_t; + float32x4_t arg0_float32x4_t; + + out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c new file mode 100644 index 000000000..789973e0a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p128 (void) +{ + uint64x2_t out_uint64x2_t; + poly128_t arg0_poly128_t; + + out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c new file mode 100644 index 000000000..fc592b78d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p16 (void) +{ + uint64x2_t out_uint64x2_t; + poly16x8_t arg0_poly16x8_t; + + out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c new file mode 100644 index 000000000..38071503e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p64 (void) +{ + uint64x2_t out_uint64x2_t; + poly64x2_t arg0_poly64x2_t; + + out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c new file mode 100644 index 000000000..503c44393 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_p8 (void) +{ + uint64x2_t out_uint64x2_t; + poly8x16_t arg0_poly8x16_t; + + out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c new file mode 100644 index 000000000..430694abc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s16 (void) +{ + uint64x2_t out_uint64x2_t; + int16x8_t arg0_int16x8_t; + + out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c new file mode 100644 index 000000000..acfc69e74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s32 (void) +{ + uint64x2_t out_uint64x2_t; + int32x4_t arg0_int32x4_t; + + out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c new file mode 100644 index 000000000..033c6516e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s64 (void) +{ + uint64x2_t out_uint64x2_t; + int64x2_t arg0_int64x2_t; + + out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c new file mode 100644 index 000000000..b6c312fbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_s8 (void) +{ + uint64x2_t out_uint64x2_t; + int8x16_t arg0_int8x16_t; + + out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c new file mode 100644 index 000000000..dbe9d5160 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u16 (void) +{ + uint64x2_t out_uint64x2_t; + uint16x8_t arg0_uint16x8_t; + + out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c new file mode 100644 index 000000000..58b3c67e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x4_t arg0_uint32x4_t; + + out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c new file mode 100644 index 000000000..c20fef185 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu64_u8 (void) +{ + uint64x2_t out_uint64x2_t; + uint8x16_t arg0_uint8x16_t; + + out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c new file mode 100644 index 000000000..f7b470415 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_f32 (void) +{ + uint8x16_t out_uint8x16_t; + float32x4_t arg0_float32x4_t; + + out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c new file mode 100644 index 000000000..54a832cf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p128 (void) +{ + uint8x16_t out_uint8x16_t; + poly128_t arg0_poly128_t; + + out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c new file mode 100644 index 000000000..758f10bea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p16 (void) +{ + uint8x16_t out_uint8x16_t; + poly16x8_t arg0_poly16x8_t; + + out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c new file mode 100644 index 000000000..3336e6c24 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p64 (void) +{ + uint8x16_t out_uint8x16_t; + poly64x2_t arg0_poly64x2_t; + + out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c new file mode 100644 index 000000000..29f2aa19e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_p8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c new file mode 100644 index 000000000..1d79abb9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s16 (void) +{ + uint8x16_t out_uint8x16_t; + int16x8_t arg0_int16x8_t; + + out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c new file mode 100644 index 000000000..9f7c4f2f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s32 (void) +{ + uint8x16_t out_uint8x16_t; + int32x4_t arg0_int32x4_t; + + out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c new file mode 100644 index 000000000..a01fb1d1d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s64 (void) +{ + uint8x16_t out_uint8x16_t; + int64x2_t arg0_int64x2_t; + + out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c new file mode 100644 index 000000000..0d65f31d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_s8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + + out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c new file mode 100644 index 000000000..dd9306192 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u16 (void) +{ + uint8x16_t out_uint8x16_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c new file mode 100644 index 000000000..30f4b4559 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u32 (void) +{ + uint8x16_t out_uint8x16_t; + uint32x4_t arg0_uint32x4_t; + + out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c new file mode 100644 index 000000000..3f04c7192 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretQu8_u64 (void) +{ + uint8x16_t out_uint8x16_t; + uint64x2_t arg0_uint64x2_t; + + out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c new file mode 100644 index 000000000..92ede4949 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p16 (void) +{ + float32x2_t out_float32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c new file mode 100644 index 000000000..e9714658f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p64 (void) +{ + float32x2_t out_float32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c new file mode 100644 index 000000000..ee2e6a92e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_p8 (void) +{ + float32x2_t out_float32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c new file mode 100644 index 000000000..39ec36947 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s16 (void) +{ + float32x2_t out_float32x2_t; + int16x4_t arg0_int16x4_t; + + out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c new file mode 100644 index 000000000..008598f14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s32 (void) +{ + float32x2_t out_float32x2_t; + int32x2_t arg0_int32x2_t; + + out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c new file mode 100644 index 000000000..6a5ede493 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s64 (void) +{ + float32x2_t out_float32x2_t; + int64x1_t arg0_int64x1_t; + + out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c new file mode 100644 index 000000000..cc645e5d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_s8 (void) +{ + float32x2_t out_float32x2_t; + int8x8_t arg0_int8x8_t; + + out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c new file mode 100644 index 000000000..fbb96790f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u16 (void) +{ + float32x2_t out_float32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c new file mode 100644 index 000000000..f87c885c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u32 (void) +{ + float32x2_t out_float32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c new file mode 100644 index 000000000..610f77ad4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u64 (void) +{ + float32x2_t out_float32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c new file mode 100644 index 000000000..bfd81b171 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretf32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretf32_u8 (void) +{ + float32x2_t out_float32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c new file mode 100644 index 000000000..91508a6d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_f32 (void) +{ + poly16x4_t out_poly16x4_t; + float32x2_t arg0_float32x2_t; + + out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c new file mode 100644 index 000000000..4cd6818db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_p64 (void) +{ + poly16x4_t out_poly16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c new file mode 100644 index 000000000..a2f7207ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_p8 (void) +{ + poly16x4_t out_poly16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c new file mode 100644 index 000000000..3f22296cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s16 (void) +{ + poly16x4_t out_poly16x4_t; + int16x4_t arg0_int16x4_t; + + out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c new file mode 100644 index 000000000..393246cca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s32 (void) +{ + poly16x4_t out_poly16x4_t; + int32x2_t arg0_int32x2_t; + + out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c new file mode 100644 index 000000000..f5c99711a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s64 (void) +{ + poly16x4_t out_poly16x4_t; + int64x1_t arg0_int64x1_t; + + out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c new file mode 100644 index 000000000..6cf01b280 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_s8 (void) +{ + poly16x4_t out_poly16x4_t; + int8x8_t arg0_int8x8_t; + + out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c new file mode 100644 index 000000000..4cdeeac44 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u16 (void) +{ + poly16x4_t out_poly16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c new file mode 100644 index 000000000..5b1094097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u32 (void) +{ + poly16x4_t out_poly16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c new file mode 100644 index 000000000..b036ff475 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u64 (void) +{ + poly16x4_t out_poly16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c new file mode 100644 index 000000000..d165cafb4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp16_u8 (void) +{ + poly16x4_t out_poly16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c new file mode 100644 index 000000000..d9ecd6f88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_f32 (void) +{ + poly64x1_t out_poly64x1_t; + float32x2_t arg0_float32x2_t; + + out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c new file mode 100644 index 000000000..db437279b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_p16 (void) +{ + poly64x1_t out_poly64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c new file mode 100644 index 000000000..1fb0131d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_p8 (void) +{ + poly64x1_t out_poly64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c new file mode 100644 index 000000000..528db2d57 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s16 (void) +{ + poly64x1_t out_poly64x1_t; + int16x4_t arg0_int16x4_t; + + out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c new file mode 100644 index 000000000..c6887d7e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s32 (void) +{ + poly64x1_t out_poly64x1_t; + int32x2_t arg0_int32x2_t; + + out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c new file mode 100644 index 000000000..f2b041649 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s64 (void) +{ + poly64x1_t out_poly64x1_t; + int64x1_t arg0_int64x1_t; + + out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c new file mode 100644 index 000000000..1866d19fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_s8 (void) +{ + poly64x1_t out_poly64x1_t; + int8x8_t arg0_int8x8_t; + + out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c new file mode 100644 index 000000000..7903ec26f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u16 (void) +{ + poly64x1_t out_poly64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c new file mode 100644 index 000000000..3d8e9e40f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u32 (void) +{ + poly64x1_t out_poly64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c new file mode 100644 index 000000000..caa0464aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u64 (void) +{ + poly64x1_t out_poly64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c new file mode 100644 index 000000000..47e1dfa5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp64_u8 (void) +{ + poly64x1_t out_poly64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c new file mode 100644 index 000000000..b73599085 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_f32 (void) +{ + poly8x8_t out_poly8x8_t; + float32x2_t arg0_float32x2_t; + + out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c new file mode 100644 index 000000000..28a04a3e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_p16 (void) +{ + poly8x8_t out_poly8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c new file mode 100644 index 000000000..f5eff21ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_p64 (void) +{ + poly8x8_t out_poly8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c new file mode 100644 index 000000000..2a559c8d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s16 (void) +{ + poly8x8_t out_poly8x8_t; + int16x4_t arg0_int16x4_t; + + out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c new file mode 100644 index 000000000..a3c627085 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s32 (void) +{ + poly8x8_t out_poly8x8_t; + int32x2_t arg0_int32x2_t; + + out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c new file mode 100644 index 000000000..1a5cbbbcd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s64 (void) +{ + poly8x8_t out_poly8x8_t; + int64x1_t arg0_int64x1_t; + + out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c new file mode 100644 index 000000000..0f8af3e5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_s8 (void) +{ + poly8x8_t out_poly8x8_t; + int8x8_t arg0_int8x8_t; + + out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c new file mode 100644 index 000000000..f3cdaab48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u16 (void) +{ + poly8x8_t out_poly8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c new file mode 100644 index 000000000..210e063c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u32 (void) +{ + poly8x8_t out_poly8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c new file mode 100644 index 000000000..bf83e5df9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u64 (void) +{ + poly8x8_t out_poly8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c new file mode 100644 index 000000000..17d8d8c87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretp8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretp8_u8 (void) +{ + poly8x8_t out_poly8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c new file mode 100644 index 000000000..380947bcc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_f32 (void) +{ + int16x4_t out_int16x4_t; + float32x2_t arg0_float32x2_t; + + out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c new file mode 100644 index 000000000..3742001b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p16 (void) +{ + int16x4_t out_int16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c new file mode 100644 index 000000000..127865d16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p64 (void) +{ + int16x4_t out_int16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c new file mode 100644 index 000000000..5970dc86c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_p8 (void) +{ + int16x4_t out_int16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c new file mode 100644 index 000000000..bee17e4c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s32 (void) +{ + int16x4_t out_int16x4_t; + int32x2_t arg0_int32x2_t; + + out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c new file mode 100644 index 000000000..4a8feda9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s64 (void) +{ + int16x4_t out_int16x4_t; + int64x1_t arg0_int64x1_t; + + out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c new file mode 100644 index 000000000..e079c6158 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_s8 (void) +{ + int16x4_t out_int16x4_t; + int8x8_t arg0_int8x8_t; + + out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c new file mode 100644 index 000000000..cf86bd4a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u16 (void) +{ + int16x4_t out_int16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c new file mode 100644 index 000000000..853e7ab2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u32 (void) +{ + int16x4_t out_int16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c new file mode 100644 index 000000000..a72786ded --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u64 (void) +{ + int16x4_t out_int16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c new file mode 100644 index 000000000..9c8459e46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets16_u8 (void) +{ + int16x4_t out_int16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c new file mode 100644 index 000000000..73fe251e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_f32 (void) +{ + int32x2_t out_int32x2_t; + float32x2_t arg0_float32x2_t; + + out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c new file mode 100644 index 000000000..36df97c5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p16 (void) +{ + int32x2_t out_int32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c new file mode 100644 index 000000000..f8be30b92 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p64 (void) +{ + int32x2_t out_int32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c new file mode 100644 index 000000000..54e9dee78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_p8 (void) +{ + int32x2_t out_int32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c new file mode 100644 index 000000000..f5e3fb6fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s16 (void) +{ + int32x2_t out_int32x2_t; + int16x4_t arg0_int16x4_t; + + out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c new file mode 100644 index 000000000..f1430843f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s64 (void) +{ + int32x2_t out_int32x2_t; + int64x1_t arg0_int64x1_t; + + out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c new file mode 100644 index 000000000..a336577d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_s8 (void) +{ + int32x2_t out_int32x2_t; + int8x8_t arg0_int8x8_t; + + out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c new file mode 100644 index 000000000..2f078613e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u16 (void) +{ + int32x2_t out_int32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c new file mode 100644 index 000000000..4087e9c78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u32 (void) +{ + int32x2_t out_int32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c new file mode 100644 index 000000000..826bb8efb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u64 (void) +{ + int32x2_t out_int32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c new file mode 100644 index 000000000..31589a8a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets32_u8 (void) +{ + int32x2_t out_int32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c new file mode 100644 index 000000000..0096e368a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_f32 (void) +{ + int64x1_t out_int64x1_t; + float32x2_t arg0_float32x2_t; + + out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c new file mode 100644 index 000000000..bdbe4302f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p16 (void) +{ + int64x1_t out_int64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c new file mode 100644 index 000000000..5f7c17bd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p64 (void) +{ + int64x1_t out_int64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c new file mode 100644 index 000000000..76da59f39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_p8 (void) +{ + int64x1_t out_int64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c new file mode 100644 index 000000000..0f978f390 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s16 (void) +{ + int64x1_t out_int64x1_t; + int16x4_t arg0_int16x4_t; + + out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c new file mode 100644 index 000000000..aefa689a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s32 (void) +{ + int64x1_t out_int64x1_t; + int32x2_t arg0_int32x2_t; + + out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c new file mode 100644 index 000000000..a7e0adad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_s8 (void) +{ + int64x1_t out_int64x1_t; + int8x8_t arg0_int8x8_t; + + out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c new file mode 100644 index 000000000..110818567 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u16 (void) +{ + int64x1_t out_int64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c new file mode 100644 index 000000000..978a6e480 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u32 (void) +{ + int64x1_t out_int64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c new file mode 100644 index 000000000..0546f26dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u64 (void) +{ + int64x1_t out_int64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c new file mode 100644 index 000000000..601b5988d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets64_u8 (void) +{ + int64x1_t out_int64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c new file mode 100644 index 000000000..05d921d7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_f32 (void) +{ + int8x8_t out_int8x8_t; + float32x2_t arg0_float32x2_t; + + out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c new file mode 100644 index 000000000..38e812a16 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p16 (void) +{ + int8x8_t out_int8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c new file mode 100644 index 000000000..8345963ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p64 (void) +{ + int8x8_t out_int8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c new file mode 100644 index 000000000..402484411 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_p8 (void) +{ + int8x8_t out_int8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c new file mode 100644 index 000000000..df368e370 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s16 (void) +{ + int8x8_t out_int8x8_t; + int16x4_t arg0_int16x4_t; + + out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c new file mode 100644 index 000000000..caefc38dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s32 (void) +{ + int8x8_t out_int8x8_t; + int32x2_t arg0_int32x2_t; + + out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c new file mode 100644 index 000000000..a8c7c333e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_s64 (void) +{ + int8x8_t out_int8x8_t; + int64x1_t arg0_int64x1_t; + + out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c new file mode 100644 index 000000000..dbd1eec43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u16 (void) +{ + int8x8_t out_int8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c new file mode 100644 index 000000000..40e1475ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u32 (void) +{ + int8x8_t out_int8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c new file mode 100644 index 000000000..6d53d41e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u64 (void) +{ + int8x8_t out_int8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c new file mode 100644 index 000000000..8f31a4c76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterprets8_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterprets8_u8 (void) +{ + int8x8_t out_int8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c new file mode 100644 index 000000000..f960624d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_f32 (void) +{ + uint16x4_t out_uint16x4_t; + float32x2_t arg0_float32x2_t; + + out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c new file mode 100644 index 000000000..e787a969e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p16 (void) +{ + uint16x4_t out_uint16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c new file mode 100644 index 000000000..34f920bbd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p64 (void) +{ + uint16x4_t out_uint16x4_t; + poly64x1_t arg0_poly64x1_t; + + out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c new file mode 100644 index 000000000..c332e9450 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_p8 (void) +{ + uint16x4_t out_uint16x4_t; + poly8x8_t arg0_poly8x8_t; + + out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c new file mode 100644 index 000000000..d72ec3452 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + + out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c new file mode 100644 index 000000000..b6d86c011 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s32 (void) +{ + uint16x4_t out_uint16x4_t; + int32x2_t arg0_int32x2_t; + + out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c new file mode 100644 index 000000000..87f494bec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s64 (void) +{ + uint16x4_t out_uint16x4_t; + int64x1_t arg0_int64x1_t; + + out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c new file mode 100644 index 000000000..11695c169 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_s8 (void) +{ + uint16x4_t out_uint16x4_t; + int8x8_t arg0_int8x8_t; + + out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c new file mode 100644 index 000000000..9f0171a05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x2_t arg0_uint32x2_t; + + out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c new file mode 100644 index 000000000..0db76c692 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u64 (void) +{ + uint16x4_t out_uint16x4_t; + uint64x1_t arg0_uint64x1_t; + + out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c new file mode 100644 index 000000000..71b555ac5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu16_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu16_u8 (void) +{ + uint16x4_t out_uint16x4_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c new file mode 100644 index 000000000..813b8b961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_f32 (void) +{ + uint32x2_t out_uint32x2_t; + float32x2_t arg0_float32x2_t; + + out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c new file mode 100644 index 000000000..3662cc3cd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p16 (void) +{ + uint32x2_t out_uint32x2_t; + poly16x4_t arg0_poly16x4_t; + + out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c new file mode 100644 index 000000000..b5f24fbc4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p64 (void) +{ + uint32x2_t out_uint32x2_t; + poly64x1_t arg0_poly64x1_t; + + out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c new file mode 100644 index 000000000..73ddff115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_p8 (void) +{ + uint32x2_t out_uint32x2_t; + poly8x8_t arg0_poly8x8_t; + + out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c new file mode 100644 index 000000000..02ec84c91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s16 (void) +{ + uint32x2_t out_uint32x2_t; + int16x4_t arg0_int16x4_t; + + out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c new file mode 100644 index 000000000..2a964c830 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + + out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c new file mode 100644 index 000000000..ad9493856 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s64 (void) +{ + uint32x2_t out_uint32x2_t; + int64x1_t arg0_int64x1_t; + + out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c new file mode 100644 index 000000000..8ff896e70 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_s8 (void) +{ + uint32x2_t out_uint32x2_t; + int8x8_t arg0_int8x8_t; + + out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c new file mode 100644 index 000000000..5c4883422 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u16 (void) +{ + uint32x2_t out_uint32x2_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c new file mode 100644 index 000000000..8fd55f24b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x1_t arg0_uint64x1_t; + + out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c new file mode 100644 index 000000000..ab192091d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu32_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu32_u8 (void) +{ + uint32x2_t out_uint32x2_t; + uint8x8_t arg0_uint8x8_t; + + out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c new file mode 100644 index 000000000..7ded8687a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_f32 (void) +{ + uint64x1_t out_uint64x1_t; + float32x2_t arg0_float32x2_t; + + out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c new file mode 100644 index 000000000..c48213439 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p16 (void) +{ + uint64x1_t out_uint64x1_t; + poly16x4_t arg0_poly16x4_t; + + out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c new file mode 100644 index 000000000..741912a4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p64 (void) +{ + uint64x1_t out_uint64x1_t; + poly64x1_t arg0_poly64x1_t; + + out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c new file mode 100644 index 000000000..858af4624 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_p8 (void) +{ + uint64x1_t out_uint64x1_t; + poly8x8_t arg0_poly8x8_t; + + out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c new file mode 100644 index 000000000..e07c4e83e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s16 (void) +{ + uint64x1_t out_uint64x1_t; + int16x4_t arg0_int16x4_t; + + out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c new file mode 100644 index 000000000..0fa51a1a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s32 (void) +{ + uint64x1_t out_uint64x1_t; + int32x2_t arg0_int32x2_t; + + out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c new file mode 100644 index 000000000..1f1f62e43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s64 (void) +{ + uint64x1_t out_uint64x1_t; + int64x1_t arg0_int64x1_t; + + out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c new file mode 100644 index 000000000..299b45ce5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_s8 (void) +{ + uint64x1_t out_uint64x1_t; + int8x8_t arg0_int8x8_t; + + out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c new file mode 100644 index 000000000..dd2c1550d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u16 (void) +{ + uint64x1_t out_uint64x1_t; + uint16x4_t arg0_uint16x4_t; + + out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c new file mode 100644 index 000000000..8dbe9e200 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u32 (void) +{ + uint64x1_t out_uint64x1_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c new file mode 100644 index 000000000..fe0724a8c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu64_u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu64_u8 (void) +{ + uint64x1_t out_uint64x1_t; + uint8x8_t arg0_uint8x8_t; + + out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c new file mode 100644 index 000000000..e82cba753 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_f32 (void) +{ + uint8x8_t out_uint8x8_t; + float32x2_t arg0_float32x2_t; + + out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c new file mode 100644 index 000000000..08516125c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p16 (void) +{ + uint8x8_t out_uint8x8_t; + poly16x4_t arg0_poly16x4_t; + + out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c new file mode 100644 index 000000000..907b67c15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p64 (void) +{ + uint8x8_t out_uint8x8_t; + poly64x1_t arg0_poly64x1_t; + + out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c new file mode 100644 index 000000000..91d3d0eaa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_p8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c new file mode 100644 index 000000000..50a2cd187 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s16 (void) +{ + uint8x8_t out_uint8x8_t; + int16x4_t arg0_int16x4_t; + + out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c new file mode 100644 index 000000000..a5db01b62 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s32 (void) +{ + uint8x8_t out_uint8x8_t; + int32x2_t arg0_int32x2_t; + + out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c new file mode 100644 index 000000000..f906e018b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s64 (void) +{ + uint8x8_t out_uint8x8_t; + int64x1_t arg0_int64x1_t; + + out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c new file mode 100644 index 000000000..bd2ba481f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_s8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + + out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c new file mode 100644 index 000000000..eb38ca82f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x4_t arg0_uint16x4_t; + + out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c new file mode 100644 index 000000000..6fb11b26f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u32 (void) +{ + uint8x8_t out_uint8x8_t; + uint32x2_t arg0_uint32x2_t; + + out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c new file mode 100644 index 000000000..cf7ff27ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c @@ -0,0 +1,19 @@ +/* Test the `vreinterpretu8_u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vreinterpretu8_u64 (void) +{ + uint8x8_t out_uint8x8_t; + uint64x1_t arg0_uint64x1_t; + + out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c new file mode 100644 index 000000000..b815c199f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c new file mode 100644 index 000000000..7167fec30 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c new file mode 100644 index 000000000..d43613079 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c new file mode 100644 index 000000000..15086d584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c new file mode 100644 index 000000000..b2c7ca88e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev16_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c new file mode 100644 index 000000000..10ba66f7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev16u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c new file mode 100644 index 000000000..af213d91e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c new file mode 100644 index 000000000..926068f10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c new file mode 100644 index 000000000..bfd8ec2e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c new file mode 100644 index 000000000..74fc2470d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c new file mode 100644 index 000000000..cf0220a86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c new file mode 100644 index 000000000..ad5dba31c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c new file mode 100644 index 000000000..93f19405e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c new file mode 100644 index 000000000..b19ce01c3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c new file mode 100644 index 000000000..08bf6f258 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev32_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c new file mode 100644 index 000000000..47b8a591d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev32_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c new file mode 100644 index 000000000..928c1d45c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c @@ -0,0 +1,20 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c new file mode 100644 index 000000000..ac5c63690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev32u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c new file mode 100644 index 000000000..c9ab7008d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c new file mode 100644 index 000000000..2d5d2f86b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qp16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + + out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c new file mode 100644 index 000000000..019b6d419 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qp8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + + out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c new file mode 100644 index 000000000..5923b2d2f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c new file mode 100644 index 000000000..93ffd5818 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c new file mode 100644 index 000000000..9353e7057 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c new file mode 100644 index 000000000..590d833fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c new file mode 100644 index 000000000..014da6812 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c new file mode 100644 index 000000000..4b7d8e495 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64Qu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c new file mode 100644 index 000000000..3ea280e90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64f32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrev64_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c new file mode 100644 index 000000000..1b30d60e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64p16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + + out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c new file mode 100644 index 000000000..370f49854 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + + out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c new file mode 100644 index 000000000..ee4206ba7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vrev64_s16 (arg0_int16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c new file mode 100644 index 000000000..f7057ce49 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vrev64_s32 (arg0_int32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c new file mode 100644 index 000000000..c073b0b68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vrev64_s8 (arg0_int8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c new file mode 100644 index 000000000..4fdd2697c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); +} + +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c new file mode 100644 index 000000000..61d21b69d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c new file mode 100644 index 000000000..71a6af177 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c @@ -0,0 +1,20 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrev64u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); +} + +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c new file mode 100644 index 000000000..02ca46509 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndaf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrnda_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c new file mode 100644 index 000000000..b94165735 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrnd_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c new file mode 100644 index 000000000..7f4e90bf3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndmf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndmf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndm_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c new file mode 100644 index 000000000..df8e3e934 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndnf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndn_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c new file mode 100644 index 000000000..d3900cd78 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndpf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrndp_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c new file mode 100644 index 000000000..b7b5d73c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqaf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqaf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqa_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c new file mode 100644 index 000000000..08b4b45f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c new file mode 100644 index 000000000..6d16bfc93 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqmf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqmf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqm_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c new file mode 100644 index 000000000..b31ca95db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqnf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqn_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c new file mode 100644 index 000000000..5c4a86690 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndqpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndqpf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndqp_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c new file mode 100644 index 000000000..05b92b0aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c new file mode 100644 index 000000000..5d51dec60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c new file mode 100644 index 000000000..6e1bf7532 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrtef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtef32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + + out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c new file mode 100644 index 000000000..1e4908e46 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c @@ -0,0 +1,20 @@ +/* Test the `vrsqrteu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrteu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c new file mode 100644 index 000000000..ee38e04fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c @@ -0,0 +1,21 @@ +/* Test the `vrsqrtsQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtsQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c new file mode 100644 index 000000000..36cb69def --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c @@ -0,0 +1,21 @@ +/* Test the `vrsqrtsf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vrsqrtsf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c new file mode 100644 index 000000000..c6b18495e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanef32 (void) +{ + float32x4_t out_float32x4_t; + float32_t arg0_float32_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c new file mode 100644 index 000000000..dda571aaf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16_t arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c new file mode 100644 index 000000000..873c8cfe4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanep8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8_t arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c new file mode 100644 index 000000000..f6ade301c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes16 (void) +{ + int16x8_t out_int16x8_t; + int16_t arg0_int16_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c new file mode 100644 index 000000000..c825da15e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes32 (void) +{ + int32x4_t out_int32x4_t; + int32_t arg0_int32_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c new file mode 100644 index 000000000..af8f2853c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes64 (void) +{ + int64x2_t out_int64x2_t; + int64_t arg0_int64_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c new file mode 100644 index 000000000..55dca359b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_lanes8 (void) +{ + int8x16_t out_int8x16_t; + int8_t arg0_int8_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c new file mode 100644 index 000000000..f671e1e4b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16_t arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c new file mode 100644 index 000000000..27a0f7225 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32_t arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c new file mode 100644 index 000000000..b30b26748 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64_t arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); +} + +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c new file mode 100644 index 000000000..d6e5817d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c @@ -0,0 +1,21 @@ +/* Test the `vsetQ_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsetQ_laneu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8_t arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c new file mode 100644 index 000000000..340614cd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanef32 (void) +{ + float32x2_t out_float32x2_t; + float32_t arg0_float32_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c new file mode 100644 index 000000000..d02118a25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanep16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16_t arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c new file mode 100644 index 000000000..e63a197df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanep8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8_t arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c new file mode 100644 index 000000000..6f4f4d379 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes16 (void) +{ + int16x4_t out_int16x4_t; + int16_t arg0_int16_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c new file mode 100644 index 000000000..77c22056b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes32 (void) +{ + int32x2_t out_int32x2_t; + int32_t arg0_int32_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c new file mode 100644 index 000000000..5c5454f98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vset_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes64 (void) +{ + int64x1_t out_int64x1_t; + int64_t arg0_int64_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c new file mode 100644 index 000000000..fd09e21d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c @@ -0,0 +1,21 @@ +/* Test the `vset_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_lanes8 (void) +{ + int8x8_t out_int8x8_t; + int8_t arg0_int8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c new file mode 100644 index 000000000..783cc82c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16_t arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c new file mode 100644 index 000000000..0d5a89ec1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32_t arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c new file mode 100644 index 000000000..3bff5d232 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vset_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64_t arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c new file mode 100644 index 000000000..0e4853190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c @@ -0,0 +1,21 @@ +/* Test the `vset_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vset_laneu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8_t arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c new file mode 100644 index 000000000..31344a6e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c new file mode 100644 index 000000000..dd11cd54b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c new file mode 100644 index 000000000..2fdbc0d01 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c new file mode 100644 index 000000000..078ffd41b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c new file mode 100644 index 000000000..a330ae3d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c new file mode 100644 index 000000000..cdf26269a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c new file mode 100644 index 000000000..70fe6ccf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c new file mode 100644 index 000000000..06e6b52d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshlQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c new file mode 100644 index 000000000..ed3d4a4a6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c new file mode 100644 index 000000000..6413ef8d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c new file mode 100644 index 000000000..8dc0bd470 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c new file mode 100644 index 000000000..58a6dbb97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c @@ -0,0 +1,21 @@ +/* Test the `vshlQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c new file mode 100644 index 000000000..584ef1270 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c new file mode 100644 index 000000000..77e6e0160 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c new file mode 100644 index 000000000..6138ad3dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + int64x2_t arg1_int64x2_t; + + out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c new file mode 100644 index 000000000..65bfdb1d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c @@ -0,0 +1,21 @@ +/* Test the `vshlQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c new file mode 100644 index 000000000..59a91bdec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c new file mode 100644 index 000000000..66f4c3119 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c new file mode 100644 index 000000000..f7a49f4bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c new file mode 100644 index 000000000..634e66739 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshl_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c new file mode 100644 index 000000000..7d71f84f4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c new file mode 100644 index 000000000..ae1f85ae9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c new file mode 100644 index 000000000..c4e11a18b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c new file mode 100644 index 000000000..12378ebfe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshl_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshl_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c new file mode 100644 index 000000000..cc2c7d5f6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + + out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c new file mode 100644 index 000000000..6591e42c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + + out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c new file mode 100644 index 000000000..94d904506 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshll_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_ns8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + + out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c new file mode 100644 index 000000000..eabc7928c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c new file mode 100644 index 000000000..f205caf00 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c new file mode 100644 index 000000000..bf8240fde --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshll_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshll_nu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c new file mode 100644 index 000000000..2c8941f9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c @@ -0,0 +1,21 @@ +/* Test the `vshls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c new file mode 100644 index 000000000..fb6be6ea0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c @@ -0,0 +1,21 @@ +/* Test the `vshls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c new file mode 100644 index 000000000..b5a61033f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c @@ -0,0 +1,21 @@ +/* Test the `vshls64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c new file mode 100644 index 000000000..a807191ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c @@ -0,0 +1,21 @@ +/* Test the `vshls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshls8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c new file mode 100644 index 000000000..14f2428d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c @@ -0,0 +1,21 @@ +/* Test the `vshlu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c new file mode 100644 index 000000000..596327584 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c @@ -0,0 +1,21 @@ +/* Test the `vshlu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c new file mode 100644 index 000000000..f29dedc14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c @@ -0,0 +1,21 @@ +/* Test the `vshlu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + int64x1_t arg1_int64x1_t; + + out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c new file mode 100644 index 000000000..1b900396b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c @@ -0,0 +1,21 @@ +/* Test the `vshlu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshlu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c new file mode 100644 index 000000000..286edb14b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + + out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c new file mode 100644 index 000000000..d47d574e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + + out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c new file mode 100644 index 000000000..66b693e73 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + + out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c new file mode 100644 index 000000000..f92da931d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + + out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c new file mode 100644 index 000000000..8f81e7896 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c new file mode 100644 index 000000000..e5fbf44f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c new file mode 100644 index 000000000..a8ff5f7d7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c new file mode 100644 index 000000000..673d90e4f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshrQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + + out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c new file mode 100644 index 000000000..0a14a00df --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + + out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c new file mode 100644 index 000000000..545478909 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + + out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c new file mode 100644 index 000000000..3fd27fc98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + + out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c new file mode 100644 index 000000000..069978d47 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c @@ -0,0 +1,20 @@ +/* Test the `vshr_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + + out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c new file mode 100644 index 000000000..43c610b62 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + + out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c new file mode 100644 index 000000000..1b7bb5d33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + + out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c new file mode 100644 index 000000000..a78b9fcf7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + + out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c new file mode 100644 index 000000000..cdb968693 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c @@ -0,0 +1,20 @@ +/* Test the `vshr_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshr_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + + out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c new file mode 100644 index 000000000..832dc831a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + + out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c new file mode 100644 index 000000000..314ba2516 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + + out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c new file mode 100644 index 000000000..465592a65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_ns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + + out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c new file mode 100644 index 000000000..614451a68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + + out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c new file mode 100644 index 000000000..6fe4066ac --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + + out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c new file mode 100644 index 000000000..901b17c31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c @@ -0,0 +1,20 @@ +/* Test the `vshrn_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vshrn_nu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + + out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c new file mode 100644 index 000000000..601ee13c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c new file mode 100644 index 000000000..cbb47285e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsliQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c new file mode 100644 index 000000000..8e5a256e8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c new file mode 100644 index 000000000..d3c67ac77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c new file mode 100644 index 000000000..12b69848f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c new file mode 100644 index 000000000..441996f8d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c new file mode 100644 index 000000000..8f393b4c9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c new file mode 100644 index 000000000..0936eb759 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c new file mode 100644 index 000000000..23b1dddcf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c new file mode 100644 index 000000000..b14a16592 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c new file mode 100644 index 000000000..d6a86a6e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsliQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsliQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c new file mode 100644 index 000000000..30d206e79 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c new file mode 100644 index 000000000..801add49b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsli_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c new file mode 100644 index 000000000..ffcacb25b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c new file mode 100644 index 000000000..1d58cc7ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c new file mode 100644 index 000000000..1920c9115 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c new file mode 100644 index 000000000..4bef7bc91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c new file mode 100644 index 000000000..7b0260f4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c new file mode 100644 index 000000000..addda9c20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c new file mode 100644 index 000000000..0bdaef3a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c new file mode 100644 index 000000000..3733d7055 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c new file mode 100644 index 000000000..020e5959b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsli_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsli_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c new file mode 100644 index 000000000..d1f6100e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c new file mode 100644 index 000000000..9d44cca6b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c new file mode 100644 index 000000000..bcda76849 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c new file mode 100644 index 000000000..0dbf181c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c new file mode 100644 index 000000000..4b6553314 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c new file mode 100644 index 000000000..721459583 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c new file mode 100644 index 000000000..8a982d205 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c new file mode 100644 index 000000000..523e5a09b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsraQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsraQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c new file mode 100644 index 000000000..37c97c562 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c new file mode 100644 index 000000000..e79430804 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c new file mode 100644 index 000000000..6381a13e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c new file mode 100644 index 000000000..6f46eef22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsra_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c new file mode 100644 index 000000000..42ad77321 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c new file mode 100644 index 000000000..baaab7e48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c new file mode 100644 index 000000000..dc63a5ad9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c new file mode 100644 index 000000000..5555f75d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsra_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsra_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c new file mode 100644 index 000000000..39a96c080 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_np16 (void) +{ + poly16x8_t out_poly16x8_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c new file mode 100644 index 000000000..d2e48165a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsriQ_np64 (void) +{ + poly64x2_t out_poly64x2_t; + poly64x2_t arg0_poly64x2_t; + poly64x2_t arg1_poly64x2_t; + + out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c new file mode 100644 index 000000000..d17d7e724 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_np8 (void) +{ + poly8x16_t out_poly8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c new file mode 100644 index 000000000..c7375409c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c new file mode 100644 index 000000000..1b17696aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c new file mode 100644 index 000000000..d959c341b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c new file mode 100644 index 000000000..b04c800cf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_ns8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c new file mode 100644 index 000000000..2d3f1d6b7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c new file mode 100644 index 000000000..19c87fec7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c new file mode 100644 index 000000000..b747b2237 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c new file mode 100644 index 000000000..1e949e5e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsriQ_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsriQ_nu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c new file mode 100644 index 000000000..a1aac08f1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_np16 (void) +{ + poly16x4_t out_poly16x4_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c new file mode 100644 index 000000000..0abffc2e0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vsri_np64 (void) +{ + poly64x1_t out_poly64x1_t; + poly64x1_t arg0_poly64x1_t; + poly64x1_t arg1_poly64x1_t; + + out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c new file mode 100644 index 000000000..bd102bf98 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_np8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_np8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c new file mode 100644 index 000000000..bb0687220 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c new file mode 100644 index 000000000..8712857ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c new file mode 100644 index 000000000..f54fca4dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c new file mode 100644 index 000000000..405e03522 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_ns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_ns8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c new file mode 100644 index 000000000..4c751e792 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c new file mode 100644 index 000000000..b82f63b59 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c new file mode 100644 index 000000000..20381bfd2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c new file mode 100644 index 000000000..87293317c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c @@ -0,0 +1,21 @@ +/* Test the `vsri_nu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsri_nu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c new file mode 100644 index 000000000..1f95128e6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c new file mode 100644 index 000000000..90e7ccc1b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c new file mode 100644 index 000000000..74a198baf --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x2_t arg1_poly64x2_t; + + vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c new file mode 100644 index 000000000..6abb646c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c new file mode 100644 index 000000000..ec283e228 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c new file mode 100644 index 000000000..6e73d6e11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c new file mode 100644 index 000000000..46d369c99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c new file mode 100644 index 000000000..d7b3a1c12 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c new file mode 100644 index 000000000..27958f6d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c new file mode 100644 index 000000000..b4aa760e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c new file mode 100644 index 000000000..5f4c927b6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c @@ -0,0 +1,25 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ + +/* Detect ICE in the case of unaligned memory address. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +unsigned char dummy_store[1000]; + +void +foo (char* addr) +{ + uint8x16_t vdata = vld1q_u8 (addr); + vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0); +} + +uint64_t +bar (uint64x2_t vdata) +{ + vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0); + return vgetq_lane_u64 (vdata, 0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c new file mode 100644 index 000000000..54faaa3fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c new file mode 100644 index 000000000..9b09e72c2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Q_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Q_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c new file mode 100644 index 000000000..a4b3d8a1c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4_t arg1_float32x4_t; + + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c new file mode 100644 index 000000000..9b4873371 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8_t arg1_poly16x8_t; + + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c new file mode 100644 index 000000000..7d1e020f1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1Qp64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x2_t arg1_poly64x2_t; + + vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c new file mode 100644 index 000000000..f3843399e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16_t arg1_poly8x16_t; + + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c new file mode 100644 index 000000000..e6c39cf35 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8_t arg1_int16x8_t; + + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c new file mode 100644 index 000000000..587dcf0ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4_t arg1_int32x4_t; + + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c new file mode 100644 index 000000000..50511d1ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs64 (void) +{ + int64_t *arg0_int64_t; + int64x2_t arg1_int64x2_t; + + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c new file mode 100644 index 000000000..2de9814b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16_t arg1_int8x16_t; + + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c new file mode 100644 index 000000000..81d8cc5ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8_t arg1_uint16x8_t; + + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c new file mode 100644 index 000000000..408c6b29e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4_t arg1_uint32x4_t; + + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c new file mode 100644 index 000000000..1c17e5b0c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x2_t arg1_uint64x2_t; + + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c new file mode 100644 index 000000000..1605e2756 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16_t arg1_uint8x16_t; + + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c new file mode 100644 index 000000000..781703140 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c new file mode 100644 index 000000000..c6a19daf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c new file mode 100644 index 000000000..f8c70c359 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1_lanep64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1_t arg1_poly64x1_t; + + vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c new file mode 100644 index 000000000..1b5dd4f77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c new file mode 100644 index 000000000..4efdc5024 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c new file mode 100644 index 000000000..9c3c1354c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c new file mode 100644 index 000000000..64fed4a10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c new file mode 100644 index 000000000..59646f8a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c new file mode 100644 index 000000000..6ae716647 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c new file mode 100644 index 000000000..369abf7fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c new file mode 100644 index 000000000..7296fee8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c new file mode 100644 index 000000000..ba6076e1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst1_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c new file mode 100644 index 000000000..f3460f5e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c @@ -0,0 +1,20 @@ +/* Test the `vst1f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1f32 (void) +{ + float32_t *arg0_float32_t; + float32x2_t arg1_float32x2_t; + + vst1_f32 (arg0_float32_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c new file mode 100644 index 000000000..7504c5cf8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c @@ -0,0 +1,20 @@ +/* Test the `vst1p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4_t arg1_poly16x4_t; + + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c new file mode 100644 index 000000000..7329fba9d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c @@ -0,0 +1,20 @@ +/* Test the `vst1p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1_t arg1_poly64x1_t; + + vst1_p64 (arg0_poly64_t, arg1_poly64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c new file mode 100644 index 000000000..3059aac60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c @@ -0,0 +1,20 @@ +/* Test the `vst1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8_t arg1_poly8x8_t; + + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c new file mode 100644 index 000000000..fbddb2fd7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c @@ -0,0 +1,20 @@ +/* Test the `vst1s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s16 (void) +{ + int16_t *arg0_int16_t; + int16x4_t arg1_int16x4_t; + + vst1_s16 (arg0_int16_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c new file mode 100644 index 000000000..f264db036 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c @@ -0,0 +1,20 @@ +/* Test the `vst1s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s32 (void) +{ + int32_t *arg0_int32_t; + int32x2_t arg1_int32x2_t; + + vst1_s32 (arg0_int32_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c new file mode 100644 index 000000000..64de48bb0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c @@ -0,0 +1,20 @@ +/* Test the `vst1s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s64 (void) +{ + int64_t *arg0_int64_t; + int64x1_t arg1_int64x1_t; + + vst1_s64 (arg0_int64_t, arg1_int64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c new file mode 100644 index 000000000..7916448d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c @@ -0,0 +1,20 @@ +/* Test the `vst1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1s8 (void) +{ + int8_t *arg0_int8_t; + int8x8_t arg1_int8x8_t; + + vst1_s8 (arg0_int8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c new file mode 100644 index 000000000..797aef16f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c @@ -0,0 +1,20 @@ +/* Test the `vst1u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4_t arg1_uint16x4_t; + + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c new file mode 100644 index 000000000..563ea9dc3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c @@ -0,0 +1,20 @@ +/* Test the `vst1u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2_t arg1_uint32x2_t; + + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c new file mode 100644 index 000000000..b95f5d587 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c @@ -0,0 +1,20 @@ +/* Test the `vst1u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1_t arg1_uint64x1_t; + + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c new file mode 100644 index 000000000..75358e769 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c @@ -0,0 +1,20 @@ +/* Test the `vst1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8_t arg1_uint8x8_t; + + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c new file mode 100644 index 000000000..485735632 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c new file mode 100644 index 000000000..bed15034c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c new file mode 100644 index 000000000..57867352f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c new file mode 100644 index 000000000..cf0dc15dd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c new file mode 100644 index 000000000..b751e6b97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c new file mode 100644 index 000000000..b5fbe0e28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst2Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c new file mode 100644 index 000000000..56f9adcda --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x2_t arg1_float32x4x2_t; + + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c new file mode 100644 index 000000000..184199033 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x2_t arg1_poly16x8x2_t; + + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c new file mode 100644 index 000000000..2d98ec910 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x2_t arg1_poly8x16x2_t; + + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c new file mode 100644 index 000000000..39395f6d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x2_t arg1_int16x8x2_t; + + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c new file mode 100644 index 000000000..1768d4786 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x2_t arg1_int32x4x2_t; + + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c new file mode 100644 index 000000000..423cb8c8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x2_t arg1_int8x16x2_t; + + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c new file mode 100644 index 000000000..a25958a72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x2_t arg1_uint16x8x2_t; + + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c new file mode 100644 index 000000000..47722b352 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x2_t arg1_uint32x4x2_t; + + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c new file mode 100644 index 000000000..b79478026 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst2Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x2_t arg1_uint8x16x2_t; + + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c new file mode 100644 index 000000000..e7752920e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c new file mode 100644 index 000000000..be9913b39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c new file mode 100644 index 000000000..0a95e268d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c new file mode 100644 index 000000000..728593ccb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c new file mode 100644 index 000000000..32d49b58c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c new file mode 100644 index 000000000..9e67eb323 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c new file mode 100644 index 000000000..d56f20961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c new file mode 100644 index 000000000..053704cea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c new file mode 100644 index 000000000..a35360088 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst2_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c new file mode 100644 index 000000000..b43c4135b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c @@ -0,0 +1,20 @@ +/* Test the `vst2f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x2_t arg1_float32x2x2_t; + + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c new file mode 100644 index 000000000..1d112ff65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c @@ -0,0 +1,20 @@ +/* Test the `vst2p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x2_t arg1_poly16x4x2_t; + + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c new file mode 100644 index 000000000..3ccaa5464 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c @@ -0,0 +1,20 @@ +/* Test the `vst2p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst2p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x2_t arg1_poly64x1x2_t; + + vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c new file mode 100644 index 000000000..59c4d62e3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c @@ -0,0 +1,20 @@ +/* Test the `vst2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x2_t arg1_poly8x8x2_t; + + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c new file mode 100644 index 000000000..eb6cb59a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c @@ -0,0 +1,20 @@ +/* Test the `vst2s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x2_t arg1_int16x4x2_t; + + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c new file mode 100644 index 000000000..a17b58dc4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c @@ -0,0 +1,20 @@ +/* Test the `vst2s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x2_t arg1_int32x2x2_t; + + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c new file mode 100644 index 000000000..668ae50a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c @@ -0,0 +1,20 @@ +/* Test the `vst2s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x2_t arg1_int64x1x2_t; + + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c new file mode 100644 index 000000000..343414e34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c @@ -0,0 +1,20 @@ +/* Test the `vst2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x2_t arg1_int8x8x2_t; + + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c new file mode 100644 index 000000000..903279d0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c @@ -0,0 +1,20 @@ +/* Test the `vst2u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x2_t arg1_uint16x4x2_t; + + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); +} + +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c new file mode 100644 index 000000000..1396ed119 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c @@ -0,0 +1,20 @@ +/* Test the `vst2u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x2_t arg1_uint32x2x2_t; + + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); +} + +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c new file mode 100644 index 000000000..006e31f25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c @@ -0,0 +1,20 @@ +/* Test the `vst2u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x2_t arg1_uint64x1x2_t; + + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c new file mode 100644 index 000000000..55cd34779 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c @@ -0,0 +1,20 @@ +/* Test the `vst2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst2u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x2_t arg1_uint8x8x2_t; + + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); +} + +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c new file mode 100644 index 000000000..8e4f0dca9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c new file mode 100644 index 000000000..f8fcb977f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c new file mode 100644 index 000000000..3fde1a3af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c new file mode 100644 index 000000000..1eb428922 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c new file mode 100644 index 000000000..ca98dded6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c new file mode 100644 index 000000000..a2a59d7a7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst3Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c new file mode 100644 index 000000000..b4b480fb7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x3_t arg1_float32x4x3_t; + + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c new file mode 100644 index 000000000..aa34886f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x3_t arg1_poly16x8x3_t; + + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c new file mode 100644 index 000000000..b13fcd7e2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x3_t arg1_poly8x16x3_t; + + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c new file mode 100644 index 000000000..6cac405f0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x3_t arg1_int16x8x3_t; + + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c new file mode 100644 index 000000000..3c8437094 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x3_t arg1_int32x4x3_t; + + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c new file mode 100644 index 000000000..fee56af42 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x3_t arg1_int8x16x3_t; + + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c new file mode 100644 index 000000000..af3910b7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x3_t arg1_uint16x8x3_t; + + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c new file mode 100644 index 000000000..8828885af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x3_t arg1_uint32x4x3_t; + + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c new file mode 100644 index 000000000..c273fe6dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst3Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x3_t arg1_uint8x16x3_t; + + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c new file mode 100644 index 000000000..de654e907 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c new file mode 100644 index 000000000..de733ff67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c new file mode 100644 index 000000000..a9a26447f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c new file mode 100644 index 000000000..a98b40714 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c new file mode 100644 index 000000000..5b2450c67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c new file mode 100644 index 000000000..8cd04f716 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c new file mode 100644 index 000000000..692058d91 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c new file mode 100644 index 000000000..32a5193a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c new file mode 100644 index 000000000..952ffcbec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst3_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c new file mode 100644 index 000000000..e80b8e916 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c @@ -0,0 +1,20 @@ +/* Test the `vst3f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x3_t arg1_float32x2x3_t; + + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c new file mode 100644 index 000000000..1d7831264 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c @@ -0,0 +1,20 @@ +/* Test the `vst3p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x3_t arg1_poly16x4x3_t; + + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c new file mode 100644 index 000000000..73ced9544 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c @@ -0,0 +1,20 @@ +/* Test the `vst3p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst3p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x3_t arg1_poly64x1x3_t; + + vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c new file mode 100644 index 000000000..ca8c5ec43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c @@ -0,0 +1,20 @@ +/* Test the `vst3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x3_t arg1_poly8x8x3_t; + + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c new file mode 100644 index 000000000..5c1bcf9de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c @@ -0,0 +1,20 @@ +/* Test the `vst3s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x3_t arg1_int16x4x3_t; + + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c new file mode 100644 index 000000000..3f5a3aad1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c @@ -0,0 +1,20 @@ +/* Test the `vst3s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x3_t arg1_int32x2x3_t; + + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c new file mode 100644 index 000000000..8c6a851db --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c @@ -0,0 +1,20 @@ +/* Test the `vst3s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x3_t arg1_int64x1x3_t; + + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c new file mode 100644 index 000000000..8853fbaf5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c @@ -0,0 +1,20 @@ +/* Test the `vst3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x3_t arg1_int8x8x3_t; + + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c new file mode 100644 index 000000000..e17c6c8d6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c @@ -0,0 +1,20 @@ +/* Test the `vst3u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x3_t arg1_uint16x4x3_t; + + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); +} + +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c new file mode 100644 index 000000000..3b7d8ce20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c @@ -0,0 +1,20 @@ +/* Test the `vst3u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x3_t arg1_uint32x2x3_t; + + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); +} + +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c new file mode 100644 index 000000000..08d9c7a08 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c @@ -0,0 +1,20 @@ +/* Test the `vst3u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x3_t arg1_uint64x1x3_t; + + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c new file mode 100644 index 000000000..78944cba0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c @@ -0,0 +1,20 @@ +/* Test the `vst3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst3u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x3_t arg1_uint8x8x3_t; + + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); +} + +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c new file mode 100644 index 000000000..adbb4d569 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c new file mode 100644 index 000000000..587477c87 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c new file mode 100644 index 000000000..3febdf7d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c new file mode 100644 index 000000000..71406af83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c new file mode 100644 index 000000000..1229c86a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c new file mode 100644 index 000000000..5e0683f30 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst4Q_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Q_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c new file mode 100644 index 000000000..2ecb6b173 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qf32 (void) +{ + float32_t *arg0_float32_t; + float32x4x4_t arg1_float32x4x4_t; + + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c new file mode 100644 index 000000000..a9b9b7ca9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qp16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x8x4_t arg1_poly16x8x4_t; + + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c new file mode 100644 index 000000000..17142c1a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qp8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x16x4_t arg1_poly8x16x4_t; + + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c new file mode 100644 index 000000000..8511619fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs16 (void) +{ + int16_t *arg0_int16_t; + int16x8x4_t arg1_int16x8x4_t; + + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c new file mode 100644 index 000000000..f65894eab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs32 (void) +{ + int32_t *arg0_int32_t; + int32x4x4_t arg1_int32x4x4_t; + + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c new file mode 100644 index 000000000..a74d58b5f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qs8 (void) +{ + int8_t *arg0_int8_t; + int8x16x4_t arg1_int8x16x4_t; + + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c new file mode 100644 index 000000000..b124c7cc9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x8x4_t arg1_uint16x8x4_t; + + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c new file mode 100644 index 000000000..fa7d2130d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x4x4_t arg1_uint32x4x4_t; + + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c new file mode 100644 index 000000000..d853b12bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c @@ -0,0 +1,21 @@ +/* Test the `vst4Qu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4Qu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x16x4_t arg1_uint8x16x4_t; + + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c new file mode 100644 index 000000000..acef9f0a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanef32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanef32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c new file mode 100644 index 000000000..64e4713ff --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanep16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanep16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c new file mode 100644 index 000000000..1ac58df28 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanep8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanep8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c new file mode 100644 index 000000000..e7e1e2aea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c new file mode 100644 index 000000000..2c99611a8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c new file mode 100644 index 000000000..7eebc1644 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_lanes8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_lanes8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c new file mode 100644 index 000000000..decc7caf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c new file mode 100644 index 000000000..4cfeddbbb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c new file mode 100644 index 000000000..217ced27a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c @@ -0,0 +1,20 @@ +/* Test the `vst4_laneu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4_laneu8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c new file mode 100644 index 000000000..931b8ed15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c @@ -0,0 +1,20 @@ +/* Test the `vst4f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4f32 (void) +{ + float32_t *arg0_float32_t; + float32x2x4_t arg1_float32x2x4_t; + + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c new file mode 100644 index 000000000..ea58c44fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c @@ -0,0 +1,20 @@ +/* Test the `vst4p16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4p16 (void) +{ + poly16_t *arg0_poly16_t; + poly16x4x4_t arg1_poly16x4x4_t; + + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c new file mode 100644 index 000000000..b9f7b168d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c @@ -0,0 +1,20 @@ +/* Test the `vst4p64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst4p64 (void) +{ + poly64_t *arg0_poly64_t; + poly64x1x4_t arg1_poly64x1x4_t; + + vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c new file mode 100644 index 000000000..95e5ccdf1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c @@ -0,0 +1,20 @@ +/* Test the `vst4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4p8 (void) +{ + poly8_t *arg0_poly8_t; + poly8x8x4_t arg1_poly8x8x4_t; + + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c new file mode 100644 index 000000000..7811d74c1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c @@ -0,0 +1,20 @@ +/* Test the `vst4s16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s16 (void) +{ + int16_t *arg0_int16_t; + int16x4x4_t arg1_int16x4x4_t; + + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c new file mode 100644 index 000000000..f93ea4097 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c @@ -0,0 +1,20 @@ +/* Test the `vst4s32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s32 (void) +{ + int32_t *arg0_int32_t; + int32x2x4_t arg1_int32x2x4_t; + + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c new file mode 100644 index 000000000..796762a3e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c @@ -0,0 +1,20 @@ +/* Test the `vst4s64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s64 (void) +{ + int64_t *arg0_int64_t; + int64x1x4_t arg1_int64x1x4_t; + + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c new file mode 100644 index 000000000..877e2c407 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c @@ -0,0 +1,20 @@ +/* Test the `vst4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4s8 (void) +{ + int8_t *arg0_int8_t; + int8x8x4_t arg1_int8x8x4_t; + + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c new file mode 100644 index 000000000..5de43f591 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c @@ -0,0 +1,20 @@ +/* Test the `vst4u16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u16 (void) +{ + uint16_t *arg0_uint16_t; + uint16x4x4_t arg1_uint16x4x4_t; + + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); +} + +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c new file mode 100644 index 000000000..1ae9e5e60 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c @@ -0,0 +1,20 @@ +/* Test the `vst4u32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u32 (void) +{ + uint32_t *arg0_uint32_t; + uint32x2x4_t arg1_uint32x2x4_t; + + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); +} + +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c new file mode 100644 index 000000000..2453d6bd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c @@ -0,0 +1,20 @@ +/* Test the `vst4u64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u64 (void) +{ + uint64_t *arg0_uint64_t; + uint64x1x4_t arg1_uint64x1x4_t; + + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); +} + +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c new file mode 100644 index 000000000..380acc647 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c @@ -0,0 +1,20 @@ +/* Test the `vst4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst4u8 (void) +{ + uint8_t *arg0_uint8_t; + uint8x8x4_t arg1_uint8x8x4_t; + + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); +} + +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c new file mode 100644 index 000000000..88caa2898 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c new file mode 100644 index 000000000..d33790b9c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs16 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c new file mode 100644 index 000000000..77b2a743f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs32 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c new file mode 100644 index 000000000..1b0c5a198 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c new file mode 100644 index 000000000..11b2f6a8b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c @@ -0,0 +1,21 @@ +/* Test the `vsubQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQs8 (void) +{ + int8x16_t out_int8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c new file mode 100644 index 000000000..e3f750406 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c new file mode 100644 index 000000000..5fe1d0b4a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c new file mode 100644 index 000000000..19536b992 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu64 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c new file mode 100644 index 000000000..c9f5d95b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c new file mode 100644 index 000000000..442828abd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c @@ -0,0 +1,21 @@ +/* Test the `vsubf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubf32 (void) +{ + float32x2_t out_float32x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c new file mode 100644 index 000000000..06e6189be --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns16 (void) +{ + int8x8_t out_int8x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c new file mode 100644 index 000000000..42e8b5740 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns32 (void) +{ + int16x4_t out_int16x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c new file mode 100644 index 000000000..f314a40d5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c @@ -0,0 +1,21 @@ +/* Test the `vsubhns64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhns64 (void) +{ + int32x2_t out_int32x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c new file mode 100644 index 000000000..5c3f82624 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu16 (void) +{ + uint8x8_t out_uint8x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c new file mode 100644 index 000000000..1bd62fc15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu32 (void) +{ + uint16x4_t out_uint16x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c new file mode 100644 index 000000000..35fa65afa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c @@ -0,0 +1,21 @@ +/* Test the `vsubhnu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubhnu64 (void) +{ + uint32x2_t out_uint32x2_t; + uint64x2_t arg0_uint64x2_t; + uint64x2_t arg1_uint64x2_t; + + out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); +} + +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c new file mode 100644 index 000000000..1db042d94 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c @@ -0,0 +1,21 @@ +/* Test the `vsubls16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls16 (void) +{ + int32x4_t out_int32x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c new file mode 100644 index 000000000..e8acf9240 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c @@ -0,0 +1,21 @@ +/* Test the `vsubls32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls32 (void) +{ + int64x2_t out_int64x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c new file mode 100644 index 000000000..7b457cadb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c @@ -0,0 +1,21 @@ +/* Test the `vsubls8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubls8 (void) +{ + int16x8_t out_int16x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c new file mode 100644 index 000000000..b9cc873ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c @@ -0,0 +1,21 @@ +/* Test the `vsublu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c new file mode 100644 index 000000000..afb456e65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c @@ -0,0 +1,21 @@ +/* Test the `vsublu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c new file mode 100644 index 000000000..890925437 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c @@ -0,0 +1,21 @@ +/* Test the `vsublu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsublu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c new file mode 100644 index 000000000..0638a7dfe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c @@ -0,0 +1,21 @@ +/* Test the `vsubs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs16 (void) +{ + int16x4_t out_int16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c new file mode 100644 index 000000000..0c9b6a360 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c @@ -0,0 +1,21 @@ +/* Test the `vsubs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs32 (void) +{ + int32x2_t out_int32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c new file mode 100644 index 000000000..57bcd33d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c @@ -0,0 +1,20 @@ +/* Test the `vsubs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs64 (void) +{ + int64x1_t out_int64x1_t; + int64x1_t arg0_int64x1_t; + int64x1_t arg1_int64x1_t; + + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c new file mode 100644 index 000000000..cb927d615 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c @@ -0,0 +1,21 @@ +/* Test the `vsubs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubs8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c new file mode 100644 index 000000000..80985e247 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c new file mode 100644 index 000000000..47d595ba1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c new file mode 100644 index 000000000..3a8ae462e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c @@ -0,0 +1,20 @@ +/* Test the `vsubu64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu64 (void) +{ + uint64x1_t out_uint64x1_t; + uint64x1_t arg0_uint64x1_t; + uint64x1_t arg1_uint64x1_t; + + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c new file mode 100644 index 000000000..b359e1655 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c new file mode 100644 index 000000000..90cbe20a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c @@ -0,0 +1,21 @@ +/* Test the `vsubws16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws16 (void) +{ + int32x4_t out_int32x4_t; + int32x4_t arg0_int32x4_t; + int16x4_t arg1_int16x4_t; + + out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c new file mode 100644 index 000000000..963e5933c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c @@ -0,0 +1,21 @@ +/* Test the `vsubws32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws32 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int32x2_t arg1_int32x2_t; + + out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c new file mode 100644 index 000000000..103b8fcb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c @@ -0,0 +1,21 @@ +/* Test the `vsubws8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubws8 (void) +{ + int16x8_t out_int16x8_t; + int16x8_t arg0_int16x8_t; + int8x8_t arg1_int8x8_t; + + out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c new file mode 100644 index 000000000..98e5cdac3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu16 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c new file mode 100644 index 000000000..ccd2a7b09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu32 (void) +{ + uint64x2_t out_uint64x2_t; + uint64x2_t arg0_uint64x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c new file mode 100644 index 000000000..c89e73331 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c @@ -0,0 +1,21 @@ +/* Test the `vsubwu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vsubwu8 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c new file mode 100644 index 000000000..225159c3a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c new file mode 100644 index 000000000..a8ecd46e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c new file mode 100644 index 000000000..1d2ea7d0d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c new file mode 100644 index 000000000..bb748f95b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x2_t arg0_poly8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c new file mode 100644 index 000000000..29dc16190 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x2_t arg0_int8x8x2_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c new file mode 100644 index 000000000..493538461 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x2_t arg0_uint8x8x2_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c new file mode 100644 index 000000000..4bc77fa1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x3_t arg0_poly8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c new file mode 100644 index 000000000..f088f3777 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x3_t arg0_int8x8x3_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c new file mode 100644 index 000000000..3f84d0062 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x3_t arg0_uint8x8x3_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c new file mode 100644 index 000000000..2cdc37d04 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8x4_t arg0_poly8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c new file mode 100644 index 000000000..870c9bd4e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8x4_t arg0_int8x8x4_t; + int8x8_t arg1_int8x8_t; + + out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c new file mode 100644 index 000000000..461fc9569 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c @@ -0,0 +1,21 @@ +/* Test the `vtbl4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbl4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8x4_t arg0_uint8x8x4_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c new file mode 100644 index 000000000..a081f169e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c new file mode 100644 index 000000000..400ef33ca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c new file mode 100644 index 000000000..da4a65d43 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx1u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx1u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c new file mode 100644 index 000000000..ffc07b470 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x2_t arg1_poly8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c new file mode 100644 index 000000000..96c9104a1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x2_t arg1_int8x8x2_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c new file mode 100644 index 000000000..4b5606448 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx2u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx2u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x2_t arg1_uint8x8x2_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c new file mode 100644 index 000000000..8f06ef92e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x3_t arg1_poly8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c new file mode 100644 index 000000000..996277476 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x3_t arg1_int8x8x3_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c new file mode 100644 index 000000000..b6785512a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx3u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx3u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x3_t arg1_uint8x8x3_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c new file mode 100644 index 000000000..c021cf823 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4p8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4p8 (void) +{ + poly8x8_t out_poly8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8x4_t arg1_poly8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c new file mode 100644 index 000000000..c06b1aaf9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4s8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4s8 (void) +{ + int8x8_t out_int8x8_t; + int8x8_t arg0_int8x8_t; + int8x8x4_t arg1_int8x8x4_t; + int8x8_t arg2_int8x8_t; + + out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c new file mode 100644 index 000000000..e43ca46f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c @@ -0,0 +1,22 @@ +/* Test the `vtbx4u8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtbx4u8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8x4_t arg1_uint8x8x4_t; + uint8x8_t arg2_uint8x8_t; + + out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c new file mode 100644 index 000000000..690fa19d8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c new file mode 100644 index 000000000..58f156eab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c new file mode 100644 index 000000000..0819bfbf2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c new file mode 100644 index 000000000..dc4f76e8e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c new file mode 100644 index 000000000..fe71416de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c new file mode 100644 index 000000000..5ddd827d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c new file mode 100644 index 000000000..1d66dae84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c new file mode 100644 index 000000000..2712dd513 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c new file mode 100644 index 000000000..58f6f64e9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c new file mode 100644 index 000000000..c5a301b99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c new file mode 100644 index 000000000..b970a6a26 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c new file mode 100644 index 000000000..615bd5750 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c new file mode 100644 index 000000000..068720c86 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c @@ -0,0 +1,21 @@ +/* Test the `vtrns16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c new file mode 100644 index 000000000..f01047497 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c @@ -0,0 +1,21 @@ +/* Test the `vtrns32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c new file mode 100644 index 000000000..bf900a107 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c @@ -0,0 +1,21 @@ +/* Test the `vtrns8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrns8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c new file mode 100644 index 000000000..aa98b4026 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c new file mode 100644 index 000000000..74f5cace6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c new file mode 100644 index 000000000..f4766be76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c @@ -0,0 +1,21 @@ +/* Test the `vtrnu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtrnu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c new file mode 100644 index 000000000..69e876328 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQp8 (void) +{ + uint8x16_t out_uint8x16_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c new file mode 100644 index 000000000..a41fd7df9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs16 (void) +{ + uint16x8_t out_uint16x8_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c new file mode 100644 index 000000000..b5e46b442 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs32 (void) +{ + uint32x4_t out_uint32x4_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c new file mode 100644 index 000000000..f3bf7004a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQs8 (void) +{ + uint8x16_t out_uint8x16_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c new file mode 100644 index 000000000..7024ebe1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu16 (void) +{ + uint16x8_t out_uint16x8_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c new file mode 100644 index 000000000..717ffd1ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu32 (void) +{ + uint32x4_t out_uint32x4_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c new file mode 100644 index 000000000..bc3729961 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c @@ -0,0 +1,21 @@ +/* Test the `vtstQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstQu8 (void) +{ + uint8x16_t out_uint8x16_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c new file mode 100644 index 000000000..6bd7cae15 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c @@ -0,0 +1,21 @@ +/* Test the `vtstp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstp8 (void) +{ + uint8x8_t out_uint8x8_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c new file mode 100644 index 000000000..1637af486 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c @@ -0,0 +1,21 @@ +/* Test the `vtsts16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts16 (void) +{ + uint16x4_t out_uint16x4_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c new file mode 100644 index 000000000..e8037b977 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c @@ -0,0 +1,21 @@ +/* Test the `vtsts32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts32 (void) +{ + uint32x2_t out_uint32x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c new file mode 100644 index 000000000..ec3379adb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c @@ -0,0 +1,21 @@ +/* Test the `vtsts8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtsts8 (void) +{ + uint8x8_t out_uint8x8_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c new file mode 100644 index 000000000..629855f61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c @@ -0,0 +1,21 @@ +/* Test the `vtstu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu16 (void) +{ + uint16x4_t out_uint16x4_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c new file mode 100644 index 000000000..a8b774b7b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c @@ -0,0 +1,21 @@ +/* Test the `vtstu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu32 (void) +{ + uint32x2_t out_uint32x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c new file mode 100644 index 000000000..51480d8ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c @@ -0,0 +1,21 @@ +/* Test the `vtstu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vtstu8 (void) +{ + uint8x8_t out_uint8x8_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c new file mode 100644 index 000000000..2f429394e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c new file mode 100644 index 000000000..31760090a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c new file mode 100644 index 000000000..e5d7a2de5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c new file mode 100644 index 000000000..b0a427e4d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c new file mode 100644 index 000000000..b883174b9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c new file mode 100644 index 000000000..84d2a8afb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c new file mode 100644 index 000000000..f583a5082 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c new file mode 100644 index 000000000..3c96ef362 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c new file mode 100644 index 000000000..f385a56ce --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c new file mode 100644 index 000000000..ca92c7e9a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c new file mode 100644 index 000000000..cf2b796ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c new file mode 100644 index 000000000..da46ec058 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c new file mode 100644 index 000000000..4d0a90670 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c @@ -0,0 +1,21 @@ +/* Test the `vuzps16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c new file mode 100644 index 000000000..b337fad20 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c @@ -0,0 +1,21 @@ +/* Test the `vuzps32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c new file mode 100644 index 000000000..73da12852 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c @@ -0,0 +1,21 @@ +/* Test the `vuzps8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzps8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c new file mode 100644 index 000000000..259a141e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c new file mode 100644 index 000000000..1d5fae6a2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c new file mode 100644 index 000000000..e5e368039 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c @@ -0,0 +1,21 @@ +/* Test the `vuzpu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vuzpu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c new file mode 100644 index 000000000..fee46b793 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQf32 (void) +{ + float32x4x2_t out_float32x4x2_t; + float32x4_t arg0_float32x4_t; + float32x4_t arg1_float32x4_t; + + out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c new file mode 100644 index 000000000..1a0b0803e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQp16 (void) +{ + poly16x8x2_t out_poly16x8x2_t; + poly16x8_t arg0_poly16x8_t; + poly16x8_t arg1_poly16x8_t; + + out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c new file mode 100644 index 000000000..c0cca6074 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQp8 (void) +{ + poly8x16x2_t out_poly8x16x2_t; + poly8x16_t arg0_poly8x16_t; + poly8x16_t arg1_poly8x16_t; + + out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c new file mode 100644 index 000000000..2979d1a0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs16 (void) +{ + int16x8x2_t out_int16x8x2_t; + int16x8_t arg0_int16x8_t; + int16x8_t arg1_int16x8_t; + + out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c new file mode 100644 index 000000000..4a96c4aa3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs32 (void) +{ + int32x4x2_t out_int32x4x2_t; + int32x4_t arg0_int32x4_t; + int32x4_t arg1_int32x4_t; + + out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c new file mode 100644 index 000000000..718756774 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQs8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQs8 (void) +{ + int8x16x2_t out_int8x16x2_t; + int8x16_t arg0_int8x16_t; + int8x16_t arg1_int8x16_t; + + out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c new file mode 100644 index 000000000..b4641de3a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu16 (void) +{ + uint16x8x2_t out_uint16x8x2_t; + uint16x8_t arg0_uint16x8_t; + uint16x8_t arg1_uint16x8_t; + + out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c new file mode 100644 index 000000000..c8fee60c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu32 (void) +{ + uint32x4x2_t out_uint32x4x2_t; + uint32x4_t arg0_uint32x4_t; + uint32x4_t arg1_uint32x4_t; + + out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); +} + +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c new file mode 100644 index 000000000..eee6bc54f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c @@ -0,0 +1,21 @@ +/* Test the `vzipQu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipQu8 (void) +{ + uint8x16x2_t out_uint8x16x2_t; + uint8x16_t arg0_uint8x16_t; + uint8x16_t arg1_uint8x16_t; + + out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c new file mode 100644 index 000000000..6c13a07ad --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c @@ -0,0 +1,21 @@ +/* Test the `vzipf32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipf32 (void) +{ + float32x2x2_t out_float32x2x2_t; + float32x2_t arg0_float32x2_t; + float32x2_t arg1_float32x2_t; + + out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c new file mode 100644 index 000000000..726500ed3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c @@ -0,0 +1,21 @@ +/* Test the `vzipp16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipp16 (void) +{ + poly16x4x2_t out_poly16x4x2_t; + poly16x4_t arg0_poly16x4_t; + poly16x4_t arg1_poly16x4_t; + + out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c new file mode 100644 index 000000000..4a5dd76b0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c @@ -0,0 +1,21 @@ +/* Test the `vzipp8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipp8 (void) +{ + poly8x8x2_t out_poly8x8x2_t; + poly8x8_t arg0_poly8x8_t; + poly8x8_t arg1_poly8x8_t; + + out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c new file mode 100644 index 000000000..795bab6d3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c @@ -0,0 +1,21 @@ +/* Test the `vzips16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips16 (void) +{ + int16x4x2_t out_int16x4x2_t; + int16x4_t arg0_int16x4_t; + int16x4_t arg1_int16x4_t; + + out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c new file mode 100644 index 000000000..663985ebe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c @@ -0,0 +1,21 @@ +/* Test the `vzips32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips32 (void) +{ + int32x2x2_t out_int32x2x2_t; + int32x2_t arg0_int32x2_t; + int32x2_t arg1_int32x2_t; + + out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c new file mode 100644 index 000000000..cca6933aa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c @@ -0,0 +1,21 @@ +/* Test the `vzips8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzips8 (void) +{ + int8x8x2_t out_int8x8x2_t; + int8x8_t arg0_int8x8_t; + int8x8_t arg1_int8x8_t; + + out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c new file mode 100644 index 000000000..53822f93a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c @@ -0,0 +1,21 @@ +/* Test the `vzipu16' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu16 (void) +{ + uint16x4x2_t out_uint16x4x2_t; + uint16x4_t arg0_uint16x4_t; + uint16x4_t arg1_uint16x4_t; + + out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); +} + +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c new file mode 100644 index 000000000..d9a280bf4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c @@ -0,0 +1,21 @@ +/* Test the `vzipu32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu32 (void) +{ + uint32x2x2_t out_uint32x2x2_t; + uint32x2_t arg0_uint32x2_t; + uint32x2_t arg1_uint32x2_t; + + out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); +} + +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c new file mode 100644 index 000000000..056898939 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c @@ -0,0 +1,21 @@ +/* Test the `vzipu8' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vzipu8 (void) +{ + uint8x8x2_t out_uint8x8x2_t; + uint8x8_t arg0_uint8x8_t; + uint8x8_t arg1_uint8x8_t; + + out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); +} + +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c new file mode 100644 index 000000000..9dac3043e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-fno-omit-frame-pointer -mapcs-frame -O" } */ + +extern void abort (void); + +struct x +{ + int y; + int z; +}; + +int __attribute__((noinline)) f (int c, int d, int e, int h, int i) +{ + int a; + struct x b; + + int __attribute__((noinline)) g (int p, int q, int r, struct x s) + { + return a + p + q + r + s.y + s.z; + } + + a = 5; + b.y = h; + b.z = i; + + return g(c, d, e, b); +} + +int main(void) +{ + if (f (1, 2, 3, 4, 5) != 20) + abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c new file mode 100644 index 000000000..1be162e05 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +int +foo (int a, short b, short c) +{ + int bc = b * c; + return a + (short)bc; +} + +/* { dg-final { scan-assembler "\tmul\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c new file mode 100644 index 000000000..eb2b86ee7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_prefer_ldrd_strd } */ +/* { dg-options "-O2" } */ +int foo(int a, int b, int* p, int *q) +{ + a = p[2] + p[3]; + *q = a; + *p = a; + return a; +} +/* { dg-final { scan-assembler "ldrd" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c new file mode 100644 index 000000000..bd3307695 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_prefer_ldrd_strd } */ +/* { dg-options "-O2" } */ +void foo(int a, int b, int* p) +{ + p[2] = a; + p[3] = b; +} +/* { dg-final { scan-assembler "strd" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c new file mode 100644 index 000000000..c3ee22017 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c @@ -0,0 +1,10 @@ +/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" "-mthumb" } { "" } } */ +/* { dg-options "-O2 -march=armv5te -marm" } */ +/* { dg-final { scan-assembler "bx" } } */ + +int (*indirect_func)(); + +int indirect_call() +{ + return indirect_func(); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c new file mode 100644 index 000000000..3d353244c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c @@ -0,0 +1,24 @@ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-Os -fpic" } */ +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ + +struct S +{ + int count; + char *addr; +}; + +void func(const char*, const char*, int, const char*); + +/* This function should not need to spill to the stack. */ +void test(struct S *p) +{ + int off = p->count; + while (p->count >= 0) + { + const char *s = "xyz"; + if (*p->addr) s = "pqr"; + func("abcde", p->addr + off, off, s); + p->count--; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c new file mode 100644 index 000000000..44122bb2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-Os" } */ +/* { dg-do compile } */ + +int bar(int* p) +{ + int x = p[0] + p[1]; + return x; +} + +/* { dg-final { scan-assembler "ldrd|ldm" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c new file mode 100644 index 000000000..31624d351 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +void foo(int* p) +{ + p[0] = 1; + p[1] = 0; +} + +/* { dg-final { scan-assembler "strd|stm" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c new file mode 100644 index 000000000..81f6a424c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c @@ -0,0 +1,10 @@ +/* { dg-options "-Os" } */ +/* { dg-do compile } */ + +void foo(int* p) +{ + p[0] = 1; + p[1] = 0; +} + +/* { dg-final { scan-assembler "strd|stm" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c new file mode 100644 index 000000000..6926e6fc8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c @@ -0,0 +1,8 @@ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-final { scan-assembler-not "ldr" } } */ + +unsigned int foo (unsigned int i ) +{ + return i | 0xff000000; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c new file mode 100644 index 000000000..a6ac6c78a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -march=armv5te -mthumb" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler "pop.*r1.*pc" } } */ +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ + +extern void bar(int*); +int foo() +{ + int x; + bar(&x); + return x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c new file mode 100644 index 000000000..afd469a76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c @@ -0,0 +1,20 @@ +/* { dg-options "-Os -mthumb" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ + +/* Here, we test that if there's a pop of r[4567] in the epilogue, + add sp,sp,#12 is removed and replaced by three additional pops + of lower-numbered regs. */ + +extern void bar(int*); + +int t1, t2, t3, t4, t5; +int foo() +{ + int i,j,k,x = 0; + for (i = 0; i < t1; i++) + for (j = 0; j < t2; j++) + bar(&x); + return x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c new file mode 100644 index 000000000..24786385d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c @@ -0,0 +1,8 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "ldr" } } */ + +float foo (void) +{ + return 2.0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c new file mode 100644 index 000000000..76ad509eb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c @@ -0,0 +1,56 @@ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "cmp" } } */ + +int bar(); +void goo(int, int); + +void eq() +{ + int v = bar(); + if (v == 0) + return; + goo(1, v); +} + +void ge() +{ + int v = bar(); + if (v >= 0) + return; + goo(1, v); +} + +void gt() +{ + int v = bar(); + if (v > 0) + return; + goo(1, v); +} + +void lt() +{ + int v = bar(); + if (v < 0) + return; + goo(1, v); +} + +void le() +{ + int v = bar(); + if (v <= 0) + return; + goo(1, v); +} + +unsigned int foo(); + +void leu() +{ + unsigned int v = foo(); + if (v <= 0) + return; + goo(1, v); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c new file mode 100644 index 000000000..5cabe3ab7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c @@ -0,0 +1,10 @@ +/* { dg-skip-if "need at least armv5" { *-*-* } { "-march=armv[234]*" } { "" } } */ +/* { dg-options "-O2 -march=armv5te" } */ +/* { dg-final { scan-assembler "blx" } } */ + +int (*indirect_func)(int x); + +int indirect_call() +{ + return indirect_func(20) + indirect_func (40); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c new file mode 100644 index 000000000..278bc3702 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-optimize-sibling-calls" } */ + +extern short shortv2(); +short shortv1() +{ + return shortv2(); +} + +/* { dg-final { scan-assembler-not "lsl" } } */ +/* { dg-final { scan-assembler-not "asr" } } */ +/* { dg-final { scan-assembler-not "sxth" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c new file mode 100644 index 000000000..167cdc6ec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -fpic" } */ +/* { dg-require-effective-target fpic } */ +/* Make sure the constant "0" is loaded into register only once. */ +/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */ + +int foo(int p, int* q) +{ + if (p!=9) + *q = 0; + else + *(q+1) = 0; + return 3; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c new file mode 100644 index 000000000..7ba2f933e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c @@ -0,0 +1,51 @@ +/* { dg-options "-mthumb -O2 -fno-reorder-blocks" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler-not "tbb" } } */ +/* { dg-final { scan-assembler-not "tbh" } } */ + +#include <stdlib.h> + +int gbl; +int foo (int *buf, int n) +{ + int ctr = 0; + int c; + while (1) + { + c = buf[ctr++]; + switch (c) + { + case '\n': + gbl++; + break; + + case ' ': case '\t' : case '\f' : case '\r': + break; + + case ';': + do + c = buf [ctr++]; + while (c != '\n' && c != -1); + gbl++; + break; + + case '/': + { + int prevc; + c = buf [ctr++]; + if (c != '*') + abort (); + + prevc = 0; + while ((c = buf[ctr++]) && c != -1) + { + if (c == '\n') + gbl++; + } + break; + } + default: + return c; + } + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c new file mode 100644 index 000000000..207f6001f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c @@ -0,0 +1,19 @@ +/* { dg-options "-O2" } */ + +struct A { + unsigned int f1 : 3; + unsigned int f2 : 3; + unsigned int f3 : 1; + unsigned int f4 : 1; + +}; + +void init_A (struct A *this) +{ + this->f1 = 0; + this->f2 = 1; + this->f3 = 0; + this->f4 = 0; +} + +/* { dg-final { scan-assembler-times "ldr" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c new file mode 100644 index 000000000..582c8a2d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c @@ -0,0 +1,11 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */ +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */ + +#include <string.h> + +int foo (char *x) +{ + memset (x, 0, 6); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c new file mode 100644 index 000000000..7e08cf298 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c @@ -0,0 +1,31 @@ +/* { dg-options "-mthumb -Os -fpic -fdump-rtl-hoist" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-require-effective-target fpic } */ +/* Make sure all calculations of gObj's address get hoisted to one location. */ +/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */ + +struct st_a { + int data; +}; + +struct st_b { + struct st_a *p_a; + struct st_b *next; +}; + +extern struct st_b gObj; +extern void foo(int, struct st_b*); + +int goo(struct st_b * obj) { + struct st_a *pa; + if (gObj.p_a->data != 0) { + foo(gObj.p_a->data, obj); + } + pa = obj->p_a; + if (pa == 0) { + return 0; + } else if (pa == gObj.p_a) { + return 0; + } + return pa->data; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c new file mode 100644 index 000000000..c6d8a1f39 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c @@ -0,0 +1,16 @@ +/* { dg-options "-O2" } */ + +void foo(int i) +{ + extern int j; + + if (i) { + j = 10; + } + else { + j = 20; + } +} + +/* { dg-final { scan-assembler-not "strne" } } */ +/* { dg-final { scan-assembler-not "streq" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c new file mode 100644 index 000000000..5ddfea1da --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c @@ -0,0 +1,22 @@ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ + +struct A { + int f1; + int f2; +}; + +int func(int c); + +/* This function should not need to spill anything to the stack. */ +int test(struct A* src, struct A* dst, int count) +{ + while (count--) { + if (!func(src->f2)) { + return 0; + } + *dst++ = *src++; + } + + return 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c new file mode 100644 index 000000000..0ccd05f99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c @@ -0,0 +1,24 @@ +/* { dg-options "-mthumb -Os -fpic" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-require-effective-target fpic } */ +/* Make sure the address of glob.c is calculated only once and using + a logical shift for the offset (200<<1). */ +/* { dg-final { scan-assembler-times "lsl" 1 } } */ + +struct A { + char a[400]; + float* c; +}; +struct A glob; +void func(); +void func1(float*); +int func2(float*, int*); +void func3(float*); + +void test(int *p) { + func1(glob.c); + if (func2(glob.c, p)) { + func(); + } + func3(glob.c); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c new file mode 100644 index 000000000..1998e323d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* Make sure RA does good job allocating registers and avoids + unnecessary moves. */ +/* { dg-final { scan-assembler-not "mov" } } */ + +long long longfunc(long long x, long long y) +{ + return x * y; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c new file mode 100644 index 000000000..867dd0287 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os -fno-tree-tail-merge" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int foo(int *p, int i) +{ + return( (i < 0 && *p == 1) + || (i > 0 && *p == 2) ); +} + +/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */ +/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c new file mode 100644 index 000000000..9fcdad694 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c @@ -0,0 +1,19 @@ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-final { scan-assembler "lsls" } } */ + +struct A +{ +#ifdef __ARMEB__ + int dummy:31; +#endif + int v:1; +}; + +int bar(); +int foo(struct A* p) +{ + if (p->v) + return 1; + return bar(); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c new file mode 100644 index 000000000..3fb381227 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "mov\tr1, r\[1-9\]" } } */ + +int foo(); +long long bar22() +{ + int result = foo(); + return result; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c new file mode 100644 index 000000000..af382ba72 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c @@ -0,0 +1,28 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -save-temps -mthumb" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +extern int bar (); +extern void bar2 (int); + +int +foo4 () +{ + int result = 0; + int f = -1; + f = bar (); + if (f < 0) + { + result = 1; + goto bail; + } + bar (); + bail: + bar2 (f); + return result; +} + +/* { dg-final { scan-assembler-times "sub" 1 } } */ +/* { dg-final { scan-assembler-times "cmp" 0 } } */ +/* { dg-final { object-size text <= 30 } } */ +/* { dg-final { cleanup-saved-temps "pr43597" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c new file mode 100644 index 000000000..1fc497c22 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-Os" } */ +#include <stdint.h> +#include <stdlib.h> + + +char do_reverse_endian = 0; + +# define bswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) + +#define EGET(X) \ + (__extension__ ({ \ + uint64_t __res; \ + if (!do_reverse_endian) { __res = (X); \ + } else if (sizeof(X) == 4) { __res = bswap_32((X)); \ + } \ + __res; \ + })) + +void __attribute__((noinline)) X(char **phdr, char **data, int *phoff) +{ + *phdr = *data + EGET(*phoff); +} + +int main() +{ + char *phdr; + char *data = (char *)0x40164000; + int phoff = 0x34; + X(&phdr, &data, &phoff); + if (phdr != (char *)0x40164034) + abort (); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c new file mode 100644 index 000000000..d673f1e88 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +f (int start, int end, int *start_) +{ + if (start == -1 || end == -1) + return -1; + + if (end - start) + return -1; + + *start_ = start; + + return 0; +} + +/* { dg-final { scan-assembler-times "\torr" 0 } } */ +/* { dg-final { scan-assembler-times "\tit\t" 0 } } */ +/* { dg-final { scan-assembler "\tbeq" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c new file mode 100644 index 000000000..f647165bd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c @@ -0,0 +1,30 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os -save-temps" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +#include <stdio.h> + +int getFileStartAndLength (int fd, int *start_, size_t *length_) +{ + int start, end; + size_t length; + + start = lseek (fd, 0L, SEEK_CUR); + end = lseek (fd, 0L, SEEK_END); + + if (start == -1 || end == -1) + return -1; + + length = end - start; + if (length == 0) + return -1; + + *start_ = start; + *length_ = length; + + return 0; +} + +/* { dg-final { scan-assembler-times "pop" 2 } } */ +/* { dg-final { scan-assembler-times "beq" 3 } } */ +/* { dg-final { object-size text <= 54 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c new file mode 100644 index 000000000..eb4bc11af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ + +void joint_decode(float* mlt_buffer1, int t) { + int i; + float decode_buffer[1060]; + foo(decode_buffer); + for (i=0; i<10 ; i++) { + mlt_buffer1[i] = i * decode_buffer[t]; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c new file mode 100644 index 000000000..d07dca1a0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c @@ -0,0 +1,9 @@ +/* Use UXTB to extract the lowest byte. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "uxtb" } } */ + +int tp(int x, int y) +{ + return (x & 0xff) - (y & 0xffff); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c new file mode 100644 index 000000000..f35e7bb2d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2 -mcpu=cortex-a8" } */ +/* { dg-add-options arm_neon } */ + +#include <stdlib.h> + +long long buffer[32]; + +void __attribute__((noinline)) f(long long *p, int n) +{ + while (--n >= 0) + { + *p = 1; + p += 32; + } +} + +int main(void) +{ + f(buffer, 1); + + if (!buffer[0]) + abort(); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c new file mode 100644 index 000000000..cb4a44275 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c @@ -0,0 +1,3 @@ +/* { dg-do compile } */ +/* { dg-options "-g -femit-struct-debug-baseonly" } */ +typedef __builtin_va_list x; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c new file mode 100644 index 000000000..2c690d5bc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-final { scan-assembler "push\t\{r3" } } */ +/* { dg-final { scan-assembler-not "r8" } } */ + +extern int hist_verify; +extern char *pre_process_line (char*); +extern char* str_cpy (char*, char*); +extern int str_len (char*); +extern char* x_malloc (int); +#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x)) + +char * +history_expand_line_internal (char* line) +{ + char *new_line; + int old_verify; + + old_verify = hist_verify; + hist_verify = 0; + new_line = pre_process_line (line); + hist_verify = old_verify; + return (new_line == line) ? savestring (line) : new_line; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c new file mode 100644 index 000000000..ee1ee7df0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-final { scan-assembler "push\t\{r3" } } */ +/* { dg-final { scan-assembler-not "r8" } } */ + +extern int hist_verify; +extern char *pre_process_line (char*); +extern char* savestring1 (char*, char*); +extern char* str_cpy (char*, char*); +extern int str_len (char*); +extern char* x_malloc (int); +#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x)) + +char * +history_expand_line_internal (char* line) +{ + char *new_line; + int old_verify; + + old_verify = hist_verify; + hist_verify = 0; + new_line = pre_process_line (line); + hist_verify = old_verify; + /* Two tail calls here, but r3 is not used to pass values. */ + return (new_line == line) ? savestring (line) : savestring1 (new_line, line); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c new file mode 100644 index 000000000..452c398f9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-final { scan-assembler "push\t.*r8" } } */ +/* { dg-final { scan-assembler-not "push\t*r3" } } */ + +extern int hist_verify; +extern char *pre_process_line (char*); +extern char* savestring1 (char*, char*, int, int); +extern char* str_cpy (char*, char*); +extern int str_len (char*); +extern char* x_malloc (int); +#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x)) + +char * +history_expand_line_internal (char* line) +{ + char *new_line; + int old_verify; + + old_verify = hist_verify; + hist_verify = 0; + new_line = pre_process_line (line); + hist_verify = old_verify; + /* Two tail calls here, but r3 is used to pass values. */ + return (new_line == line) ? savestring (line) : + savestring1 (new_line, line, 0, old_verify+1); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c new file mode 100644 index 000000000..9dd939c7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +int __attribute__ ((vector_size (32))) x; +void +foo (void) +{ + x <<= x; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c new file mode 100644 index 000000000..6f6dc4e85 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c @@ -0,0 +1,16 @@ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "ands" } } */ + +struct S { + int bi_buf; + int bi_valid; +}; + +int tz (struct S* p, int bits, int value) +{ + if (p == 0) return 1; + p->bi_valid = bits; + p->bi_buf = value & ((1 << bits) - 1); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c new file mode 100644 index 000000000..223676946 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c @@ -0,0 +1,26 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler-not "-32768" } } */ + +typedef union +{ + unsigned long int u_32_value; + struct + { + unsigned short int u_16_value_0; + unsigned short int u_16_value_1; + } u_16_values; +} my_union; + + +unsigned long int Test(const unsigned short int wXe) +{ + my_union dwCalcVal; + + dwCalcVal.u_16_values.u_16_value_0=wXe; + dwCalcVal.u_16_values.u_16_value_1=0x8000u; + + dwCalcVal.u_32_value /=3; + + return (dwCalcVal.u_32_value); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c new file mode 100644 index 000000000..f4017e3f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "sub" } } */ +/* { dg-final { scan-assembler "clz" } } */ +/* { dg-final { scan-assembler "lsr.*#5" } } */ + +int foo (int s) +{ + return s == 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c new file mode 100644 index 000000000..60d773b1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c @@ -0,0 +1,9 @@ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "subs" } } */ +/* { dg-final { scan-assembler "adcs" } } */ + +int foo (int s) +{ + return s == 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c new file mode 100644 index 000000000..f021825b1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c @@ -0,0 +1,25 @@ +/* testsuite/gcc.target/arm/pr48183.c */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O -g" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n) +{ + unsigned i; + int16x4x2_t input; + int32x4x2_t mid; + int32x4x2_t output; + + for (i = 0; i < n/2; i += 8) { + input = vld2_s16(src + i); + mid.val[0] = vmovl_s16(input.val[0]); + mid.val[1] = vmovl_s16(input.val[1]); + output.val[0] = vshlq_n_s32(mid.val[0], 8); + output.val[1] = vshlq_n_s32(mid.val[1], 8); + vst2q_s32((int32_t *)dst + i, output); + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c new file mode 100644 index 000000000..17f729bb3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main(void) +{ + uint8_t v1_init[8] = {1, 1, 1, 1, 1, 1, 1, 1}; + uint8_t v2_init[8] = {2, 2, 2, 2, 2, 2, 2, 2}; + uint8x8_t v1 = vld1_u8 (v1_init); + uint8x8_t v2 = vld1_u8 (v2_init); + uint8x8x2_t vd1, vd2; + union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4; + int i; + uint8_t odd, even; + + vd1 = vzip_u8(v1, vdup_n_u8(0)); + vd2 = vzip_u8(v2, vdup_n_u8(0)); + + vst1_u8(d1.buf, vd1.val[0]); + vst1_u8(d2.buf, vd1.val[1]); + vst1_u8(d3.buf, vd2.val[0]); + vst1_u8(d4.buf, vd2.val[1]); + +#ifdef __ARMEL__ + odd = 1; + even = 0; +#else + odd = 0; + even = 1; +#endif + + for (i = 0; i < 8; i++) + if ((i % 2 == even && d4.buf[i] != 2) + || (i % 2 == odd && d4.buf[i] != 0)) + abort (); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c new file mode 100644 index 000000000..7f9b3769c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */ +typedef struct { + void *t1, *t2, *t3; +} z; +extern volatile int y; +static inline void foo(z *x) { + x->t1 = &x->t2; + x->t2 = ((void *)0); + x->t3 = &x->t1; +} +extern z v; +void bar (void) { + y = 0; + foo(&v); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c new file mode 100644 index 000000000..c0d143dd5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long long foo (signed char * arg) +{ + long long temp_1; + + temp_1 = arg[256]; + return temp_1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c new file mode 100644 index 000000000..2f6ad5cfe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */ + +struct event { + unsigned long long id; + unsigned int flag; +}; + +void dummy(void) +{ + /* This is here to ensure that the offset of perf_event_id below + relative to the LANCHOR symbol exceeds the allowed displacement. */ + static int __warned[300]; + __warned[0] = 1; +} + +extern void *kmem_cache_alloc_trace (void *cachep); +extern void *cs_cachep; +extern int nr_cpu_ids; + +struct event * +event_alloc (int cpu) +{ + static unsigned long long __attribute__((aligned(8))) perf_event_id; + struct event *event; + unsigned long long result; + unsigned long tmp; + + if (cpu >= nr_cpu_ids) + return 0; + + event = kmem_cache_alloc_trace (cs_cachep); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + __asm__ __volatile__("@ atomic64_add_return\n" +"1: ldrexd %0, %H0, [%3]\n" +" adds %0, %0, %4\n" +" adc %H0, %H0, %H4\n" +" strexd %1, %0, %H0, [%3]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id) + : "r" (&perf_event_id), "r" (1LL) + : "cc"); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + event->id = result; + + if (cpu) + event->flag = 1; + + for (cpu = 0; cpu < nr_cpu_ids; cpu++) + kmem_cache_alloc_trace (cs_cachep); + + return event; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c new file mode 100644 index 000000000..be270eefa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long test (unsigned int sec, unsigned long long nsecs) +{ + return (long long)(long)sec * 1000000000L + (long long)(unsigned + long)nsecs; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c new file mode 100644 index 000000000..6d462d915 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-skip-if "avoid conflicting -mfpu" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv4-sp-d16" "-mfpu=vfpv3xd" "-mfpu=vfpv3xd-fp16" } } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=hard -mfpu=fpv4-sp-d16" } */ + +int func1 (double d) +{ + return (int)d; +} +unsigned int func2 (double d) +{ + return (unsigned int)d; +} + +/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */ +/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c new file mode 100644 index 000000000..144d522f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c @@ -0,0 +1,15 @@ +/* PR target/51915 */ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ + +struct S { int s1; void *s2; }; +struct T { struct S t1; unsigned long long t2; }; +struct S *foo (unsigned long long); + +struct S * +bar (struct S *x) +{ + return foo (((struct T *) x)->t2); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c new file mode 100644 index 000000000..f0506c267 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c @@ -0,0 +1,32 @@ +/* PR target/51968 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ +/* { dg-require-effective-target arm_neon_ok } */ + +typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8))); +typedef __builtin_neon_qi int8x16_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_hi int16x8_t __attribute__ ((__vector_size__ (16))); +typedef __builtin_neon_si int32x4_t __attribute__ ((__vector_size__ (16))); +struct T { int8x8_t val[2]; }; +int y; + +void +foo (int8x8_t z, int8x8_t x, int16x8_t b, int8x8_t n) +{ + if (y) + { + struct T m; + __builtin_neon_vuzpv8qi (&m.val[0], z, x); + } + for (;;) + { + int8x16_t g; + int8x8_t h, j, k; + struct T m; + j = __builtin_neon_vqmovunv8hi (b, 1); + g = __builtin_neon_vcombinev8qi (j, h); + k = __builtin_neon_vget_lowv16qi (g); + __builtin_neon_vuzpv8qi (&m.val[0], k, n); + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c new file mode 100644 index 000000000..c274449ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c @@ -0,0 +1,21 @@ +/* PR target/52006 */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicts with multilib flags" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2 -fPIC" } */ + +unsigned long a; +static int b; + +void +foo (void) +{ + asm volatile ("" : "=r" (b)); +} + +void +bar (float f) +{ + if (f < b / 100.0) + a = 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c new file mode 100644 index 000000000..0405c6685 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c @@ -0,0 +1,15 @@ +/* PR target/52375 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -O -ftree-vectorize" } */ + +struct C { int c, d; }; + +unsigned +foo (struct C *p) +{ + unsigned int b = 0, i; + for (i = 0; i < 64; i++) + b |= 0x80000000U >> p[i].c; + return b; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c new file mode 100644 index 000000000..b904d59d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c @@ -0,0 +1,13 @@ +/* PR tree-optimization/52633 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */ + +void +test (unsigned short *x, signed char *y) +{ + int i; + for (i = 0; i < 32; i++) + x[i] = (short) (y[i] << 5); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c new file mode 100644 index 000000000..66cbc575e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c @@ -0,0 +1,19 @@ +/* PR target/52375 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */ + +unsigned int output[4]; + +void test (unsigned short *p) +{ + unsigned int x = *p; + if (x) + { + output[0] = x << 1; + output[1] = x << 1; + output[2] = x << 1; + output[3] = x << 1; + } +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c new file mode 100644 index 000000000..b40dbbb31 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c @@ -0,0 +1,15 @@ +/* PR target/53187 */ +/* { dg-do compile } */ +/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ +/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ + +void bar (int); + +void +foo (int x, double y, double z) +{ + _Bool t = z >= y; + if (!t || x) + bar (t ? 1 : 16); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c new file mode 100644 index 000000000..dc094180c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-final { scan-assembler-not "mov" } } */ + +void t0p(long long * p) +{ + *p += 0x100000001; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c new file mode 100644 index 000000000..9a2b0315c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-final { scan-assembler-not "mov" } } */ + +void t0p(long long * p) +{ + *p -= 0x100000008; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c new file mode 100644 index 000000000..8e48f119b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-final { scan-assembler-not "mov" } } */ + + +void t0p(long long * p) +{ + *p +=0x1fffffff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c new file mode 100644 index 000000000..22acb9727 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c @@ -0,0 +1,9 @@ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-final { scan-assembler-not "mov" } } */ + + +void t0p(long long * p) +{ + *p -=0x1fffffff8; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c new file mode 100644 index 000000000..dbad7957e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +void fill (short *buf) __attribute__ ((noinline)); +void fill (short *buf) +{ + int i; + + for (i = 0; i < 11 * 8; i++) + buf[i] = i; +} + +void test (unsigned char *dst) __attribute__ ((noinline)); +void test (unsigned char *dst) +{ + short tmp[11 * 8], *tptr; + int i; + + fill (tmp); + + tptr = tmp; + for (i = 0; i < 8; i++) + { + dst[0] = (-tptr[0] + 9 * tptr[0 + 1] + 9 * tptr[0 + 2] - tptr[0 + 3]) >> 7; + dst[1] = (-tptr[1] + 9 * tptr[1 + 1] + 9 * tptr[1 + 2] - tptr[1 + 3]) >> 7; + dst[2] = (-tptr[2] + 9 * tptr[2 + 1] + 9 * tptr[2 + 2] - tptr[2 + 3]) >> 7; + dst[3] = (-tptr[3] + 9 * tptr[3 + 1] + 9 * tptr[3 + 2] - tptr[3 + 3]) >> 7; + dst[4] = (-tptr[4] + 9 * tptr[4 + 1] + 9 * tptr[4 + 2] - tptr[4 + 3]) >> 7; + dst[5] = (-tptr[5] + 9 * tptr[5 + 1] + 9 * tptr[5 + 2] - tptr[5 + 3]) >> 7; + dst[6] = (-tptr[6] + 9 * tptr[6 + 1] + 9 * tptr[6 + 2] - tptr[6 + 3]) >> 7; + dst[7] = (-tptr[7] + 9 * tptr[7 + 1] + 9 * tptr[7 + 2] - tptr[7 + 3]) >> 7; + + dst += 8; + tptr += 11; + } +} + +int main (void) +{ + char buf [8 * 8]; + + test (buf); + + return 0; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c new file mode 100644 index 000000000..003489e0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c @@ -0,0 +1,11 @@ +/* PR target/53859 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-mcpu=cortex-m4 -mthumb -O2" } */ + +void bar (int,int,char* ,int); + +void foo (char c) +{ + bar (1,2,&c,3); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c new file mode 100644 index 000000000..1d2e93c89 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +int32_t a __attribute__ ((aligned (64))); + +int32x2x3_t test (void) +{ + return vld3_dup_s32 (&a); +} + +int32x2x3_t test1 (void) +{ + int32x2x3_t res ; + return vld3_lane_s32 (&a, res, 1); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C new file mode 100644 index 000000000..eb1a74e36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +#include <stdlib.h> + +struct __attribute__ ((aligned(8))) _v16u8_ { + uint8x16_t val; + _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); } + operator int16x8_t () const { return vreinterpretq_s16_u8(val); } +}; +typedef struct _v16u8_ v16u8; + +struct __attribute__ ((aligned(4))) _v8u8_ { + uint8x8_t val; + _v8u8_( const uint8x8_t &src) { val = src; } + operator int16x4_t () const { return vreinterpret_s16_u8(val); } +}; +typedef struct _v8u8_ v8u8; + +typedef v16u8 v8i16; +typedef int32x4_t v4i32; +typedef const short cv1i16; +typedef const unsigned char cv1u8; +typedef const v8i16 cv8i16; + +static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); } + +static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){ + return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() ); +} +static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){ + return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) ); +} + +void __attribute__((noinline)) +test(unsigned short *_Inp, int32_t *_Out, + unsigned int s1v, unsigned int dv0, + unsigned int smask_v) +{ + int32x4_t c = vdupq_n_s32(0); + + for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v ) + { + int32x4_t s; + s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) ); + c = vaddq_s32( c, s ); + } + vst1q_s32( _Out, c ); +} + +main() +{ + unsigned short a[4] = {1, 2, 3, 4}; + int32_t b[4] = {0, 0, 0, 0}; + test(a, b, 1, 1, ~0); + if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4) + abort(); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c new file mode 100644 index 000000000..a7fe1bc66 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +int set_role(unsigned char role_id, short m_role) +{ + return __sync_bool_compare_and_swap(&m_role, -1, role_id); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C new file mode 100644 index 000000000..5575cf779 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +#include <stdlib.h> + +struct __attribute__((aligned(16))) _v16u8_ { + uint8x16_t val; + _v16u8_() { } + + _v16u8_( const uint8x16_t &src) { val = src; } + _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); } + _v16u8_( const uint32x4_t &src) { val = vreinterpretq_u8_u32(src); } + + operator uint8x16_t () const { return val; } + operator int8x16_t () const { return vreinterpretq_s8_u8 (val); } + operator int16x8_t () const { return vreinterpretq_s16_u8(val); } + operator uint32x4_t () const { return vreinterpretq_u32_u8(val); } + operator int32x4_t () const { return vreinterpretq_s32_u8(val); } +}; +typedef struct _v16u8_ v16u8; +typedef const v16u8 cv16u8; + +typedef v16u8 v16i8; +typedef v16u8 v8i16; +typedef v16u8 v4u32; + +inline v16u8 __attribute__((always_inline)) mergelo( const v16u8 & s, const v16u8 & t ) +{ + uint8x8x2_t r = vzip_u8( vget_low_u8(s), vget_low_u8(t) ); + return vcombine_u8( r.val[0], r.val[1] ); +} + +inline v8i16 __attribute__((always_inline)) unpacklo(const v16i8 & s) +{ + return vmovl_s8( vget_low_s8( s ) ); +} + +const uint32_t __attribute__((aligned(16))) _InA [4] = { 0xFF020001, 0xFF020001, 0xFF000101, 0xFF000101 } ; +const uint32_t __attribute__((aligned(16))) _InB [4] = { 0xFF050002, 0xFF050002, 0xFF000303, 0xFF000203 } ; + +__attribute__((noinline)) v16i8 test_func(void) +{ + v16u8 A = vld1q_u8( (uint8_t*) _InA ); + v16u8 B = vld1q_u8( (uint8_t*) _InB ); + v8i16 r = vdupq_n_s16(2); + + v16u8 _0 = mergelo( A, B ); + v16u8 _1 = mergelo( B, A ); + + v16u8 _2 = mergelo( _0, _1 ); + v16u8 _3 = mergelo( _1, _0 ); + + v8i16 _4 = vsubq_s16( unpacklo( _2 ), r ); + v8i16 _5 = vsubq_s16( unpacklo( _3 ), r ); + + v8i16 ret = vaddq_s16( _4, _5 ); + + return ( ret ); +} + +int main (int argc, char **argv) +{ + v16u8 val = test_func(); + + if (vgetq_lane_u32( val, 0 ) != 0xffffffff + || vgetq_lane_u32( val, 1 ) != 0xffffffff + || vgetq_lane_u32( val, 2 ) != 0xfffcfffc + || vgetq_lane_u32( val, 3 ) != 0xfffcfffc) + abort (); + exit (0); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c new file mode 100644 index 000000000..10f2daa25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c @@ -0,0 +1,15 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo (int v) +{ + register int i asm ("r0"); + register int j asm ("r1"); + if (v > 1) + i = abs (j); + + return i; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C new file mode 100644 index 000000000..d44c1b432 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C @@ -0,0 +1,257 @@ +/* { dg-do compile } */ +/* { dg-options "-fno-short-enums -O2 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=softfp -mtune=cortex-a9 -fno-section-anchors" } */ + +typedef unsigned int size_t; +__extension__ typedef int __intptr_t; +typedef __intptr_t intptr_t; +typedef union tree_node *tree; +typedef const union tree_node *const_tree; +extern void *ggc_internal_cleared_alloc_stat (size_t ) + __attribute__ ((__malloc__)); +enum tree_code { +TREE_LIST=2, +FUNCTION_DECL, +MAX_TREE_CODES=254 +}; +extern unsigned char tree_contains_struct[MAX_TREE_CODES][64]; +struct tree_base { + enum tree_code code : 16; +}; +struct tree_common { + tree chain; +}; +enum tree_node_structure_enum { +TS_COMMON, +TS_DECL_COMMON, +}; +extern void tree_contains_struct_check_failed (const_tree, + const enum tree_node_structure_enum, + const char *, int, const char *) + __attribute__ ((__noreturn__)); +extern void tree_check_failed (const_tree, const char *, int, const char *, + ...) __attribute__ ((__noreturn__)); +struct tree_list { + tree value; +}; +struct tree_decl_common { + tree initial; +}; +struct tree_function_decl { + struct function *f; +}; +union + tree_node { + struct tree_base base; + struct tree_common common; + struct tree_decl_common decl_common; + struct tree_function_decl function_decl; + struct tree_list list; +}; +inline tree +tree_check (tree __t, const char *__f, int __l, const char *__g, enum tree_code __c) +{ + if (((enum tree_code) (__t)->base.code) != __c) + tree_check_failed (__t, __f, __l, __g, __c, 0); +} +inline tree +contains_struct_check (tree __t, const enum tree_node_structure_enum __s, + const char *__f, int __l, const char *__g) +{ + if (tree_contains_struct[((enum tree_code) (__t)->base.code)][__s] != 1) + tree_contains_struct_check_failed (__t, __s, __f, __l, __g); +} +struct function { + tree static_chain_decl; +}; +enum gimple_code { + LAST_AND_UNUSED_GIMPLE_CODE +}; +struct eh_catch_d +{ + struct eh_catch_d *next_catch; + struct eh_catch_d *prev_catch; + tree type_list; + tree filter_list; + tree label; +}; +struct eh_region_d +{ + struct eh_region_d *outer; + struct eh_region_d *inner; + int index; + union eh_region_u { + struct eh_region_u_try { + struct eh_catch_d *first_catch; + } eh_try; + } u; +}; +typedef struct eh_catch_d *eh_catch; +typedef struct eh_region_d *eh_region; +extern void add_type_for_runtime (tree); +enum LTO_tags +{ + LTO_null = 0, + LTO_bb0 = 1 + MAX_TREE_CODES + LAST_AND_UNUSED_GIMPLE_CODE, + LTO_ert_cleanup, + LTO_NUM_TAGS +}; +enum lto_section_type +{ + LTO_section_function_body, +}; +struct lto_input_block +{ + const char *data; + unsigned int p; + unsigned int len; +}; +extern void lto_section_overrun (struct lto_input_block *) __attribute__ ((__noreturn__)); +extern void lto_value_range_error (const char *, + long long, long long, + long long) __attribute__ ((__noreturn__)); +long long streamer_read_hwi (struct lto_input_block *); +static inline unsigned char +streamer_read_uchar (struct lto_input_block *ib) +{ + if (ib->p >= ib->len) + lto_section_overrun (ib); + return (ib->data[ib->p++]); +} +static inline long long +streamer_read_hwi_in_range (struct lto_input_block *ib, + const char *purpose, + long long min, + long long max) +{ + long long range = max - min; + long long val = streamer_read_uchar (ib); + if (range >= 0xff) + val |= ((long long)streamer_read_uchar (ib)) << 8; + if (val < min || val > max) + lto_value_range_error (purpose, val, min, max); + return val; +} +static inline enum LTO_tags +streamer_read_record_start (struct lto_input_block *ib) +{ + return (enum LTO_tags)streamer_read_hwi_in_range ((ib), "LTO_tags", 0, (int)(LTO_NUM_TAGS) - 1); +} +struct streamer_hooks { + tree (*read_tree) (struct lto_input_block *, struct data_in *); +}; +extern struct streamer_hooks streamer_hooks; +static struct eh_catch_d * +lto_input_eh_catch_list (struct lto_input_block *ib, struct data_in *data_in, + eh_catch *last_p) +{ + eh_catch first; + enum LTO_tags tag; + *last_p = first = __null; + tag = streamer_read_record_start (ib); + while (tag) + { + tree list; + eh_catch n; + n = ((struct eh_catch_d *)(ggc_internal_cleared_alloc_stat (sizeof (struct eh_catch_d) ))); + n->type_list = streamer_hooks.read_tree(ib, data_in); + n->filter_list = streamer_hooks.read_tree(ib, data_in); + n->label = streamer_hooks.read_tree(ib, data_in); + for (list = n->filter_list; list; list = ((contains_struct_check ((list), (TS_COMMON), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 275, __FUNCTION__))->common.chain)) + add_type_for_runtime (((tree_check ((list), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 276, __FUNCTION__, (TREE_LIST)))->list.value)); + if (*last_p) + (*last_p)->next_catch = n; + n->prev_catch = *last_p; + *last_p = n; + if (first == __null) + first = n; + tag = streamer_read_record_start (ib); + } + return first; +} +static eh_region +input_eh_region (struct lto_input_block *ib, struct data_in *data_in, int ix) +{ + enum LTO_tags tag; + eh_region r; + tag = streamer_read_record_start (ib); + if (tag == LTO_null) + return __null; + r = ((struct eh_region_d *)(ggc_internal_cleared_alloc_stat (sizeof (struct eh_region_d) ))); + r->index = streamer_read_hwi (ib); + r->outer = (eh_region) (intptr_t) streamer_read_hwi (ib); + r->inner = (eh_region) (intptr_t) streamer_read_hwi (ib); + switch (tag) + { + case LTO_ert_cleanup: + { + struct eh_catch_d *last_catch; + r->u.eh_try.first_catch = lto_input_eh_catch_list (ib, data_in, + &last_catch); + } + { + tree l; + add_type_for_runtime (((tree_check ((l), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 346, __FUNCTION__, (TREE_LIST)))->list.value)); + } + } +} +static void +input_eh_regions (struct lto_input_block *ib, struct data_in *data_in, + struct function *fn) +{ + long long i, root_region, len; + enum LTO_tags tag; + tag = streamer_read_record_start (ib); + if (tag == LTO_null) + return; + len = streamer_read_hwi (ib); + if (len > 0) + { + for (i = 0; i < len; i++) + { + eh_region r = input_eh_region (ib, data_in, i); + } + } +} +static void +input_ssa_names (struct lto_input_block *ib, struct data_in *data_in, + struct function *fn) +{ + unsigned int i, size; + while (i) + { + } +} +static void +input_struct_function_base (struct function *fn, struct data_in *data_in, + struct lto_input_block *ib) +{ + fn->static_chain_decl = streamer_hooks.read_tree(ib, data_in); +} +static void +input_function (tree fn_decl, struct data_in *data_in, + struct lto_input_block *ib) +{ + struct function *fn; + enum LTO_tags tag; + fn = ((tree_check ((fn_decl), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 807, __FUNCTION__, (FUNCTION_DECL)))->function_decl.f); + tag = streamer_read_record_start (ib); + input_struct_function_base (fn, data_in, ib); + input_ssa_names (ib, data_in, fn); + input_eh_regions (ib, data_in, fn); + ((contains_struct_check ((fn_decl), (TS_DECL_COMMON), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 823, __FUNCTION__))->decl_common.initial) = streamer_hooks.read_tree(ib, data_in); +} +static void +lto_read_body (struct lto_file_decl_data *file_data, tree fn_decl, + const char *data, enum lto_section_type section_type) +{ + struct data_in *data_in; + struct lto_input_block ib_main; + input_function (fn_decl, data_in, &ib_main); +} +void +lto_input_function_body (struct lto_file_decl_data *file_data, + tree fn_decl, const char *data) +{ + lto_read_body (file_data, fn_decl, data, LTO_section_function_body); +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c new file mode 100644 index 000000000..ac8b8cf67 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target naked_functions } */ +/* { dg-options "-O2 -Wall" } */ +extern void bar(); + +void __attribute__((__naked__)) +foo(void) +{ + bar (); +} + +int __attribute__((naked)) +zoo (int a, int b, int c, int d, int e, int f) +{ + bar (); + return e; +} +/* Verify that __attribute__((naked)) produces a naked function that + does not use bx to return. */ +/* { dg-final { scan-assembler-not "\tbx\tlr" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c new file mode 100644 index 000000000..2b9bfdded --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c @@ -0,0 +1,206 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline" } */ + +typedef struct _GtkCssStyleProperty GtkCssStyleProperty; + +struct _GtkCssStyleProperty +{ + int *initial_value; + unsigned int id; + unsigned int inherit :1; + unsigned int animated :1; + unsigned int affects_size :1; + unsigned int affects_font :1; + + int * parse_value; + int * query_value; + int * assign_value; +}; + +void +g_assertion_message_expr (const char *domain, + const char *file, + int line, + const char *func, + const char *expr) __attribute__((__noreturn__)); + +void +g_assertion_message_expr (const char *domain, + const char *file, + int line, + const char *func, + const char *expr) +{ + __builtin_abort (); +} +int +get_id (GtkCssStyleProperty *property) +{ + return 1; +} +int +_gtk_css_style_property_get_type () +{ + return 1; +} + +GtkCssStyleProperty * +g_object_new (int object_type, + const char *first_property_name, + ...) +{ + return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty)); +} + +typedef enum { + INHERIT = (1 << 0), + ANIMATED = (1 << 1), + RESIZE = (1 << 2), + FONT = (1 << 3) +} GtkStylePropertyFlags; + +int t = 0; +void +gtk_css_style_property_register (const char * name, + int expected_id, + int value_type, + int flags, + int *parse_value, + int *query_value, + int *assign_value, + int *initial_value) +{ + GtkCssStyleProperty *node; + + do + { + if (__builtin_expect (__extension__ ( + { + int _g_boolean_var_; + if (initial_value != ((void *)0)) + _g_boolean_var_ = 1; + else + _g_boolean_var_ = 0; + _g_boolean_var_; + }), + 1)) + ; + else + g_assertion_message_expr ("Gtk", + "gtkcssstylepropertyimpl.c", + 85, + ((const char*) (__PRETTY_FUNCTION__)), + "initial_value != NULL"); + } while (0); + + do + { + if (__builtin_expect (__extension__ ( + { + int _g_boolean_var_; + if (parse_value != ((void *)0)) + _g_boolean_var_ = 1; + else + _g_boolean_var_ = 0; + _g_boolean_var_; + }), + 1)) + ; + else + g_assertion_message_expr ("Gtk", + "gtkcssstylepropertyimpl.c", + 86, + ((const char*) (__PRETTY_FUNCTION__)), + "parse_value != NULL"); + } while (0); + + do + { + if (__builtin_expect (__extension__ ( + { + int _g_boolean_var_; + if (value_type == ((int) ((1) << (2))) + || query_value != ((void *)0)) + _g_boolean_var_ = 1; + else + _g_boolean_var_ = 0; + _g_boolean_var_; + }), + 1)) + ; + else + g_assertion_message_expr ("Gtk", + "gtkcssstylepropertyimpl.c", + 87, ((const char*) (__PRETTY_FUNCTION__)), + "value_type == NONE || query_value != NULL"); + } while (0); + + /* FLAGS is changed in a cond_exec instruction with pr57637. */ + if (flags == 15) + t = 15; + + do + { + if (__builtin_expect (__extension__ ( + { + int _g_boolean_var_; + if (value_type == ((1) << (2)) + || assign_value != ((void *)0)) + _g_boolean_var_ = 1; + else + _g_boolean_var_ = 0; + _g_boolean_var_; + }), + 1)) + ; + else + g_assertion_message_expr ("Gtk", + "gtkcssstylepropertyimpl.c", + 88, ((const char*) (__PRETTY_FUNCTION__)), + "value_type == NONE || assign_value != NULL"); + } while (0); + + node = g_object_new ((_gtk_css_style_property_get_type ()), + "value-type", value_type, + "affects-size", (flags & RESIZE) ? (0) : (!(0)), + "affects-font", (flags & FONT) ? (!(0)) : (0), + "animated", (flags & ANIMATED) ? (!(0)) : (0), + "inherit", (flags & INHERIT) ? (!(0)) : (0), + "initial-value", initial_value, + "name", name, + ((void *)0)); + + node->parse_value = parse_value; + node->query_value = query_value; + node->assign_value = assign_value; + + do + { + if (__builtin_expect (__extension__ ( + { + int _g_boolean_var_; + if (get_id (node) == expected_id) + _g_boolean_var_ = 1; + else + _g_boolean_var_ = 0; + _g_boolean_var_; + }), + 1)) + ; + else + g_assertion_message_expr ("Gtk", + "gtkcssstylepropertyimpl.c", + 106, + ((const char*) (__PRETTY_FUNCTION__)), + "get_id (node) == expected_id"); + } while (0); +} + +int main () +{ + gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t); + + if (t != 15) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c new file mode 100644 index 000000000..481a72b81 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-unaligned-access" } */ +/* { dg-final { scan-assembler "ldrb" } } */ +/* { dg-final { scan-assembler "strb" } } */ + +struct s +{ + char u; + long long v[2]; +} __attribute__((packed,aligned(1))); + +__attribute__((noinline, noclone)) +long long foo(struct s *x, int y, long long z) +{ + long long a = x->v[y]; + x->v[y] = z; + return a; +} + +struct s a = {0,{0,0}}; +int main() +{ + if (foo(&a,0,1) != 0) + __builtin_abort(); + if (foo(&a,0,2) != 1) + __builtin_abort(); + if (foo(&a,1,1) != 0) + __builtin_abort(); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c new file mode 100644 index 000000000..2b474f544 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c @@ -0,0 +1,54 @@ + +/* PR target/58578 */ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +#include <stdlib.h> + +typedef struct { + long _prec; + int _flag; + long _exp; +} __my_st_t; + +typedef __my_st_t *__my_st_ptr; + +int +_test_fn (__my_st_ptr y, const __my_st_ptr xt) +{ + int inexact; + if (xt->_exp != -2147483647L) + { + (y->_flag = xt->_flag); + } + + do { + __my_st_ptr _y = y; + long _err1 = -2 * xt->_exp; + long _err2 = 2; + if (0 < _err1) + { + unsigned long _err = (unsigned long) _err1 + _err2; + if (__builtin_expect(!!(_err > _y->_prec + 1), 0)) + return 2; + return 3; + } + } while (0); + + return 0; +} + +int main () +{ + __my_st_t x, y; + long pz; + int inex; + + x._prec = 914; + y._exp = 18; + if (_test_fn (&x, &y)) + { + abort(); + } + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c new file mode 100644 index 000000000..e3ef950b4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -marm -O2" } */ + +typedef struct __attribute__ ((__packed__)) +{ + char valueField[2]; +} ptp_tlv_t; +typedef struct __attribute__ ((__packed__)) +{ + char stepsRemoved; + ptp_tlv_t tlv[1]; +} ptp_message_announce_t; +int ptplib_send_announce(int sequenceId, int i) +{ + ptp_message_announce_t tx_packet; + ((long long *)tx_packet.tlv[0].valueField)[sequenceId] = i; + f(&tx_packet); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c new file mode 100644 index 000000000..13494f463 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c @@ -0,0 +1,15 @@ +/* PR target/59575 */ +/* { dg-do compile } */ +/* { dg-options "-Os -g -march=armv7-a" } */ + +void foo (int *); +int *bar (int, long long, int); + +void +test (int *p) +{ + if (p) + foo (p); + else if (p = bar (0, 1, 2)) + foo (p); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c new file mode 100644 index 000000000..a944b9afa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c @@ -0,0 +1,163 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv5te -fno-builtin -mfloat-abi=soft -mthumb -fno-stack-protector -Os -fno-tree-loop-optimize -fno-tree-dominator-opts -fPIC -w" } */ +/* { dg-skip-if "Incompatible command line options: -mfloat-abi=soft -mfloat-abi=hard" { *-*-* } { "-mfloat-abi=hard" } { "" } } */ + +typedef enum { + REG_ENOSYS = -1, +} reg_errcode_t; +typedef unsigned long int bitset_word_t; +typedef bitset_word_t bitset_t[(256 / (sizeof (bitset_word_t) * 8))]; +typedef bitset_word_t *re_bitset_ptr_t; +typedef const bitset_word_t *re_const_bitset_ptr_t; +typedef struct { + int nelem; + int *elems; +} re_node_set; +typedef enum { + CHARACTER = 1, +} re_token_type_t; +typedef struct { + re_token_type_t type:8; + unsigned int word_char:1; +} re_token_t; +struct re_string_t { + const unsigned char *raw_mbs; + int raw_mbs_idx; + int cur_idx; + unsigned int tip_context; + re_const_bitset_ptr_t word_char; +}; +typedef struct re_string_t re_string_t; +typedef struct re_dfa_t re_dfa_t; +struct re_dfastate_t { + re_node_set nodes; +}; +typedef struct re_dfastate_t re_dfastate_t; +typedef struct { + re_dfastate_t **array; +} state_array_t; +typedef struct { + state_array_t path; +} re_sub_match_last_t; +typedef struct { + int nlasts; + re_sub_match_last_t **lasts; +} re_sub_match_top_t; +typedef struct { + re_string_t input; + const re_dfa_t *dfa; + int nsub_tops; + re_sub_match_top_t **sub_tops; +} re_match_context_t; +struct re_dfa_t { + re_token_t *nodes; + re_bitset_ptr_t sb_char; + int mb_cur_max; + bitset_t word_char; +} bracket_elem_t; +static reg_errcode_t +re_string_reconstruct ( + re_string_t * pstr, + int idx, + int eflags +) +{ + int offset = idx - pstr->raw_mbs_idx; + int c = pstr->raw_mbs[pstr->raw_mbs_idx + offset - 1]; + pstr->tip_context = ((pstr->word_char[c] & ((bitset_word_t) 1)) ? : (c)); +} + +static void match_ctx_clean ( + re_match_context_t * +); +static int check_matching ( +); +static re_dfastate_t *transit_state ( +); +static int build_trtable ( +); +re_search_internal (int eflags +) +{ + reg_errcode_t err; + int incr; + int + match_first, + match_last = -1; + re_match_context_t mctx; + err = re_string_allocate (&mctx.input); + for (;; match_first += incr) + { + err = re_string_reconstruct (&mctx.input, match_first, eflags); + err = re_string_reconstruct (&mctx.input, match_first, eflags); + match_last = check_matching (&mctx, &match_first); + match_ctx_clean (&mctx); + } +} + +check_matching (re_match_context_t * mctx, int *p_match_first +) +{ + int cur_str_idx = ((&mctx->input)->cur_idx); + re_dfastate_t *cur_state; + int next_start_idx = cur_str_idx; + cur_state = transit_state (mctx, cur_state); + *p_match_first += next_start_idx; +} + +static re_dfastate_t * +transit_state ( + re_match_context_t * mctx, + re_dfastate_t * state +) +{ + if (!build_trtable (mctx->dfa, state)) + { + } +} + +build_trtable (const re_dfa_t * dfa, + re_dfastate_t * state +) +{ + int i, + j; + bitset_t accepts; + const re_node_set *cur_nodes = &state->nodes; + for (i = 0; i < cur_nodes->nelem; ++i) + { + re_token_t *node = &dfa->nodes[cur_nodes->elems[i]]; + re_token_type_t type = node->type; + { + if (dfa->mb_cur_max > 1) + bitset_merge (accepts, dfa->sb_char); + { + bitset_word_t any_set = 0; + if (type == CHARACTER && !node->word_char) + any_set |= (accepts[j] &= (dfa->word_char[j] | ~dfa->sb_char[j])); + else + for (j = 0; j < (256 / (sizeof (bitset_word_t) * 8)); ++j) + any_set |= (accepts[j] &= dfa->word_char[j]); + } + } + } +} + +static void +match_ctx_clean ( + re_match_context_t * mctx +) +{ + int st_idx; + for (st_idx = 0; st_idx < mctx->nsub_tops; ++st_idx) + { + int sl_idx; + re_sub_match_top_t *top = mctx->sub_tops[st_idx]; + for (sl_idx = 0; sl_idx < top->nlasts; ++sl_idx) + { + re_sub_match_last_t *last = top->lasts[sl_idx]; + free (last->path.array); + } + } +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c new file mode 100644 index 000000000..5896e7379 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c @@ -0,0 +1,1374 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ + +typedef unsigned int size_t; +typedef unsigned int wchar_t; +typedef int ptrdiff_t; +typedef signed char __int8_t ; +typedef unsigned char __uint8_t ; +typedef signed short __int16_t; +typedef unsigned short __uint16_t; +typedef __int16_t __int_least16_t; +typedef __uint16_t __uint_least16_t; +typedef signed int __int32_t; +typedef unsigned int __uint32_t; +typedef __int32_t __int_least32_t; +typedef __uint32_t __uint_least32_t; +typedef signed long long __int64_t; +typedef unsigned long long __uint64_t; +typedef int _LOCK_T; +typedef int _LOCK_RECURSIVE_T; +typedef long _off_t; +typedef short __dev_t; +typedef unsigned short __uid_t; +typedef unsigned short __gid_t; +__extension__ typedef long long _off64_t; +typedef long _fpos_t; +typedef signed int _ssize_t; +typedef unsigned int wint_t; +typedef struct +{ + int __count; + union + { + wint_t __wch; + unsigned char __wchb[4]; + } __value; +} _mbstate_t; +typedef _LOCK_RECURSIVE_T _flock_t; +typedef void *_iconv_t; +typedef unsigned long __ULong; +struct _reent; +struct _Bigint +{ + struct _Bigint *_next; + int _k, _maxwds, _sign, _wds; + __ULong _x[1]; +}; +struct __tm +{ + int __tm_sec; + int __tm_min; + int __tm_hour; + int __tm_mday; + int __tm_mon; + int __tm_year; + int __tm_wday; + int __tm_yday; + int __tm_isdst; +}; +struct _on_exit_args { + void * _fnargs[32]; + void * _dso_handle[32]; + __ULong _fntypes; + __ULong _is_cxa; +}; +struct _atexit { + struct _atexit *_next; + int _ind; + void (*_fns[32])(void); + struct _on_exit_args _on_exit_args; +}; +struct __sbuf { + unsigned char *_base; + int _size; +}; +struct __sFILE { + unsigned char *_p; + int _r; + int _w; + short _flags; + short _file; + struct __sbuf _bf; + int _lbfsize; + void * _cookie; + int (* _read) (struct _reent *, void *, char *, int) + ; + int (* _write) (struct _reent *, void *, const char *, int) + ; + _fpos_t (* _seek) (struct _reent *, void *, _fpos_t, int); + int (* _close) (struct _reent *, void *); + struct __sbuf _ub; + unsigned char *_up; + int _ur; + unsigned char _ubuf[3]; + unsigned char _nbuf[1]; + struct __sbuf _lb; + int _blksize; + _off_t _offset; + struct _reent *_data; + _flock_t _lock; + _mbstate_t _mbstate; + int _flags2; +}; +typedef struct __sFILE __FILE; +struct _glue +{ + struct _glue *_next; + int _niobs; + __FILE *_iobs; +}; +struct _rand48 { + unsigned short _seed[3]; + unsigned short _mult[3]; + unsigned short _add; +}; +struct _reent +{ + int _errno; + __FILE *_stdin, *_stdout, *_stderr; + int _inc; + char _emergency[25]; + int _current_category; + const char *_current_locale; + int __sdidinit; + void (* __cleanup) (struct _reent *); + struct _Bigint *_result; + int _result_k; + struct _Bigint *_p5s; + struct _Bigint **_freelist; + int _cvtlen; + char *_cvtbuf; + union + { + struct + { + unsigned int _unused_rand; + char * _strtok_last; + char _asctime_buf[26]; + struct __tm _localtime_buf; + int _gamma_signgam; + __extension__ unsigned long long _rand_next; + struct _rand48 _r48; + _mbstate_t _mblen_state; + _mbstate_t _mbtowc_state; + _mbstate_t _wctomb_state; + char _l64a_buf[8]; + char _signal_buf[24]; + int _getdate_err; + _mbstate_t _mbrlen_state; + _mbstate_t _mbrtowc_state; + _mbstate_t _mbsrtowcs_state; + _mbstate_t _wcrtomb_state; + _mbstate_t _wcsrtombs_state; + int _h_errno; + } _reent; + struct + { + unsigned char * _nextf[30]; + unsigned int _nmalloc[30]; + } _unused; + } _new; + struct _atexit *_atexit; + struct _atexit _atexit0; + void (**(_sig_func))(int); + struct _glue __sglue; + __FILE __sf[3]; +}; +extern struct _reent *_impure_ptr ; +extern struct _reent *const _global_impure_ptr ; +void _reclaim_reent (struct _reent *); +typedef struct +{ + int quot; + int rem; +} div_t; +typedef struct +{ + long quot; + long rem; +} ldiv_t; +typedef struct +{ + long long int quot; + long long int rem; +} lldiv_t; +typedef int (*__compar_fn_t) (const void *, const void *); +int __locale_mb_cur_max (void); +void abort (void) __attribute__ ((noreturn)); +int abs (int); +int atexit (void (*__func)(void)); +double atof (const char *__nptr); +float atoff (const char *__nptr); +int atoi (const char *__nptr); +int _atoi_r (struct _reent *, const char *__nptr); +long atol (const char *__nptr); +long _atol_r (struct _reent *, const char *__nptr); +void * bsearch (const void * __key, const void * __base, size_t __nmemb, size_t __size, __compar_fn_t _compar) + ; +void * calloc (size_t __nmemb, size_t __size) ; +div_t div (int __numer, int __denom); +void exit (int __status) __attribute__ ((noreturn)); +void free (void *) ; +char * getenv (const char *__string); +char * _getenv_r (struct _reent *, const char *__string); +char * _findenv (const char *, int *); +char * _findenv_r (struct _reent *, const char *, int *); +extern char *suboptarg; +int getsubopt (char **, char * const *, char **); +long labs (long); +ldiv_t ldiv (long __numer, long __denom); +void * malloc (size_t __size) ; +int mblen (const char *, size_t); +int _mblen_r (struct _reent *, const char *, size_t, _mbstate_t *); +int mbtowc (wchar_t *, const char *, size_t); +int _mbtowc_r (struct _reent *, wchar_t *, const char *, size_t, _mbstate_t *); +int wctomb (char *, wchar_t); +int _wctomb_r (struct _reent *, char *, wchar_t, _mbstate_t *); +size_t mbstowcs (wchar_t *, const char *, size_t); +size_t _mbstowcs_r (struct _reent *, wchar_t *, const char *, size_t, _mbstate_t *); +size_t wcstombs (char *, const wchar_t *, size_t); +size_t _wcstombs_r (struct _reent *, char *, const wchar_t *, size_t, _mbstate_t *); +char * mkdtemp (char *); +int mkostemp (char *, int); +int mkostemps (char *, int, int); +int mkstemp (char *); +int mkstemps (char *, int); +char * mktemp (char *) __attribute__ ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))); +char * _mkdtemp_r (struct _reent *, char *); +int _mkostemp_r (struct _reent *, char *, int); +int _mkostemps_r (struct _reent *, char *, int, int); +int _mkstemp_r (struct _reent *, char *); +int _mkstemps_r (struct _reent *, char *, int); +char * _mktemp_r (struct _reent *, char *) __attribute__ ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))); +void qsort (void * __base, size_t __nmemb, size_t __size, __compar_fn_t _compar); +int rand (void); +void * realloc (void * __r, size_t __size) ; +void * reallocf (void * __r, size_t __size); +void srand (unsigned __seed); +double strtod (const char *__n, char **__end_PTR); +double _strtod_r (struct _reent *,const char *__n, char **__end_PTR); +float strtof (const char *__n, char **__end_PTR); +long strtol (const char *__n, char **__end_PTR, int __base); +long _strtol_r (struct _reent *,const char *__n, char **__end_PTR, int __base); +unsigned long strtoul (const char *__n, char **__end_PTR, int __base); +unsigned long _strtoul_r (struct _reent *,const char *__n, char **__end_PTR, int __base); +int system (const char *__string); +long a64l (const char *__input); +char * l64a (long __input); +char * _l64a_r (struct _reent *,long __input); +int on_exit (void (*__func)(int, void *),void * __arg); +void _Exit (int __status) __attribute__ ((noreturn)); +int putenv (char *__string); +int _putenv_r (struct _reent *, char *__string); +void * _reallocf_r (struct _reent *, void *, size_t); +int setenv (const char *__string, const char *__value, int __overwrite); +int _setenv_r (struct _reent *, const char *__string, const char *__value, int __overwrite); +char * gcvt (double,int,char *); +char * gcvtf (float,int,char *); +char * fcvt (double,int,int *,int *); +char * fcvtf (float,int,int *,int *); +char * ecvt (double,int,int *,int *); +char * ecvtbuf (double, int, int*, int*, char *); +char * fcvtbuf (double, int, int*, int*, char *); +char * ecvtf (float,int,int *,int *); +char * dtoa (double, int, int, int *, int*, char**); +int rand_r (unsigned *__seed); +double drand48 (void); +double _drand48_r (struct _reent *); +double erand48 (unsigned short [3]); +double _erand48_r (struct _reent *, unsigned short [3]); +long jrand48 (unsigned short [3]); +long _jrand48_r (struct _reent *, unsigned short [3]); +void lcong48 (unsigned short [7]); +void _lcong48_r (struct _reent *, unsigned short [7]); +long lrand48 (void); +long _lrand48_r (struct _reent *); +long mrand48 (void); +long _mrand48_r (struct _reent *); +long nrand48 (unsigned short [3]); +long _nrand48_r (struct _reent *, unsigned short [3]); +unsigned short * + seed48 (unsigned short [3]); +unsigned short * + _seed48_r (struct _reent *, unsigned short [3]); +void srand48 (long); +void _srand48_r (struct _reent *, long); +long long atoll (const char *__nptr); +long long _atoll_r (struct _reent *, const char *__nptr); +long long llabs (long long); +lldiv_t lldiv (long long __numer, long long __denom); +long long strtoll (const char *__n, char **__end_PTR, int __base); +long long _strtoll_r (struct _reent *, const char *__n, char **__end_PTR, int __base); +unsigned long long strtoull (const char *__n, char **__end_PTR, int __base); +unsigned long long _strtoull_r (struct _reent *, const char *__n, char **__end_PTR, int __base); +void cfree (void *); +int unsetenv (const char *__string); +int _unsetenv_r (struct _reent *, const char *__string); +char * _dtoa_r (struct _reent *, double, int, int, int *, int*, char**); +void * _malloc_r (struct _reent *, size_t) ; +void * _calloc_r (struct _reent *, size_t, size_t) ; +void _free_r (struct _reent *, void *) ; +void * _realloc_r (struct _reent *, void *, size_t) ; +void _mstats_r (struct _reent *, char *); +int _system_r (struct _reent *, const char *); +void __eprintf (const char *, const char *, unsigned int, const char *); +extern long double strtold (const char *, char **); +extern long double wcstold (const wchar_t *, wchar_t **); +typedef long int __off_t; +typedef int __pid_t; +__extension__ typedef long long int __loff_t; +struct stat; +struct tms; +struct timeval; +struct timezone; +extern int _close_r (struct _reent *, int); +extern int _execve_r (struct _reent *, const char *, char *const *, char *const *); +extern int _fcntl_r (struct _reent *, int, int, int); +extern int _fork_r (struct _reent *); +extern int _fstat_r (struct _reent *, int, struct stat *); +extern int _getpid_r (struct _reent *); +extern int _isatty_r (struct _reent *, int); +extern int _kill_r (struct _reent *, int, int); +extern int _link_r (struct _reent *, const char *, const char *); +extern _off_t _lseek_r (struct _reent *, int, _off_t, int); +extern int _mkdir_r (struct _reent *, const char *, int); +extern int _open_r (struct _reent *, const char *, int, int); +extern _ssize_t _read_r (struct _reent *, int, void *, size_t); +extern int _rename_r (struct _reent *, const char *, const char *); +extern void *_sbrk_r (struct _reent *, ptrdiff_t); +extern int _stat_r (struct _reent *, const char *, struct stat *); +extern unsigned long _times_r (struct _reent *, struct tms *); +extern int _unlink_r (struct _reent *, const char *); +extern int _wait_r (struct _reent *, int *); +extern _ssize_t _write_r (struct _reent *, int, const void *, size_t); +extern int _gettimeofday_r (struct _reent *, struct timeval *__tp, void *__tzp); +typedef signed char int8_t ; +typedef unsigned char uint8_t ; +typedef signed char int_least8_t; +typedef unsigned char uint_least8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef int16_t int_least16_t; +typedef uint16_t uint_least16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef int32_t int_least32_t; +typedef uint32_t uint_least32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +typedef int64_t int_least64_t; +typedef uint64_t uint_least64_t; + typedef signed int int_fast8_t; + typedef unsigned int uint_fast8_t; + typedef signed int int_fast16_t; + typedef unsigned int uint_fast16_t; + typedef signed int int_fast32_t; + typedef unsigned int uint_fast32_t; + typedef int_least64_t int_fast64_t; + typedef uint_least64_t uint_fast64_t; + typedef long long int intmax_t; + typedef long long unsigned int uintmax_t; +typedef signed int intptr_t; +typedef unsigned int uintptr_t; +void * memchr (const void *, int, size_t); +int memcmp (const void *, const void *, size_t); +void * memcpy (void * , const void * , size_t); +void * memmove (void *, const void *, size_t); +void * memset (void *, int, size_t); +char *strcat (char *, const char *); +char *strchr (const char *, int); +int strcmp (const char *, const char *); +int strcoll (const char *, const char *); +char *strcpy (char *, const char *); +size_t strcspn (const char *, const char *); +char *strerror (int); +size_t strlen (const char *); +char *strncat (char *, const char *, size_t); +int strncmp (const char *, const char *, size_t); +char *strncpy (char *, const char *, size_t); +char *strpbrk (const char *, const char *); +char *strrchr (const char *, int); +size_t strspn (const char *, const char *); +char *strstr (const char *, const char *); +char *strtok (char *, const char *); +size_t strxfrm (char *, const char *, size_t); +char *strtok_r (char *, const char *, char **); +int bcmp (const void *, const void *, size_t); +void bcopy (const void *, void *, size_t); +void bzero (void *, size_t); +int ffs (int); +char *index (const char *, int); +void * memccpy (void * , const void * , int, size_t); +void * mempcpy (void *, const void *, size_t); +void * memmem (const void *, size_t, const void *, size_t); +void * memrchr (const void *, int, size_t); +void * rawmemchr (const void *, int); +char *rindex (const char *, int); +char *stpcpy (char *, const char *); +char *stpncpy (char *, const char *, size_t); +int strcasecmp (const char *, const char *); +char *strcasestr (const char *, const char *); +char *strchrnul (const char *, int); +char *strdup (const char *); +char *_strdup_r (struct _reent *, const char *); +char *strndup (const char *, size_t); +char *_strndup_r (struct _reent *, const char *, size_t); +int strerror_r (int, char *, size_t) __asm__ ("" "__xpg_strerror_r"); +size_t strlcat (char *, const char *, size_t); +size_t strlcpy (char *, const char *, size_t); +int strncasecmp (const char *, const char *, size_t); +size_t strnlen (const char *, size_t); +char *strsep (char **, const char *); +char *strlwr (char *); +char *strupr (char *); +char *strsignal (int __signo); +char * _strerror_r (struct _reent *, int, int, int *); +typedef union +{ + double value; + struct + { + unsigned int fraction1:32; + unsigned int fraction0:20; + unsigned int exponent :11; + unsigned int sign : 1; + } number; + struct + { + unsigned int function1:32; + unsigned int function0:19; + unsigned int quiet:1; + unsigned int exponent: 11; + unsigned int sign : 1; + } nan; + struct + { + unsigned long lsw; + unsigned long msw; + } parts; + long aslong[2]; +} __ieee_double_shape_type; +typedef union +{ + float value; + struct + { + unsigned int fraction0: 7; + unsigned int fraction1: 16; + unsigned int exponent: 8; + unsigned int sign : 1; + } number; + struct + { + unsigned int function1:16; + unsigned int function0:6; + unsigned int quiet:1; + unsigned int exponent:8; + unsigned int sign:1; + } nan; + long p1; +} __ieee_float_shape_type; +typedef int fp_rnd; +fp_rnd fpgetround (void); +fp_rnd fpsetround (fp_rnd); +typedef int fp_except; +fp_except fpgetmask (void); +fp_except fpsetmask (fp_except); +fp_except fpgetsticky (void); +fp_except fpsetsticky (fp_except); +typedef int fp_rdi; +fp_rdi fpgetroundtoi (void); +fp_rdi fpsetroundtoi (fp_rdi); +int isnan (double); +int isinf (double); +int finite (double); +int isnanf (float); +int isinff (float); +int finitef (float); +union __dmath +{ + double d; + __ULong i[2]; +}; +union __fmath +{ + float f; + __ULong i[1]; +}; +union __ldmath +{ + long double ld; + __ULong i[4]; +}; +extern double atan (double); +extern double cos (double); +extern double sin (double); +extern double tan (double); +extern double tanh (double); +extern double frexp (double, int *); +extern double modf (double, double *); +extern double ceil (double); +extern double fabs (double); +extern double floor (double); +extern double acos (double); +extern double asin (double); +extern double atan2 (double, double); +extern double cosh (double); +extern double sinh (double); +extern double exp (double); +extern double ldexp (double, int); +extern double log (double); +extern double log10 (double); +extern double pow (double, double); +extern double sqrt (double); +extern double fmod (double, double); + typedef float float_t; + typedef double double_t; +extern int __isinff (float x); +extern int __isinfd (double x); +extern int __isnanf (float x); +extern int __isnand (double x); +extern int __fpclassifyf (float x); +extern int __fpclassifyd (double x); +extern int __signbitf (float x); +extern int __signbitd (double x); +extern double infinity (void); +extern double nan (const char *); +extern int finite (double); +extern double copysign (double, double); +extern double logb (double); +extern int ilogb (double); +extern double asinh (double); +extern double cbrt (double); +extern double nextafter (double, double); +extern double rint (double); +extern double scalbn (double, int); +extern double exp2 (double); +extern double scalbln (double, long int); +extern double tgamma (double); +extern double nearbyint (double); +extern long int lrint (double); +extern long long int llrint (double); +extern double round (double); +extern long int lround (double); +extern long long int llround (double); +extern double trunc (double); +extern double remquo (double, double, int *); +extern double fdim (double, double); +extern double fmax (double, double); +extern double fmin (double, double); +extern double fma (double, double, double); +extern double log1p (double); +extern double expm1 (double); +extern double acosh (double); +extern double atanh (double); +extern double remainder (double, double); +extern double gamma (double); +extern double lgamma (double); +extern double erf (double); +extern double erfc (double); +extern double log2 (double); +extern double hypot (double, double); +extern float atanf (float); +extern float cosf (float); +extern float sinf (float); +extern float tanf (float); +extern float tanhf (float); +extern float frexpf (float, int *); +extern float modff (float, float *); +extern float ceilf (float); +extern float fabsf (float); +extern float floorf (float); +extern float acosf (float); +extern float asinf (float); +extern float atan2f (float, float); +extern float coshf (float); +extern float sinhf (float); +extern float expf (float); +extern float ldexpf (float, int); +extern float logf (float); +extern float log10f (float); +extern float powf (float, float); +extern float sqrtf (float); +extern float fmodf (float, float); +extern float exp2f (float); +extern float scalblnf (float, long int); +extern float tgammaf (float); +extern float nearbyintf (float); +extern long int lrintf (float); +extern long long llrintf (float); +extern float roundf (float); +extern long int lroundf (float); +extern long long int llroundf (float); +extern float truncf (float); +extern float remquof (float, float, int *); +extern float fdimf (float, float); +extern float fmaxf (float, float); +extern float fminf (float, float); +extern float fmaf (float, float, float); +extern float infinityf (void); +extern float nanf (const char *); +extern int finitef (float); +extern float copysignf (float, float); +extern float logbf (float); +extern int ilogbf (float); +extern float asinhf (float); +extern float cbrtf (float); +extern float nextafterf (float, float); +extern float rintf (float); +extern float scalbnf (float, int); +extern float log1pf (float); +extern float expm1f (float); +extern float acoshf (float); +extern float atanhf (float); +extern float remainderf (float, float); +extern float gammaf (float); +extern float lgammaf (float); +extern float erff (float); +extern float erfcf (float); +extern float log2f (float); +extern float hypotf (float, float); +extern long double atanl (long double); +extern long double cosl (long double); +extern long double sinl (long double); +extern long double tanl (long double); +extern long double tanhl (long double); +extern long double frexpl (long double value, int *); +extern long double modfl (long double, long double *); +extern long double ceill (long double); +extern long double fabsl (long double); +extern long double floorl (long double); +extern long double log1pl (long double); +extern long double expm1l (long double); +extern long double acosl (long double); +extern long double asinl (long double); +extern long double atan2l (long double, long double); +extern long double coshl (long double); +extern long double sinhl (long double); +extern long double expl (long double); +extern long double ldexpl (long double, int); +extern long double logl (long double); +extern long double log10l (long double); +extern long double powl (long double, long double); +extern long double sqrtl (long double); +extern long double fmodl (long double, long double); +extern long double hypotl (long double, long double); +extern long double copysignl (long double, long double); +extern long double nanl (const char *); +extern int ilogbl (long double); +extern long double asinhl (long double); +extern long double cbrtl (long double); +extern long double nextafterl (long double, long double); +extern long double rintl (long double); +extern long double scalbnl (long double, int); +extern long double exp2l (long double); +extern long double scalblnl (long double, long); +extern long double tgammal (long double); +extern long double nearbyintl (long double); +extern long int lrintl (long double); +extern long long int llrintl (long double); +extern long double roundl (long double); +extern long lroundl (long double); +extern long long int llroundl (long double); +extern long double truncl (long double); +extern long double remquol (long double, long double, int *); +extern long double fdiml (long double, long double); +extern long double fmaxl (long double, long double); +extern long double fminl (long double, long double); +extern long double fmal (long double, long double, long double); +extern long double acoshl (long double); +extern long double atanhl (long double); +extern long double remainderl (long double, long double); +extern long double lgammal (long double); +extern long double erfl (long double); +extern long double erfcl (long double); +extern double drem (double, double); +extern void sincos (double, double *, double *); +extern double gamma_r (double, int *); +extern double lgamma_r (double, int *); +extern double y0 (double); +extern double y1 (double); +extern double yn (int, double); +extern double j0 (double); +extern double j1 (double); +extern double jn (int, double); +extern float dremf (float, float); +extern void sincosf (float, float *, float *); +extern float gammaf_r (float, int *); +extern float lgammaf_r (float, int *); +extern float y0f (float); +extern float y1f (float); +extern float ynf (int, float); +extern float j0f (float); +extern float j1f (float); +extern float jnf (int, float); +extern double exp10 (double); +extern double pow10 (double); +extern float exp10f (float); +extern float pow10f (float); +extern int *__signgam (void); +struct exception +{ + int type; + char *name; + double arg1; + double arg2; + double retval; + int err; +}; +extern int matherr (struct exception *e); +enum __fdlibm_version +{ + __fdlibm_ieee = -1, + __fdlibm_svid, + __fdlibm_xopen, + __fdlibm_posix +}; +extern enum __fdlibm_version __fdlib_version; +typedef int error_t; +extern int *__errno (void); +extern const char * const _sys_errlist[]; +extern int _sys_nerr; +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; +typedef unsigned long clock_t; +typedef long time_t; +struct timespec { + time_t tv_sec; + long tv_nsec; +}; +struct itimerspec { + struct timespec it_interval; + struct timespec it_value; +}; +typedef long daddr_t; +typedef char * caddr_t; +typedef unsigned short ino_t; +typedef _off_t off_t; +typedef __dev_t dev_t; +typedef __uid_t uid_t; +typedef __gid_t gid_t; +typedef int pid_t; +typedef long key_t; +typedef _ssize_t ssize_t; +typedef unsigned int mode_t __attribute__ ((__mode__ (__SI__))); +typedef unsigned short nlink_t; +typedef long fd_mask; +typedef struct _types_fd_set { + fd_mask fds_bits[(((64)+(((sizeof (fd_mask) * 8))-1))/((sizeof (fd_mask) * 8)))]; +} _types_fd_set; +typedef unsigned long clockid_t; +typedef unsigned long timer_t; +typedef unsigned long useconds_t; +typedef long suseconds_t; +union double_union +{ + double d; + __uint32_t i[2]; +}; +typedef __int32_t Long; +typedef union { double d; __ULong i[2]; } U; +typedef struct _Bigint _Bigint; +struct _reent ; +struct FPI; +double __ulp (double x); +double __b2d (_Bigint *a , int *e); +_Bigint * _Balloc (struct _reent *p, int k); +void _Bfree (struct _reent *p, _Bigint *v); +_Bigint * __multadd (struct _reent *p, _Bigint *, int, int); +_Bigint * __s2b (struct _reent *, const char*, int, int, __ULong); +_Bigint * __i2b (struct _reent *,int); +_Bigint * __multiply (struct _reent *, _Bigint *, _Bigint *); +_Bigint * __pow5mult (struct _reent *, _Bigint *, int k); +int __hi0bits (__ULong); +int __lo0bits (__ULong *); +_Bigint * __d2b (struct _reent *p, double d, int *e, int *bits); +_Bigint * __lshift (struct _reent *p, _Bigint *b, int k); +_Bigint * __mdiff (struct _reent *p, _Bigint *a, _Bigint *b); +int __mcmp (_Bigint *a, _Bigint *b); +int __gethex (struct _reent *p, const char **sp, const struct FPI *fpi, Long *exp, _Bigint **bp, int sign); +double __ratio (_Bigint *a, _Bigint *b); +__ULong __any_on (_Bigint *b, int k); +void __copybits (__ULong *c, int n, _Bigint *b); +int __hexnan (const char **sp, const struct FPI *fpi, __ULong *x0); +extern const double __mprec_tinytens[]; +extern const double __mprec_bigtens[]; +extern const double __mprec_tens[]; +extern const unsigned char __hexdig[]; +double _mprec_log10 (int); +static int +quorem(_Bigint * b , _Bigint * S) +{ + int n; + long borrow, y; + __ULong carry, q, ys; + __ULong *bx, *bxe, *sx, *sxe; + long z; + __ULong si, zs; + n = S->_wds; + if (b->_wds < n) + return 0; + sx = S->_x; + sxe = sx + --n; + bx = b->_x; + bxe = bx + n; + q = *bxe / (*sxe + 1); + if (q) + { + borrow = 0; + carry = 0; + do + { + si = *sx++; + ys = (si & 0xffff) * q + carry; + zs = (si >> 16) * q + (ys >> 16); + carry = zs >> 16; + y = (*bx & 0xffff) - (ys & 0xffff) + borrow; + borrow = y >> 16; + ; + z = (*bx >> 16) - (zs & 0xffff) + borrow; + borrow = z >> 16; + ; + (*(bx)++ = ((z) << 16) | ((y) & 0xffff)); + } + while (sx <= sxe); + if (!*bxe) + { + bx = b->_x; + while (--bxe > bx && !*bxe) + --n; + b->_wds = n; + } + } + if (__mcmp (b, S) >= 0) + { + q++; + borrow = 0; + carry = 0; + bx = b->_x; + sx = S->_x; + do + { + si = *sx++; + ys = (si & 0xffff) + carry; + zs = (si >> 16) + (ys >> 16); + carry = zs >> 16; + y = (*bx & 0xffff) - (ys & 0xffff) + borrow; + borrow = y >> 16; + ; + z = (*bx >> 16) - (zs & 0xffff) + borrow; + borrow = z >> 16; + ; + (*(bx)++ = ((z) << 16) | ((y) & 0xffff)); + } + while (sx <= sxe); + bx = b->_x; + bxe = bx + n; + if (!*bxe) + { + while (--bxe > bx && !*bxe) + --n; + b->_wds = n; + } + } + return q; +} +char * +_dtoa_r(struct _reent *ptr , double _d , int mode , int ndigits , int *decpt , int *sign , char **rve) +{ + int bbits, b2, b5, be, dig, i, ieps, ilim, ilim0, ilim1, j, j1, k, k0, + k_check, leftright, m2, m5, s2, s5, spec_case, try_quick; + union double_union d, d2, eps; + long L; + int denorm; + __ULong x; + _Bigint *b, *b1, *delta, *mlo = ((void *)0), *mhi, *S; + double ds; + char *s, *s0; + d.d = _d; + ; + if (((ptr)->_result)) + { + ((ptr)->_result)->_k = ((ptr)->_result_k); + ((ptr)->_result)->_maxwds = 1 << ((ptr)->_result_k); + _Bfree (ptr, ((ptr)->_result)); + ((ptr)->_result) = 0; + } + if ((d.i[1]) & ((__uint32_t)0x80000000L)) + { + *sign = 1; + (d.i[1]) &= ~((__uint32_t)0x80000000L); + } + else + *sign = 0; + if (((d.i[1]) & ((__uint32_t)0x7ff00000L)) == ((__uint32_t)0x7ff00000L)) + { + *decpt = 9999; + s = + !(d.i[0]) && !((d.i[1]) & 0xfffff) ? "Infinity" : + "NaN"; + if (rve) + *rve = + s[3] ? s + 8 : + s + 3; + return s; + } + if (!d.d) + { + *decpt = 1; + s = "0"; + if (rve) + *rve = s + 1; + return s; + } + b = __d2b (ptr, d.d, &be, &bbits); + if ((i = (int) ((d.i[1]) >> 20 & (((__uint32_t)0x7ff00000L) >> 20))) != 0) + { + d2.d = d.d; + (d2.i[1]) &= ((__uint32_t)0xfffffL); + (d2.i[1]) |= ((__uint32_t)0x3ff00000L); + i -= 1023; + denorm = 0; + } + else + { + i = bbits + be + (1023 + (53 - 1) - 1); + x = (i > 32) ? ((d.i[1]) << (64 - i)) | ((d.i[0]) >> (i - 32)) + : ((d.i[0]) << (32 - i)); + d2.d = x; + (d2.i[1]) -= 31 * ((__uint32_t)0x100000L); + i -= (1023 + (53 - 1) - 1) + 1; + denorm = 1; + } + ds = (d2.d - 1.5) * 0.289529654602168 + 0.1760912590558 + i * 0.301029995663981; + k = (int) ds; + if (ds < 0. && ds != k) + k--; + k_check = 1; + if (k >= 0 && k <= 22) + { + if (d.d < __mprec_tens[k]) + k--; + k_check = 0; + } + j = bbits - i - 1; + if (j >= 0) + { + b2 = 0; + s2 = j; + } + else + { + b2 = -j; + s2 = 0; + } + if (k >= 0) + { + b5 = 0; + s5 = k; + s2 += k; + } + else + { + b2 -= k; + b5 = -k; + s5 = 0; + } + if (mode < 0 || mode > 9) + mode = 0; + try_quick = 1; + if (mode > 5) + { + mode -= 4; + try_quick = 0; + } + leftright = 1; + ilim = ilim1 = -1; + switch (mode) + { + case 0: + case 1: + i = 18; + ndigits = 0; + break; + case 2: + leftright = 0; + case 4: + if (ndigits <= 0) + ndigits = 1; + ilim = ilim1 = i = ndigits; + break; + case 3: + leftright = 0; + case 5: + i = ndigits + k + 1; + ilim = i; + ilim1 = i - 1; + if (i <= 0) + i = 1; + } + j = sizeof (__ULong); + for (((ptr)->_result_k) = 0; sizeof (_Bigint) - sizeof (__ULong) + j <= i; + j <<= 1) + ((ptr)->_result_k)++; + ((ptr)->_result) = _Balloc (ptr, ((ptr)->_result_k)); + s = s0 = (char *) ((ptr)->_result); + if (ilim >= 0 && ilim <= 14 && try_quick) + { + i = 0; + d2.d = d.d; + k0 = k; + ilim0 = ilim; + ieps = 2; + if (k > 0) + { + ds = __mprec_tens[k & 0xf]; + j = k >> 4; + if (j & 0x10) + { + j &= 0x10 - 1; + d.d /= __mprec_bigtens[5 - 1]; + ieps++; + } + for (; j; j >>= 1, i++) + if (j & 1) + { + ieps++; + ds *= __mprec_bigtens[i]; + } + d.d /= ds; + } + else if ((j1 = -k) != 0) + { + d.d *= __mprec_tens[j1 & 0xf]; + for (j = j1 >> 4; j; j >>= 1, i++) + if (j & 1) + { + ieps++; + d.d *= __mprec_bigtens[i]; + } + } + if (k_check && d.d < 1. && ilim > 0) + { + if (ilim1 <= 0) + goto fast_failed; + ilim = ilim1; + k--; + d.d *= 10.; + ieps++; + } + eps.d = ieps * d.d + 7.; + (eps.i[1]) -= (53 - 1) * ((__uint32_t)0x100000L); + if (ilim == 0) + { + S = mhi = 0; + d.d -= 5.; + if (d.d > eps.d) + goto one_digit; + if (d.d < -eps.d) + goto no_digits; + goto fast_failed; + } + if (leftright) + { + eps.d = 0.5 / __mprec_tens[ilim - 1] - eps.d; + for (i = 0;;) + { + L = d.d; + d.d -= L; + *s++ = '0' + (int) L; + if (d.d < eps.d) + goto ret1; + if (1. - d.d < eps.d) + goto bump_up; + if (++i >= ilim) + break; + eps.d *= 10.; + d.d *= 10.; + } + } + else + { + eps.d *= __mprec_tens[ilim - 1]; + for (i = 1;; i++, d.d *= 10.) + { + L = d.d; + d.d -= L; + *s++ = '0' + (int) L; + if (i == ilim) + { + if (d.d > 0.5 + eps.d) + goto bump_up; + else if (d.d < 0.5 - eps.d) + { + while (*--s == '0'); + s++; + goto ret1; + } + break; + } + } + } + fast_failed: + s = s0; + d.d = d2.d; + k = k0; + ilim = ilim0; + } + if (be >= 0 && k <= 14) + { + ds = __mprec_tens[k]; + if (ndigits < 0 && ilim <= 0) + { + S = mhi = 0; + if (ilim < 0 || d.d <= 5 * ds) + goto no_digits; + goto one_digit; + } + for (i = 1;; i++) + { + L = d.d / ds; + d.d -= L * ds; + *s++ = '0' + (int) L; + if (i == ilim) + { + d.d += d.d; + if ((d.d > ds) || ((d.d == ds) && (L & 1))) + { + bump_up: + while (*--s == '9') + if (s == s0) + { + k++; + *s = '0'; + break; + } + ++*s++; + } + break; + } + if (!(d.d *= 10.)) + break; + } + goto ret1; + } + m2 = b2; + m5 = b5; + mhi = mlo = 0; + if (leftright) + { + if (mode < 2) + { + i = + denorm ? be + (1023 + (53 - 1) - 1 + 1) : + 1 + 53 - bbits; + } + else + { + j = ilim - 1; + if (m5 >= j) + m5 -= j; + else + { + s5 += j -= m5; + b5 += j; + m5 = 0; + } + if ((i = ilim) < 0) + { + m2 -= i; + i = 0; + } + } + b2 += i; + s2 += i; + mhi = __i2b (ptr, 1); + } + if (m2 > 0 && s2 > 0) + { + i = m2 < s2 ? m2 : s2; + b2 -= i; + m2 -= i; + s2 -= i; + } + if (b5 > 0) + { + if (leftright) + { + if (m5 > 0) + { + mhi = __pow5mult (ptr, mhi, m5); + b1 = __multiply (ptr, mhi, b); + _Bfree (ptr, b); + b = b1; + } + if ((j = b5 - m5) != 0) + b = __pow5mult (ptr, b, j); + } + else + b = __pow5mult (ptr, b, b5); + } + S = __i2b (ptr, 1); + if (s5 > 0) + S = __pow5mult (ptr, S, s5); + spec_case = 0; + if (mode < 2) + { + if (!(d.i[0]) && !((d.i[1]) & ((__uint32_t)0xfffffL)) + && (d.i[1]) & ((__uint32_t)0x7ff00000L) + ) + { + b2 += 1; + s2 += 1; + spec_case = 1; + } + } + if ((i = ((s5 ? 32 - __hi0bits (S->_x[S->_wds - 1]) : 1) + s2) & 0x1f) != 0) + i = 32 - i; + if (i > 4) + { + i -= 4; + b2 += i; + m2 += i; + s2 += i; + } + else if (i < 4) + { + i += 28; + b2 += i; + m2 += i; + s2 += i; + } + if (b2 > 0) + b = __lshift (ptr, b, b2); + if (s2 > 0) + S = __lshift (ptr, S, s2); + if (k_check) + { + if (__mcmp (b, S) < 0) + { + k--; + b = __multadd (ptr, b, 10, 0); + if (leftright) + mhi = __multadd (ptr, mhi, 10, 0); + ilim = ilim1; + } + } + if (ilim <= 0 && mode > 2) + { + if (ilim < 0 || __mcmp (b, S = __multadd (ptr, S, 5, 0)) <= 0) + { + no_digits: + k = -1 - ndigits; + goto ret; + } + one_digit: + *s++ = '1'; + k++; + goto ret; + } + if (leftright) + { + if (m2 > 0) + mhi = __lshift (ptr, mhi, m2); + mlo = mhi; + if (spec_case) + { + mhi = _Balloc (ptr, mhi->_k); + memcpy((char *)&mhi->_sign, (char *)&mlo->_sign, mlo->_wds*sizeof(long) + 2*sizeof(int)); + mhi = __lshift (ptr, mhi, 1); + } + for (i = 1;; i++) + { + dig = quorem (b, S) + '0'; + j = __mcmp (b, mlo); + delta = __mdiff (ptr, S, mhi); + j1 = delta->_sign ? 1 : __mcmp (b, delta); + _Bfree (ptr, delta); + if (j1 == 0 && !mode && !((d.i[0]) & 1)) + { + if (dig == '9') + goto round_9_up; + if (j > 0) + dig++; + *s++ = dig; + goto ret; + } + if ((j < 0) || ((j == 0) && !mode + && !((d.i[0]) & 1) + )) + { + if (j1 > 0) + { + b = __lshift (ptr, b, 1); + j1 = __mcmp (b, S); + if (((j1 > 0) || ((j1 == 0) && (dig & 1))) + && dig++ == '9') + goto round_9_up; + } + *s++ = dig; + goto ret; + } + if (j1 > 0) + { + if (dig == '9') + { + round_9_up: + *s++ = '9'; + goto roundoff; + } + *s++ = dig + 1; + goto ret; + } + *s++ = dig; + if (i == ilim) + break; + b = __multadd (ptr, b, 10, 0); + if (mlo == mhi) + mlo = mhi = __multadd (ptr, mhi, 10, 0); + else + { + mlo = __multadd (ptr, mlo, 10, 0); + mhi = __multadd (ptr, mhi, 10, 0); + } + } + } + else + for (i = 1;; i++) + { + *s++ = dig = quorem (b, S) + '0'; + if (i >= ilim) + break; + b = __multadd (ptr, b, 10, 0); + } + b = __lshift (ptr, b, 1); + j = __mcmp (b, S); + if ((j > 0) || ((j == 0) && (dig & 1))) + { + roundoff: + while (*--s == '9') + if (s == s0) + { + k++; + *s++ = '1'; + goto ret; + } + ++*s++; + } + else + { + while (*--s == '0'); + s++; + } +ret: + _Bfree (ptr, S); + if (mhi) + { + if (mlo && mlo != mhi) + _Bfree (ptr, mlo); + _Bfree (ptr, mhi); + } +ret1: + _Bfree (ptr, b); + *s = 0; + *decpt = k + 1; + if (rve) + *rve = s; + return s0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c new file mode 100644 index 000000000..86a4e7d83 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c @@ -0,0 +1,24 @@ +/* PR target/59923 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mcpu=cortex-a15 -fno-strict-aliasing -mthumb -g" } */ + +struct S +{ + void *s; + struct T { unsigned short a; unsigned char b[4], c[4]; } *t; +} s; +void bar (void *); + +void +foo (struct S *x, int *y) +{ + if (*y > 0) + return; + else if (x->t->b[0] == 0x43 && x->t->b[1] == 0x6d && x->t->c[0] == 1) + x->s = &s; + else + *y = 16384; + if (*y > 0) + bar (x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C new file mode 100644 index 000000000..cc688a965 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-g -fcompare-debug -O2 -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard" } */ + +extern void *f1 (unsigned long, unsigned long); +extern const struct line_map *f2 (void *, int, unsigned int, const char *, unsigned int); +extern unsigned int f3 (void *, unsigned int); +extern void *v1; +struct B { const char *s; int t; }; +struct C { unsigned u; unsigned long long v; void *w; }; +unsigned long long f4 (struct C *); +const char *f5 (void *, unsigned int, unsigned int *); +unsigned long long f6 (void *); + +static inline unsigned long long +f7 (struct C *x, unsigned y) +{ + unsigned long long a, b; + int u = x->u; + a = y == 64 ? -1ULL : (1ULL << y) - 1; + if (u + y > 64) + { + f6 (x->w); + x->u = y; + return b & a; + } + b = x->v; + b >>= u; + x->u = u + y; + return b & a; +} + +static const char * +f8 (const char *x) +{ + B **a; + unsigned long t = __builtin_strlen (x); + char *b; + struct B *c; + b = (char *) f1 (t + 1, 1); + c = (struct B *) f1 (1, sizeof (struct B)); + __builtin_memcpy (b, x, t + 1); + c->t = t; + struct B *d = *a; + return d->s; +} + +unsigned int +f9 (struct C *x, void *y) +{ + static const char *a; + static int b; + static int c; + bool d, e, f; + unsigned t; + bool prev_file = a != __null; + if (f7 (x, 1)) + return ((unsigned int) 0); + d = f7 (x, 1); + e = f7 (x, 1); + f = f7 (x, 1); + a = f8 (f5 (y, f4 (x), &t)); + if (e) b = f4 (x); + if (f) + if (d) + if (prev_file) + f2 (v1, 1, false, __null, 0); + return f3 (v1, c); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c new file mode 100644 index 000000000..4fe6aedb2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mapcs -g" } */ + +double bar(void); + +int foo(void) +{ + int i = bar() + bar(); + + return i; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c new file mode 100644 index 000000000..8c874b22e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-options "-O" } */ + +#include <stdlib.h> + +void __attribute__((noinline)) +bar(int a, int b) +{ + if (a != 43 || b != 42) + abort(); +} + +int main(void) +{ + register int r0 asm("r0") = 42; + register int r1 asm("r1") = 43; + asm volatile("": "+r" (r0), "+r" (r1)); + bar(r1, r0); + return 0; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c new file mode 100644 index 000000000..bd85e8640 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-g -fPIC" } */ + +void *v; +void a (void *x) { } +void b (void) { } + /* line 7. */ +int /* line 8. */ +main (int argc) /* line 9. */ +{ /* line 10. */ + if (argc == 12345) /* line 11. */ + { + a (v); + return 1; + } + b (); + + return 0; +} + +/* { dg-final { scan-assembler-not "\.loc 1 7 0" } } */ +/* { dg-final { scan-assembler-not "\.loc 1 8 0" } } */ +/* { dg-final { scan-assembler-not "\.loc 1 9 0" } } */ + +/* The loc at the start of the prologue. */ +/* { dg-final { scan-assembler-times "\.loc 1 10 0" 1 } } */ + +/* The loc at the end of the prologue, with the first user line. */ +/* { dg-final { scan-assembler-times "\.loc 1 11 0" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c new file mode 100644 index 000000000..ebde56a45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-require-effective-target arm_arch_v6_ok } */ +/* { dg-options "-O2 -marm" } */ +/* { dg-add-options arm_arch_v6 } */ + + +static inline int sat1 (int a, int amin, int amax) +{ + if (a < amin) return amin; + else if (a > amax) return amax; + else return a; +} + +static inline int sat2 (int a, int amin, int amax) +{ + if (a > amax) return amax; + else if (a < amin) return amin; + else return a; +} + +int u1 (int x) +{ + return sat1 (x, 0, 63); +} + +int us1 (int x) +{ + return sat1 (x >> 5, 0, 63); +} + +int s1 (int x) +{ + return sat1 (x, -64, 63); +} + +int ss1 (int x) +{ + return sat1 (x >> 5, -64, 63); +} + +int u2 (int x) +{ + return sat2 (x, 0, 63); +} + +int us2 (int x) +{ + return sat2 (x >> 5, 0, 63); +} + +int s2 (int x) +{ + return sat2 (x, -64, 63); +} + +int ss2 (int x) +{ + return sat2 (x >> 5, -64, 63); +} + +/* { dg-final { scan-assembler-times "usat" 4 } } */ +/* { dg-final { scan-assembler-times "ssat" 4 } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c new file mode 100644 index 000000000..2cd1eeb8f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c @@ -0,0 +1,16 @@ +/* Verify that mov is preferred on XScale for loading a 1 byte constant. */ +/* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "" } } */ +/* { dg-options "-mcpu=xscale -O" } */ + +unsigned load1(void) __attribute__ ((naked)); +unsigned load1(void) +{ + /* Best code would be: + mov r0, =17 + mov pc, lr */ + + return 17; +} + +/* { dg-final { scan-assembler "mov\[ ].*17" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c new file mode 100644 index 000000000..e07740234 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c @@ -0,0 +1,20 @@ +/* Verify that mov is preferred on XScale for loading a 2 byte constant. */ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xscale -O" } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ +/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ +/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ +/* { dg-require-effective-target arm32 } */ + +unsigned load2(void) __attribute__ ((naked)); +unsigned load2(void) +{ + /* Best code would be: + mov r0, =272 + add r0, r0, =1 + mov pc, lr */ + + return 273; +} + +/* { dg-final { scan-assembler "mov\[ ].*272" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c new file mode 100644 index 000000000..eb90e43c4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c @@ -0,0 +1,17 @@ +/* Verify that ldr is preferred on XScale for loading a 3 or 4 byte constant. */ +/* { dg-do compile } */ +/* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ +/* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ +/* { dg-options "-mcpu=xscale -O" } */ + +unsigned load4(void) __attribute__ ((naked)); +unsigned load4(void) +{ + /* Best code would be: + ldr r0, =65809 + mov pc, lr */ + + return 65809; +} + +/* { dg-final { scan-assembler "ldr\[ ].*" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c new file mode 100644 index 000000000..f3080620a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ + +/* ARM has shift-and-alu insns. Depending on the ALU op GCC represents some + of these as a left shift, others as a multiply. Check that we match the + right one. */ + +int +plus (int a, int b) +{ + return (a * 64) + b; +} + +/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */ + +int +minus (int a, int b) +{ + return a - (b * 64); +} + +/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */ + +int +ior (int a, int b) +{ + return (a * 64) | b; +} + +/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */ + +int +xor (int a, int b) +{ + return (a * 64) ^ b; +} + +/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */ + +int +and (int a, int b) +{ + return (a * 64) & b; +} + +/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */ + +int +rsb (int a, int b) +{ + return (a * 64) - b; +} + +/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */ + +int +mvn (int a, int b) +{ + return ~(a * 64); +} + +/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c new file mode 100644 index 000000000..cf352c12c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target { arm32 } } } */ +/* { dg-options "-O2" } */ + +#define noinline __attribute__((noinline)) + +typedef struct { + int data[4]; +} arr16_t; + +int result = 0; + +void noinline func2 (int i, int j, arr16_t arr) +{ + result = (arr.data[0] != 1 + || arr.data[1] != 2 + || arr.data[2] != 3 + || arr.data[3] != 4); +} + +void func1 (int i, int j, int k, int l, int m, int n, arr16_t a) +{ + func2(i, j, a); +} + +int main(int argc, const char *argv[]) +{ + arr16_t arr = {{1, 2, 3, 4}}; + + func1(0, 0, 0, 0, 0, 0, arr); + return result; +} + +/* The PLT marker may appear if the test is run with -fpic/-fPIC. */ +/* { dg-final { scan-assembler "\tb\tfunc2(\\(PLT\\))?\n" } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c new file mode 100644 index 000000000..921c0f302 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=aapcs" } */ + + +extern void __attribute__((weak)) wfunc(void); +void main(void) +{ + wfunc(); /* Must not tail-call. */ +} + +/* { dg-final { scan-assembler-not "b\[\\t \]+wfunc" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c new file mode 100644 index 000000000..a27009d25 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long int +foo (long long x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltb\\t" { xfail *-*-* } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c new file mode 100644 index 000000000..380e3d01b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +long long int +foo (long long x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltt\\t" { xfail *-*-* } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c new file mode 100644 index 000000000..d73aa18ea --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +int +foo (int x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatb\\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c new file mode 100644 index 000000000..d7fb03400 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O2" } */ + +int +foo (int x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatt\\t" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c new file mode 100644 index 000000000..cc44c6280 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-O -mthumb -fno-omit-frame-pointer" } */ + +int main() { + return 0; +} + +/* { dg-final { scan-assembler-not "\tadd\tr7, sp, #8\n" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c new file mode 100644 index 000000000..b9f0f9937 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c @@ -0,0 +1,12 @@ +/* No stack red zone. PR38644. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */ + +extern int doStreamReadBlock (int *, char *, int size, int); + +char readStream (int *s) +{ + char c = 0; + doStreamReadBlock (s, &c, 1, *s); + return c; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c new file mode 100644 index 000000000..25e812816 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target arm*-*-symbianelf* } } */ +/* Symbian OS requires that all defined symbols with external linkage + have the ELF STV_HIDDEN attribute set by default. */ +/* { dg-final { scan-assembler ".hidden.*i" } } */ +/* { dg-final { scan-assembler ".hidden.*j" } } */ +/* { dg-final { scan-assembler ".hidden.*f" } } */ + +int i; +int j = 3; +void f() {} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c new file mode 100644 index 000000000..987016368 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target arm*-*-symbianelf* } } */ +/* { dg-options "-O2" } */ + +/* Symbian OS requires that builtins not be expanded by default. Make + sure that a reference to "strlen" is emitted. */ +/* { dg-final { scan-assembler "strlen" } } */ + +int f() { + return strlen("abc"); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c new file mode 100644 index 000000000..2f11d355b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target arm*-*-symbianelf* } } */ +/* Check that enumeration types are 4-byte types. */ + +enum e { e_1 }; + +extern int i[sizeof (enum e)]; +int i[4]; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c new file mode 100644 index 000000000..aede7f5c6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c @@ -0,0 +1,5 @@ +/* { dg-do compile { target arm*-*-symbianelf* } } */ +/* Check that wchar_t is a 2-byte type. */ + +extern int i[sizeof (L'a')]; +int i[2]; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c new file mode 100644 index 000000000..0bde6b0cb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target arm*-*-symbianelf* } } */ +/* { dg-options "-fno-short-wchar" } */ +/* Check that wchar_t is a 4-byte type when -fno-short-wchar is + used. */ + +extern int i[sizeof (L'a')]; +int i[4]; + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c new file mode 100644 index 000000000..d1b648105 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c @@ -0,0 +1,26 @@ + +/* { dg-do run { target sync_int_long } } */ +/* { dg-options "-O2" } */ + +volatile int mem; + +int +bar (int x, int y) +{ + if (x) + __sync_fetch_and_add(&mem, y); + return 0; +} + +extern void abort (void); + +int +main (int argc, char *argv[]) +{ + mem = 0; + bar (0, 1); + bar (1, 1); + if (mem != 1) + abort (); + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c new file mode 100644 index 000000000..7ef10e2d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c @@ -0,0 +1,6 @@ +/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-* } } } */ + +void *foo (void) +{ + __sync_synchronize(); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c new file mode 100644 index 000000000..90407eb68 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c @@ -0,0 +1,203 @@ +/* Check that the compiler properly uses 16-bit encodings where available. */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -fno-builtin -mthumb" } */ + +int +f (int a, int b) +{ + return a + b; +} + +/* { dg-final { scan-assembler "add r0, r0, r1" } } */ + +int +f2 (int a, int b, int c) +{ + return b + c; +} + +/* { dg-final { scan-assembler "adds r0, r1, r2" } } */ +int +g1 (int a) +{ + return a + 255; +} + +/* { dg-final { scan-assembler "adds r0, r0, #255" } } */ + +int +g2 (int a) +{ + return a + 256; +} + +/* { dg-final { scan-assembler "add r0, r0, #256" } } */ + +int +g3 (int a) +{ + return a - 255; +} + +/* { dg-final { scan-assembler "subs r0, r0, #255" } } */ + +int +g4 (int a) +{ + return a - 256; +} + +/* { dg-final { scan-assembler "sub r0, r0, #256" } } */ + +int +h1 (int a, int b) +{ + return b + 7; +} + +/* { dg-final { scan-assembler "adds r0, r1, #7" } } */ + +int +h2 (int a, int b) +{ + return b + 8; +} + +/* { dg-final { scan-assembler "add r0, r1, #8" } } */ + +int +h3 (int a, int b) +{ + return b - 7; +} + +/* { dg-final { scan-assembler "subs r0, r1, #7" } } */ + +int +h4 (int a, int b) +{ + return b - 8; +} + +/* { dg-final { scan-assembler "sub r0, r1, #8" } } */ + +int +i (int a, int b) +{ + return b; +} + +/* { dg-final { scan-assembler "mov r0, r1" } } */ + +int +j1 () +{ + return 255; +} + +/* { dg-final { scan-assembler "movs r0, #255" } } */ + +int +j2 () +{ + return 256; +} + +/* { dg-final { scan-assembler "mov r0, #256" } } */ + +int +k (int a, int b) +{ + return b << 15; +} + +/* { dg-final { scan-assembler "lsls r0, r1, #15" } } */ + +int +l1 (int a, int b) +{ + return a << b; +} + +/* { dg-final { scan-assembler "lsls r0, r0, r1" } } */ + +int +l2 (int a, int b, int c) +{ + return b << c; +} + +/* { dg-final { scan-assembler "lsl r0, r1, r2" } } */ + +int +m (int a, int b) +{ + return b >> 15; +} + +/* { dg-final { scan-assembler "asrs r0, r1, #15" } } */ + +int +n1 (int a, int b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler "asrs r0, r0, r1" } } */ + +int +n2 (int a, int b, int c) +{ + return b >> c; +} + +/* { dg-final { scan-assembler "asr r0, r1, r2" } } */ + +unsigned int +o (unsigned int a, unsigned int b) +{ + return b >> 15; +} + +/* { dg-final { scan-assembler "lsrs r0, r1, #15" } } */ + +unsigned int +p1 (unsigned int a, unsigned int b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler "lsrs r0, r0, r1" } } */ + +unsigned int +p2 (unsigned int a, unsigned int b, unsigned int c) +{ + return b >> c; +} + +/* { dg-final { scan-assembler "lsr r0, r1, r2" } } */ + +int +q (int a, int b) +{ + return b * a; +} + +/* { dg-final { scan-assembler "muls r0, r1, r0" } } */ + +int +r (int a, int b) +{ + return ~b; +} + +/* { dg-final { scan-assembler "mvns r0, r1" } } */ + +int +s (int a, int b) +{ + return -b; +} + +/* { dg-final { scan-assembler "negs r0, r1" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c new file mode 100644 index 000000000..992d437c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +unsigned get_least_bits(unsigned value) +{ + return value << 9 >> 9; +} + +/* { dg-final { scan-assembler "lsl" } } */ +/* { dg-final { scan-assembler "lsr" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c new file mode 100644 index 000000000..ee39887d1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-O1 -mthumb" } */ + +struct foo +{ + unsigned b31 : 1; + unsigned b30 : 1; + unsigned b29 : 1; + unsigned b28 : 1; + unsigned rest : 28; +}; +foo(a) + struct foo a; +{ + return a.b30; +} + +/* { dg-final { scan-assembler-times "lsl" 1 } } */ +/* { dg-final { scan-assembler-times "lsr" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c new file mode 100644 index 000000000..73f6cf78a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ +/* { dg-options "-Os -mthumb" } */ + +int returnbool(int a, int b) +{ + if (a < b) + return 1; + return 0; +} + +/* { dg-final { scan-assembler-not "eor" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c new file mode 100644 index 000000000..22e90e7d2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +void +trap () +{ + __builtin_trap (); +} + +/* { dg-final { scan-assembler "0xdeff" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c new file mode 100644 index 000000000..5894df964 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int ldrb(unsigned char* p) +{ + if (p[8] <= 0x7F) + return 2; + else + return 5; +} + + +/* { dg-final { scan-assembler "127" } } */ +/* { dg-final { scan-assembler "bhi|bls" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c new file mode 100644 index 000000000..45be2cf74 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int foo(char ch) +{ + switch (ch) { + case '-': + case '?': + case '/': + case 99: + return 1; + default: + return 0; + } +} + +/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c new file mode 100644 index 000000000..f2c0225a4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c @@ -0,0 +1,40 @@ +/* Wrong method to get number of arg reg will cause argument corruption. */ +/* { dg-do run } */ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-options "-mthumb -O1" } */ + +extern void abort (void); + +int foo (int, int, int, int) __attribute__((noinline)); + +int +foo (int a, int b, int c, int d) +{ + register int m asm ("r8"); + + m = a; + m += b; + m += c; + m += d; + + asm ("" : "=r" (m) : "0" (m)); + + return m; +} + +int +main () +{ + volatile int a = 10; + volatile int b = 20; + volatile int c = 30; + volatile int d = 40; + volatile int sum = 0; + + sum = foo (a, b, c, d); + + if (sum != 100) + abort (); + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c new file mode 100644 index 000000000..3da9ef080 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c @@ -0,0 +1,18 @@ +/* Check that Thumb 16-bit shifts by immediate can be if-converted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb" } */ + +int +foo (int a, int b) +{ + if (a != b) + a = a << 1; + else + a = a >> 1; + + return a + b; +} + +/* { dg-final { scan-assembler "lslne" } } */ +/* { dg-final { scan-assembler "asreq" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c new file mode 100644 index 000000000..d51827aa7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c @@ -0,0 +1,19 @@ +/* Check that Thumb 16-bit shifts can be if-converted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb" } */ + +int +foo (int a, int b) +{ + if (a != b) + { + a = a << b; + a = a >> 1; + } + + return a + b; +} + +/* { dg-final { scan-assembler "lslne" } } */ +/* { dg-final { scan-assembler "asrne" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c new file mode 100644 index 000000000..d057ea34d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-mcpu=arm1136jf-s -mthumb -O2" } */ + +void f(unsigned a, unsigned b, unsigned c, unsigned d) +{ + if (a <= b || c > d) + foo(); + else + bar(); +} + +/* { dg-final { scan-assembler-not "uxtb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c new file mode 100644 index 000000000..f6c78804e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +extern void bar(int*); +int foo() +{ + int x; + bar(&x); + return x; +} + +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c new file mode 100644 index 000000000..31b8bd692 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +int +mymul3 (int x) +{ + return x * 0x555; +} + +/* { dg-final { scan-assembler "mul\[\\t \]*r.,\[\\t \]*r." } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c new file mode 100644 index 000000000..eb16d2fc9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c @@ -0,0 +1,34 @@ +/* Check for thumb1 far jump. Shouldn't save lr for small leaf functions + * even with a branch in it. */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +void f() +{ + for (;;); +} + +volatile int g; +void f2(int i) +{ + if (i) g=0; +} + +void f3(int i) +{ + if (i) { + g=0; + g=1; + g=2; + g=3; + g=4; + g=5; + g=6; + g=7; + g=8; + g=9; + } +} + +/* { dg-final { scan-assembler-not "push.*lr" } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c new file mode 100644 index 000000000..c6878f8ef --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c @@ -0,0 +1,57 @@ +/* Check for thumb1 far jump. This is the extreme case that far jump + * will be used with minimum number of instructions. By passing this case + * it means the heuristic of saving lr for far jump meets the most extreme + * requirement. */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +volatile register r4 asm("r4"); +void f3(int i) +{ +#define GO(n) \ + extern volatile int g_##n; \ + r4=(int)&g_##n; + +#define GO8(n) \ + GO(n##_0) \ + GO(n##_1) \ + GO(n##_2) \ + GO(n##_3) \ + GO(n##_4) \ + GO(n##_5) \ + GO(n##_6) \ + GO(n##_7) + +#define GO64(n) \ + GO8(n##_0) \ + GO8(n##_1) \ + GO8(n##_2) \ + GO8(n##_3) \ + GO8(n##_4) \ + GO8(n##_5) \ + GO8(n##_6) \ + GO8(n##_7) \ + +#define GO498(n) \ + GO64(n##_0) \ + GO64(n##_1) \ + GO64(n##_2) \ + GO64(n##_3) \ + GO64(n##_4) \ + GO64(n##_5) \ + GO64(n##_6) \ + GO8(n##_0) \ + GO8(n##_1) \ + GO8(n##_2) \ + GO8(n##_3) \ + GO8(n##_4) \ + GO8(n##_5) \ + GO(n##_0) \ + GO(n##_1) \ + + if (i) { + GO498(0); + } +} + +/* { dg-final { scan-assembler "push.*lr" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c new file mode 100644 index 000000000..90559bacb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c @@ -0,0 +1,108 @@ +/* Catch reload ICE on target thumb1 with far jump optimization. + * It is also a valid case for non-thumb1 target. */ + +/* Add -mno-lra option as it is only reproducable with reload. It will + be removed after reload is completely removed. */ +/* { dg-options "-mno-lra -fomit-frame-pointer" } */ +/* { dg-do compile } */ + +#define C 2 +#define A 4 +#define RGB (C | A) +#define GRAY (A) + +typedef unsigned long uint_32; +typedef unsigned char byte; +typedef byte * bytep; + +typedef struct ss +{ + uint_32 w; + uint_32 r; + byte c; + byte b; + byte p; +} info; + +typedef info * infop; + +void +foo(infop info, bytep row) +{ + uint_32 iw = info->w; + if (info->c == RGB) + { + if (info->b == 8) + { + bytep sp = row + info->r; + bytep dp = sp; + byte save; + uint_32 i; + + for (i = 0; i < iw; i++) + { + save = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = save; + } + } + + else + { + bytep sp = row + info->r; + bytep dp = sp; + byte save[2]; + uint_32 i; + + for (i = 0; i < iw; i++) + { + save[0] = *(--sp); + save[1] = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = save[0]; + *(--dp) = save[1]; + } + } + } + else if (info->c == GRAY) + { + if (info->b == 8) + { + bytep sp = row + info->r; + bytep dp = sp; + byte save; + uint_32 i; + + for (i = 0; i < iw; i++) + { + save = *(--sp); + *(--dp) = *(--sp); + *(--dp) = save; + } + } + else + { + bytep sp = row + info->r; + bytep dp = sp; + byte save[2]; + uint_32 i; + + for (i = 0; i < iw; i++) + { + save[0] = *(--sp); + save[1] = *(--sp); + *(--dp) = *(--sp); + *(--dp) = *(--sp); + *(--dp) = save[0]; + *(--dp) = save[1]; + } + } + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c new file mode 100644 index 000000000..6d950aa18 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c @@ -0,0 +1,12 @@ +/* Check for thumb1 imm [255-510] moves. */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +int f() +{ + return 257; +} + +/* { dg-final { scan-assembler-not "ldr" } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c new file mode 100644 index 000000000..6235774fe --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c @@ -0,0 +1,11 @@ +/* Check for unnecessary register moves. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int f(int x) +{ + return x*42; +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]*r0," } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c new file mode 100644 index 000000000..df269fc84 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-mthumb -fpic -mpic-register=9" } */ + +int g_test; + +int +foo (int par) +{ + g_test = par; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c new file mode 100644 index 000000000..6e9b2570a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-mthumb -fpic -msingle-pic-base" } */ + +int g_test; + +int +foo (int par) +{ + g_test = par; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c new file mode 100644 index 000000000..d75f13aa0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c @@ -0,0 +1,12 @@ +/* Use ADDS clobbering source operand, rather than CMN */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "adds" } } */ +/* { dg-final { scan-assembler-not "cmn" } } */ + +void foo1(void); +void bar5(int x) +{ + if (x == -15) + foo1(); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c new file mode 100644 index 000000000..358bc6e14 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c @@ -0,0 +1,12 @@ +/* Use ADDS with a scratch, rather than CMN */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "adds" } } */ +/* { dg-final { scan-assembler-not "cmn" } } */ + +void foo1(int); +void bar5(int x) +{ + if (x == -1) + foo1(x); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c new file mode 100644 index 000000000..45ab605e7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpne" } } */ + +int f(int i, int j) +{ + if ( (i == '+') || (j == '-') ) { + return 1; + } else { + return 0; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c new file mode 100644 index 000000000..17d9a8f76 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpeq" } } */ + +int f(int i, int j) +{ + if ( (i == '+') && (j == '-') ) { + return 1; + } else { + return 0; + } +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c new file mode 100644 index 000000000..6b2a79b1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j > '-') : 0) + return 1; + else + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c new file mode 100644 index 000000000..80e1076fd --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j <= '-') : 1) + return 1; + else + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c new file mode 100644 index 000000000..b53df2fa1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c @@ -0,0 +1,15 @@ +/* In Thumb-2 mode, when optimizing for size, generate a "muls" + instruction and use the resulting condition flags rather than a + separate compare instruction. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "muls" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ + +int x; + +void f(int i, int j) +{ + if (i * j < 0) + x = 1; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c new file mode 100644 index 000000000..143a6deee --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c @@ -0,0 +1,17 @@ +/* In Thumb-2 mode, when optimizing for size, generate a "muls" + instruction and use the resulting condition flags rather than a + separate compare instruction. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "muls" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ + +int x; + +int f(int i, int j) +{ + i = i * j; + if (i < 0) + x = 1; + return i; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c new file mode 100644 index 000000000..8cf0cb40f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c @@ -0,0 +1,10 @@ +/* Use 16-bit multiply instruction in Thumb-2 mode when optimizing for + size. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "muls" } } */ + +int f(int i, int j) +{ + return i * j; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c new file mode 100644 index 000000000..03cccdb65 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c @@ -0,0 +1,27 @@ +/* Do not use 16-bit multiply instructions in Thumb-2 mode when + optimizing for speed. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler-not "muls" } } */ + +int f(int i, int j) +{ + return i * j; +} + +int x; + +void g(int i, int j) +{ + if (i * j < 0) + x = 1; +} + +int h(int i, int j) +{ + i = i * j; + if (i < 0) + x = 1; + return i; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c new file mode 100644 index 000000000..e10ea0375 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c @@ -0,0 +1,27 @@ +/* Ensure simple replicated constant immediates work. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a + 0xfefefefe; +} + +/* { dg-final { scan-assembler "add.*#-16843010" } } */ + +int +foo2 (int a) +{ + return a - 0xab00ab00; +} + +/* { dg-final { scan-assembler "sub.*#-1426019584" } } */ + +int +foo3 (int a) +{ + return a & 0x00cd00cd; +} + +/* { dg-final { scan-assembler "and.*#13435085" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c new file mode 100644 index 000000000..3739adba5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c @@ -0,0 +1,75 @@ +/* Ensure split constants can use replicated patterns. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a + 0xfe00fe01; +} + +/* { dg-final { scan-assembler "add.*#-33489408" } } */ +/* { dg-final { scan-assembler "add.*#1" } } */ + +int +foo2 (int a) +{ + return a + 0xdd01dd00; +} + +/* { dg-final { scan-assembler "add.*#-587145984" } } */ +/* { dg-final { scan-assembler "add.*#65536" } } */ + +int +foo3 (int a) +{ + return a + 0x00443344; +} + +/* { dg-final { scan-assembler "add.*#4456516" } } */ +/* { dg-final { scan-assembler "add.*#13056" } } */ + +int +foo4 (int a) +{ + return a + 0x77330033; +} + +/* { dg-final { scan-assembler "add.*#1996488704" } } */ +/* { dg-final { scan-assembler "add.*#3342387" } } */ + +int +foo5 (int a) +{ + return a + 0x11221122; +} + +/* { dg-final { scan-assembler "add.*#285217024" } } */ +/* { dg-final { scan-assembler "add.*#2228258" } } */ + +int +foo6 (int a) +{ + return a + 0x66666677; +} + +/* { dg-final { scan-assembler "add.*#1717986918" } } */ +/* { dg-final { scan-assembler "add.*#17" } } */ + +int +foo7 (int a) +{ + return a + 0x99888888; +} + +/* { dg-final { scan-assembler "add.*#-2004318072" } } */ +/* { dg-final { scan-assembler "add.*#285212672" } } */ + +int +foo8 (int a) +{ + return a + 0xdddddfff; +} + +/* { dg-final { scan-assembler "add.*#-572662307" } } */ +/* { dg-final { scan-assembler "addw.*#546" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c new file mode 100644 index 000000000..eb6ad443c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c @@ -0,0 +1,28 @@ +/* Ensure negated/inverted replicated constant immediates work. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + return a | 0xffffff00; +} + +/* { dg-final { scan-assembler "orn.*#255" } } */ + +int +foo2 (int a) +{ + return a & 0xffeeffee; +} + +/* { dg-final { scan-assembler "bic.*#1114129" } } */ + +int +foo3 (int a) +{ + return a & 0xaaaaaa00; +} + +/* { dg-final { scan-assembler "and.*#-1431655766" } } */ +/* { dg-final { scan-assembler "bic.*#170" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c new file mode 100644 index 000000000..24efdcf34 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c @@ -0,0 +1,22 @@ +/* Ensure replicated constants don't make things worse. */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +int +foo1 (int a) +{ + /* It might be tempting to use 0x01000100, but it wouldn't help. */ + return a + 0x01f001e0; +} + +/* { dg-final { scan-assembler "add.*#32505856" } } */ +/* { dg-final { scan-assembler "add.*#480" } } */ + +int +foo2 (int a) +{ + return a + 0x0f100e10; +} + +/* { dg-final { scan-assembler "add.*#252706816" } } */ +/* { dg-final { scan-assembler "add.*#3600" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c new file mode 100644 index 000000000..9852ea5d0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c @@ -0,0 +1,74 @@ +/* The option -mslow-flash-data is just for performance tuning, it + doesn't totally disable the use of literal pools. But for below + simple cases, the use of literal pool should be replaced by + movw/movt or read-only constant pool. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_cortex_m } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb -mslow-flash-data" } */ + +float sf; +double df; +long long l; +static char *p = "Hello World"; + +float +testsf (float *p) +{ + if (*p > 1.1234f) + return 2.1234f; + else + return 3.1234f; +} + +double +testdf (double *p) +{ + if (*p > 4.1234) + return 2.1234; + else + return 3.1234; +} + +long long +testll (long long *p) +{ + if (*p > 0x123456789ABCDEFll) + return 0x111111111ll; + else + return 0x222222222ll; +} + +char * +testchar () +{ + return p + 4; +} + +int +foo (int a, int b) +{ + int i; + volatile *labelref = &&label1; + + if (a > b) + { + while (i < b) + { + a += *labelref; + i += 1; + } + goto *labelref; + } + else + b = b + 3; + + a = a * b; + +label1: + return a + b; +} + +/* { dg-final { scan-assembler-times "movt" 13 } } */ +/* { dg-final { scan-assembler-times "movt.*LC0\\+4" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c new file mode 100644 index 000000000..366c1ae71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c @@ -0,0 +1,31 @@ +/* Test non-duplication of tlscall insn */ + +/* { dg-do assemble } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +typedef struct _IO_FILE FILE; + +extern int foo(void); +extern int bar(void); + +void uuid__generate_time() +{ + static int has_init = 0; + static __thread int state_fd = -2; + static __thread FILE *state_f; + + if (!has_init) { + foo(); + has_init = 1; + } + + if (state_fd == -2) { + if (!state_f) { + state_fd = -1; + } + } + if (state_fd >= 0) { + while (bar() < 0) {} + } + +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c new file mode 100644 index 000000000..c4f564042 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +void unknown_alignment (char *dest, char *src) +{ + memcpy (dest, src, 15); +} + +/* We should see three unaligned word loads and store pairs, one unaligned + ldrh/strh pair, and an ldrb/strb pair. Sanity check that. */ + +/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c new file mode 100644 index 000000000..1ad730d64 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char dest[16] = { 0 }; + +void aligned_dest (char *src) +{ + memcpy (dest, src, 15); +} + +/* Expect a multi-word store for the main part of the copy, but subword + loads/stores for the remainder. */ + +/* { dg-final { scan-assembler-times "ldmia" 0 } } */ +/* { dg-final { scan-assembler-times "ldrd" 0 } } */ +/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler-times "strd" 1 { target { arm_prefer_ldrd_strd } } } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c new file mode 100644 index 000000000..d0b09bd48 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char src[16] = {0}; + +void aligned_src (char *dest) +{ + memcpy (dest, src, 15); +} + +/* Expect a multi-word load for the main part of the copy, but subword + loads/stores for the remainder. */ + +/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler-times "ldrd" 1 { target { arm_prefer_ldrd_strd } } } } */ +/* { dg-final { scan-assembler-times "strd" 0 } } */ +/* { dg-final { scan-assembler-times "stm" 0 } } */ +/* { dg-final { scan-assembler-times "ldrh" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler-times "strh" 1 } } */ +/* { dg-final { scan-assembler-times "ldrb" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler-times "strb" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c new file mode 100644 index 000000000..830e22e09 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_unaligned } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +char src[16] = { 0 }; +char dest[16] = { 0 }; + +void aligned_both (void) +{ + memcpy (dest, src, 15); +} + +/* We know both src and dest to be aligned: expect multiword loads/stores. */ + +/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ +/* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */ +/* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */ +/* { dg-final { scan-assembler "strd" { target { arm_prefer_ldrd_strd } } } } */ +/* { dg-final { scan-assembler-times "stm" 0 { target { arm_prefer_ldrd_strd } } } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c new file mode 100644 index 000000000..3b4ab048f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo (unsigned char c) +{ + return (c >= '0') && (c <= '9'); +} + +/* { dg-final { scan-assembler-not "uxtb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c new file mode 100644 index 000000000..b610b7361 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O" } */ + +unsigned short foo (unsigned short x) +{ + unsigned char i = 0; + for (i = 0; i < 8; i++) + { + x >>= 1; + x &= 0x7fff; + } + return x; +} + +/* { dg-final { scan-assembler "ands" } } */ +/* { dg-final { scan-assembler-not "uxtb" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c new file mode 100644 index 000000000..b988a0d33 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_eabi } */ + +#include <stdarg.h> +#include <stddef.h> + +/* AAPCS \S 7.1.4 requires that va_list match the structure shown + here */ +typedef struct my_va_list +{ + void *ap; +} my_va_list; + +int +main () { + if (sizeof (va_list) != sizeof (my_va_list)) + return 1; + /* This check confirms both that "va_list" has a member named "__ap" + and that it is located at the correct position. */ + if (offsetof (va_list, __ap) + != offsetof (my_va_list, ap)) + return 2; + + return 0; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c new file mode 100644 index 000000000..a934233a3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-mfpu=neon -ffast-math -ftree-vectorize -fno-common -O2 -mno-unaligned-access" } */ + + +/* Test for-mno-unaligned-access and -ftree-vectorize and results bus error. */ +#define N 128 + +char ia[N]; +char ib[N+1]; + +int main() { + int i; + for(i = 0; i < N; ++i) { + ia[i] = ib[i + 1]; + } + + return 0; +} + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c new file mode 100644 index 000000000..ff033d437 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +void +foo (float *output, float *input) +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_truncf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_btruncf } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c new file mode 100644 index 000000000..b54f358f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +void +foo (float *output, float *input) +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_ceilf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_ceilf } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c new file mode 100644 index 000000000..02e188d96 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +void +foo (float *output, float *input) +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_floorf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_floorf } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c new file mode 100644 index 000000000..85e205806 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +void +foo (float *output, float *input) +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_roundf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_roundf } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c new file mode 100644 index 000000000..d6d9c4642 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c @@ -0,0 +1,139 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ +/* { dg-require-effective-target arm_vfp_ok } */ + +extern float fabsf (float); +extern float sqrtf (float); +extern double fabs (double); +extern double sqrt (double); + +volatile float f1, f2, f3; + +void test_sf() { + /* abssf2_vfp */ + /* { dg-final { scan-assembler "fabss" } } */ + f1 = fabsf (f1); + /* negsf2_vfp */ + /* { dg-final { scan-assembler "fnegs" } } */ + f1 = -f1; + /* addsf3_vfp */ + /* { dg-final { scan-assembler "fadds" } } */ + f1 = f2 + f3; + /* subsf3_vfp */ + /* { dg-final { scan-assembler "fsubs" } } */ + f1 = f2 - f3; + /* divsf3_vfp */ + /* { dg-final { scan-assembler "fdivs" } } */ + f1 = f2 / f3; + /* mulsf3_vfp */ + /* { dg-final { scan-assembler "fmuls" } } */ + f1 = f2 * f3; + /* mulsf3negsf_vfp */ + /* { dg-final { scan-assembler "fnmuls" } } */ + f1 = -f2 * f3; + /* mulsf3addsf_vfp */ + /* { dg-final { scan-assembler "fmacs" } } */ + f1 = f2 * f3 + f1; + /* mulsf3subsf_vfp */ + /* { dg-final { scan-assembler "fmscs" } } */ + f1 = f2 * f3 - f1; + /* mulsf3negsfaddsf_vfp */ + /* { dg-final { scan-assembler "fnmacs" } } */ + f1 = f2 - f3 * f1; + /* mulsf3negsfsubsf_vfp */ + /* { dg-final { scan-assembler "fnmscs" } } */ + f1 = -f2 * f3 - f1; + /* sqrtsf2_vfp */ + /* { dg-final { scan-assembler "fsqrts" } } */ + f1 = sqrtf (f1); +} + +volatile double d1, d2, d3; + +void test_df() { + /* absdf2_vfp */ + /* { dg-final { scan-assembler "fabsd" } } */ + d1 = fabs (d1); + /* negdf2_vfp */ + /* { dg-final { scan-assembler "fnegd" } } */ + d1 = -d1; + /* adddf3_vfp */ + /* { dg-final { scan-assembler "faddd" } } */ + d1 = d2 + d3; + /* subdf3_vfp */ + /* { dg-final { scan-assembler "fsubd" } } */ + d1 = d2 - d3; + /* divdf3_vfp */ + /* { dg-final { scan-assembler "fdivd" } } */ + d1 = d2 / d3; + /* muldf3_vfp */ + /* { dg-final { scan-assembler "fmuld" } } */ + d1 = d2 * d3; + /* muldf3negdf_vfp */ + /* { dg-final { scan-assembler "fnmuld" } } */ + d1 = -d2 * d3; + /* muldf3adddf_vfp */ + /* { dg-final { scan-assembler "fmacd" } } */ + d1 = d2 * d3 + d1; + /* muldf3subdf_vfp */ + /* { dg-final { scan-assembler "fmscd" } } */ + d1 = d2 * d3 - d1; + /* muldf3negdfadddf_vfp */ + /* { dg-final { scan-assembler "fnmacd" } } */ + d1 = d2 - d3 * d1; + /* muldf3negdfsubdf_vfp */ + /* { dg-final { scan-assembler "fnmscd" } } */ + d1 = -d2 * d3 - d1; + /* sqrtdf2_vfp */ + /* { dg-final { scan-assembler "fsqrtd" } } */ + d1 = sqrt (d1); +} + +volatile int i1; +volatile unsigned int u1; + +void test_convert () { + /* extendsfdf2_vfp */ + /* { dg-final { scan-assembler "fcvtds" } } */ + d1 = f1; + /* truncdfsf2_vfp */ + /* { dg-final { scan-assembler "fcvtsd" } } */ + f1 = d1; + /* truncsisf2_vfp */ + /* { dg-final { scan-assembler "ftosizs" } } */ + i1 = f1; + /* truncsidf2_vfp */ + /* { dg-final { scan-assembler "ftosizd" } } */ + i1 = d1; + /* fixuns_truncsfsi2 */ + /* { dg-final { scan-assembler "ftouizs" } } */ + u1 = f1; + /* fixuns_truncdfsi2 */ + /* { dg-final { scan-assembler "ftouizd" } } */ + u1 = d1; + /* floatsisf2_vfp */ + /* { dg-final { scan-assembler "fsitos" } } */ + f1 = i1; + /* floatsidf2_vfp */ + /* { dg-final { scan-assembler "fsitod" } } */ + d1 = i1; + /* floatunssisf2 */ + /* { dg-final { scan-assembler "fuitos" } } */ + f1 = u1; + /* floatunssidf2 */ + /* { dg-final { scan-assembler "fuitod" } } */ + d1 = u1; +} + +void test_ldst (float f[], double d[]) { + /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */ + /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ + /* { dg-final { scan-assembler "add.+ r0, #1024" } } */ + /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */ + f[256] = f[255] + f[-255]; + + /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */ + /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ + /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */ + d[32] = d[127] + d[-127]; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c new file mode 100644 index 000000000..280471496 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +extern void bar (double); + +void +foo (double *p, double a, int n) +{ + do + bar (*--p + a); + while (n--); +} + +/* { dg-final { scan-assembler "fldmdbd" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c new file mode 100644 index 000000000..f5940ef97 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +extern void baz (float); + +void +foo (float *p, float a, int n) +{ + do + bar (*--p + a); + while (n--); +} + +/* { dg-final { scan-assembler "fldmdbs" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c new file mode 100644 index 000000000..6f0526712 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +extern void bar (double); + +void +foo (double *p, double a, int n) +{ + do + bar (*p++ + a); + while (n--); +} + +/* { dg-final { scan-assembler "fldmiad" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c new file mode 100644 index 000000000..79ad7bf17 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +extern void baz (float); + +void +foo (float *p, float a, int n) +{ + do + bar (*p++ + a); + while (n--); +} + +/* { dg-final { scan-assembler "fldmias" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c new file mode 100644 index 000000000..d8093d9d4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +void +foo (double *p, double a, double b, int n) +{ + double c = a + b; + do + *--p = c; + while (n--); +} + +/* { dg-final { scan-assembler "fstmdbd" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c new file mode 100644 index 000000000..bb19d902b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +void +foo (float *p, float a, float b, int n) +{ + float c = a + b; + do + *--p = c; + while (n--); +} + +/* { dg-final { scan-assembler "fstmdbs" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c new file mode 100644 index 000000000..1b6d22bd8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +void +foo (double *p, double a, double b, int n) +{ + double c = a + b; + do + *p++ = c; + while (n--); +} + +/* { dg-final { scan-assembler "fstmiad" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c new file mode 100644 index 000000000..3da632745 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp_ok } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ + +void +foo (float *p, float a, float b, int n) +{ + float c = a + b; + do + *p++ = c; + while (n--); +} + +/* { dg-final { scan-assembler "fstmias" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c new file mode 100644 index 000000000..1a172b8c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + return __builtin_fmax (x, y); +} + +/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c new file mode 100644 index 000000000..bc2326187 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + return __builtin_fmaxf (x, y); +} + +/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c new file mode 100644 index 000000000..c2a6915b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + return __builtin_fmin (x, y); +} + +/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c new file mode 100644 index 000000000..eee43bce1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + return __builtin_fminf (x, y); +} + +/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c new file mode 100644 index 000000000..c519419cc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c @@ -0,0 +1,18 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct { + char a:1; + char b:7; + int c; +} BitStruct; + +volatile BitStruct bits; + +int foo () +{ + return bits.b; +} + +/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c new file mode 100644 index 000000000..eb0aaf7f7 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c @@ -0,0 +1,18 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct { + volatile unsigned long a:8; + volatile unsigned long b:8; + volatile unsigned long c:16; +} BitStruct; + +BitStruct bits; + +unsigned long foo () +{ + return bits.b; +} + +/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c new file mode 100644 index 000000000..0f5dde08b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c @@ -0,0 +1,18 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct { + volatile unsigned long a:8; + volatile unsigned long b:8; + volatile unsigned long c:16; +} BitStruct; + +BitStruct bits; + +unsigned long foo () +{ + return bits.c; +} + +/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c new file mode 100644 index 000000000..805dab164 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c @@ -0,0 +1,30 @@ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ +/* { dg-final { scan-assembler-not "strb" } } */ + +struct thing { + unsigned a: 8; + unsigned b: 8; + unsigned c: 8; + unsigned d: 8; +}; + +struct thing2 { + volatile unsigned a: 8; + volatile unsigned b: 8; + volatile unsigned c: 8; + volatile unsigned d: 8; +}; + +void test1(volatile struct thing *t) +{ + t->a = 5; +} + +void test2(struct thing2 *t) +{ + t->a = 5; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c new file mode 100644 index 000000000..71c5b3b0e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -marm -march=armv8-a" } */ +/* { dg-add-options arm_v8_vfp } */ + +double foo (double a) +{ + if (a > 3.0) + return __builtin_round (a); + + return 0.0; +} + +/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */ + diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c new file mode 100644 index 000000000..bea4aca55 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_roundf (x); +} + +/* { dg-final { scan-assembler-times "vrinta.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c new file mode 100644 index 000000000..0c393474f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_round (x); +} + +/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c new file mode 100644 index 000000000..33c22885f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_floorf (x); +} + +/* { dg-final { scan-assembler-times "vrintm.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c new file mode 100644 index 000000000..d1b3db964 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_floor (x); +} + +/* { dg-final { scan-assembler-times "vrintm.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c new file mode 100644 index 000000000..ecea15db6 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_ceilf (x); +} + +/* { dg-final { scan-assembler-times "vrintp.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c new file mode 100644 index 000000000..a4ce30d64 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_ceil (x); +} + +/* { dg-final { scan-assembler-times "vrintp.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c new file mode 100644 index 000000000..f1b03be5c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_nearbyintf (x); +} + +/* { dg-final { scan-assembler-times "vrintr.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c new file mode 100644 index 000000000..3f8171898 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_nearbyint (x); +} + +/* { dg-final { scan-assembler-times "vrintr.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c new file mode 100644 index 000000000..ca00b0f51 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_rintf (x); +} + +/* { dg-final { scan-assembler-times "vrintx.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c new file mode 100644 index 000000000..9b8604887 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_rint (x); +} + +/* { dg-final { scan-assembler-times "vrintx.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c new file mode 100644 index 000000000..c76bf6e99 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x) +{ + return __builtin_truncf (x); +} + +/* { dg-final { scan-assembler-times "vrintz.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c new file mode 100644 index 000000000..602e876f5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x) +{ + return __builtin_trunc (x); +} + +/* { dg-final { scan-assembler-times "vrintz.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c new file mode 100644 index 000000000..86e147b1f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i == 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c new file mode 100644 index 000000000..120f44bf0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i == 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c new file mode 100644 index 000000000..cea08d12e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i >= 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c new file mode 100644 index 000000000..86f2a0490 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i >= 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c new file mode 100644 index 000000000..2c4a6ba90 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i > 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c new file mode 100644 index 000000000..388e74c11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i > 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c new file mode 100644 index 000000000..088dc04b2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i <= 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c new file mode 100644 index 000000000..d0afdbcec --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i <= 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c new file mode 100644 index 000000000..fbcb9ea2b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i < 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c new file mode 100644 index 000000000..959dab7fa --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i < 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c new file mode 100644 index 000000000..cf67f29f3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + volatile int i = 0; + return i != 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c new file mode 100644 index 000000000..2e16423b5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + volatile int i = 0; + return i != 0 ? x : y; +} + +/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c new file mode 100644 index 000000000..7f30270c5 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + return !__builtin_isunordered (x, y) ? x : y; +} + +/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c new file mode 100644 index 000000000..1bb736925 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + return !__builtin_isunordered (x, y) ? x : y; +} + +/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c new file mode 100644 index 000000000..83ad5bf69 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +double +foo (double x, double y) +{ + return __builtin_isunordered (x, y) ? x : y; +} + +/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c new file mode 100644 index 000000000..7d762899c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_v8_vfp } */ + +float +foo (float x, float y) +{ + return __builtin_isunordered (x, y) ? x : y; +} + +/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c new file mode 100644 index 000000000..ddddd509f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ + +int mac(const short *a, const short *b, int sqr, int *sum) +{ + int i; + int dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp += b[i] * a[i]; + sqr += b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "smlabb" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c new file mode 100644 index 000000000..5ffd169ba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + + +unsigned long long +foo (unsigned short a, unsigned short *b, unsigned short *c) +{ + return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c new file mode 100644 index 000000000..904f0153a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *b) +{ + return 10 * (long long)*b; +} + +/* { dg-final { scan-assembler "smull" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c new file mode 100644 index 000000000..5c6b5b988 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *b, int *c) +{ + long long tmp = (long long)*b * *c; + return 10 + tmp; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c new file mode 100644 index 000000000..a73d80f63 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (int *a, int *b) +{ + return *a + (long long)*b * 10; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c new file mode 100644 index 000000000..2ea55f9fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ + +void vec_mpy(int y[], const short x[], short scaler) +{ + int i; + + for (i = 0; i < 150; i++) + y[i] += ((scaler * x[i]) >> 31); +} + +/* { dg-final { scan-assembler-times "smulbb" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c new file mode 100644 index 000000000..144b55308 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ + +int mac(const short *a, const short *b, int sqr, int *sum) +{ + int i; + int dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp -= b[i] * a[i]; + sqr -= b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "smulbb" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c new file mode 100644 index 000000000..68f986674 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_dsp } */ +/* { dg-options "-O1 -fexpensive-optimizations" } */ + +int mac(const int *a, const int *b, long long sqr, long long *sum) +{ + int i; + long long dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp += (long long) b[i] * a[i]; + sqr += (long long) b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "smlal" 2 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c new file mode 100644 index 000000000..9f29a81c0 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, char *b, char *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c new file mode 100644 index 000000000..babdaab1e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, unsigned char *b, signed char *c) +{ + return a + (long long)*b * (long long)*c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c new file mode 100644 index 000000000..2db4ad4e1 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +unsigned long long +foo (unsigned long long a, unsigned char *b, unsigned short *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "umlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c new file mode 100644 index 000000000..5ae110d3c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, int *b, int *c) +{ + return a + (long long)*b * *c; +} + +/* { dg-final { scan-assembler "smlal" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c new file mode 100644 index 000000000..40ed0219a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +long long +foo (long long a, short *b, char *c) +{ + return a + *b * *c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c new file mode 100644 index 000000000..2e9da5923 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +struct bf +{ + int a : 3; + int b : 15; + int c : 3; +}; + +long long +foo (long long a, struct bf b, struct bf c) +{ + return a + b.b * c.b; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c new file mode 100644 index 000000000..07ba9a84d --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_dsp } */ + +struct bf +{ + int a : 3; + unsigned int b : 15; + int c : 3; +}; + +long long +foo (long long a, struct bf b, struct bf c) +{ + return a + b.b * c.c; +} + +/* { dg-final { scan-assembler "smlalbb" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c new file mode 100644 index 000000000..53dff85f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv6" } */ +/* { dg-prune-output "switch .* conflicts with" } */ + +unsigned short foo (unsigned short x) +{ + x ^= 0x4002; + x >>= 1; + x |= 0x8000; + return x; +} + +/* { dg-final { scan-assembler "orr" } } */ +/* { dg-final { scan-assembler-not "mvn" } } */ +/* { dg-final { scan-assembler-not "uxth" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c new file mode 100644 index 000000000..7e031c3af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +unsigned long long xor64 (unsigned long long input) +{ + return input ^ 0x200000004ULL; +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ |