diff options
Diffstat (limited to 'binutils-2.25/include/opcode')
65 files changed, 1295 insertions, 333 deletions
diff --git a/binutils-2.25/include/opcode/ChangeLog b/binutils-2.25/include/opcode/ChangeLog index f645a7e7..d378910e 100644 --- a/binutils-2.25/include/opcode/ChangeLog +++ b/binutils-2.25/include/opcode/ChangeLog @@ -1,3 +1,169 @@ +2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc.h (sparc_opcode): new field `hwcaps2'. + (HWCAP2_FJATHPLUS): New define. + (HWCAP2_VIS3B): Likewise. + (HWCAP2_ADP): Likewise. + (HWCAP2_SPARC5): Likewise. + (HWCAP2_MWAIT): Likewise. + (HWCAP2_XMPMUL): Likewise. + (HWCAP2_XMONT): Likewise. + (HWCAP2_NSEC): Likewise. + (HWCAP2_FJATHHPC): Likewise. + (HWCAP2_FJDES): Likewise. + (HWCAP2_FJAES): Likewise. + Document the new operand kind `{', corresponding to the mcdper + ancillary state register. + Document the new operand kind }, which represents frsd floating + point registers (double precision) which must be the same than + frs1 in its containing instruction. + +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * nds32.h: Add new opcode declaration. + +2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> + Matthew Fortune <matthew.fortune@imgtec.com> + + * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, + OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 + instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, + +I, +O, +R, +:, +\, +", +; + (mips_check_prev_operand): New struct. + (INSN2_FORBIDDEN_SLOT): New define. + (INSN_ISA32R6): New define. + (INSN_ISA64R6): New define. + (INSN_UPTO32R6): New define. + (INSN_UPTO64R6): New define. + (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. + (ISA_MIPS32R6): New define. + (ISA_MIPS64R6): New define. + (CPU_MIPS32R6): New define. + (CPU_MIPS64R6): New define. + (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. + +2014-09-03 Jiong Wang <jiong.wang@arm.com> + + * aarch64.h (AARCH64_FEATURE_LSE): New feature added. + (aarch64_opnd): Add AARCH64_OPND_PAIRREG. + (aarch64_insn_class): Add lse_atomic. + (F_LSE_SZ): New field added. + (opcode_has_special_coder): Recognize F_LSE_SZ. + +2014-08-26 Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' + over to `+J'. + +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... + (INSN_LOAD_COPROC): New define. + (INSN_COPROC_MOVE_DELAY): Rename to... + (INSN_COPROC_MOVE): New define. + +2014-07-01 Barney Stratford <barney_stratford@fastmail.fm> + Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + Pitchumani Sivanupandi <pitchumani.s@atmel.com> + Soundararajan <Sounderarajan.D@atmel.com> + + * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. + (AVR_ISA_2xxxa): Define ISA without LPM. + (AVR_ISA_AVRTINY): Define avrtiny arch ISA. + Add doc for contraint used in 16 bit lds/sts. + Adjust ISA group for icall, ijmp, pop and push. + Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. + +2014-05-19 Nick Clifton <nickc@redhat.com> + + * msp430.h (struct msp430_operand_s): Add vshift field. + +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2014-04-22 Christian Svensson <blue@cmd.nu> + + * or32.h: Delete. + +2014-03-05 Alan Modra <amodra@gmail.com> + + Update copyright years. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + +2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com> + Wei-Cheng Wang <cole945@gmail.com> + + * nds32.h: New file for Andes NDS32. + +2013-12-07 Mike Frysinger <vapier@gentoo.org> + + * bfin.h: Remove +x file mode. + +2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_pstatefields): Change element type to + aarch64_sys_reg. + +2013-11-18 Renlin Li <Renlin.Li@arm.com> + + * arm.h (ARM_AEXT_V7VE): New define. + (ARM_ARCH_V7VE): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed. + +2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> + + Revert + + 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg): New typedef. + (aarch64_sys_regs): Change to define with the new type. + (aarch64_sys_reg_deprecated_p): Declare. + +2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. + (enum aarch64_opnd): Add AARCH64_OPND_COND1. + 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. @@ -1902,7 +2068,7 @@ For older changes see ChangeLog-9103 -Copyright (C) 2004-2012 Free Software Foundation, Inc. +Copyright (C) 2004-2014 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/binutils-2.25/include/opcode/aarch64.h b/binutils-2.25/include/opcode/aarch64.h index eaf3cda5..c0afd74a 100644 --- a/binutils-2.25/include/opcode/aarch64.h +++ b/binutils-2.25/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright (C) 2009-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -38,6 +38,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ +#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -85,6 +86,7 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_ADDRESS, AARCH64_OPND_CLASS_IMMEDIATE, AARCH64_OPND_CLASS_SYSTEM, + AARCH64_OPND_CLASS_COND, }; /* Operand code that helps both parsing and coding. @@ -105,6 +107,7 @@ enum aarch64_opnd AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ @@ -168,6 +171,7 @@ enum aarch64_opnd AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ AARCH64_OPND_COND, /* Standard condition as the last operand. */ + AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ @@ -338,6 +342,7 @@ enum aarch64_insn_class loadlit, log_imm, log_shift, + lse_atomic, movewide, pcreladdr, ic_system, @@ -548,7 +553,9 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_N (1 << 23) /* Opcode dependent field. */ #define F_OD(X) (((X) & 0x7) << 24) -/* Next bit is 27. */ +/* Instruction has the field of 'sz'. */ +#define F_LSE_SZ (1 << 27) +/* Next bit is 28. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -597,7 +604,7 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) static inline bfd_boolean opcode_has_special_coder (const aarch64_opcode *opcode) { - return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T + return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE : FALSE; } @@ -609,13 +616,22 @@ struct aarch64_name_value_pair }; extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; -extern const struct aarch64_name_value_pair aarch64_sys_regs []; -extern const struct aarch64_name_value_pair aarch64_pstatefields []; extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; extern const struct aarch64_name_value_pair aarch64_prfops [32]; typedef struct { + const char * name; + aarch64_insn value; + uint32_t flags; +} aarch64_sys_reg; + +extern const aarch64_sys_reg aarch64_sys_regs []; +extern const aarch64_sys_reg aarch64_pstatefields []; +extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); + +typedef struct +{ const char *template; uint32_t value; int has_xt; diff --git a/binutils-2.25/include/opcode/alpha.h b/binutils-2.25/include/opcode/alpha.h index 2c0d4f6c..121c831e 100644 --- a/binutils-2.25/include/opcode/alpha.h +++ b/binutils-2.25/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. diff --git a/binutils-2.25/include/opcode/arc.h b/binutils-2.25/include/opcode/arc.h index 695fec1e..6ababaa7 100644 --- a/binutils-2.25/include/opcode/arc.h +++ b/binutils-2.25/include/opcode/arc.h @@ -1,6 +1,5 @@ /* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 - Free Software Foundation, Inc. + Copyright (C) 1994-2014 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and diff --git a/binutils-2.25/include/opcode/arm.h b/binutils-2.25/include/opcode/arm.h index 851fd3c8..6d4825aa 100644 --- a/binutils-2.25/include/opcode/arm.h +++ b/binutils-2.25/include/opcode/arm.h @@ -1,5 +1,5 @@ /* ARM assembler/disassembler support. - Copyright 2004, 2010, 2011 Free Software Foundation, Inc. + Copyright (C) 2004-2014 Free Software Foundation, Inc. This file is part of GDB and GAS. @@ -116,6 +116,8 @@ #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) +#define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ + | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP) #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) #define ARM_AEXT_NOTM \ (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ @@ -224,6 +226,7 @@ #define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) +#define ARM_ARCH_V7VE ARM_FEATURE (ARM_AEXT_V7VE, 0) #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) @@ -241,11 +244,6 @@ #define ARM_ARCH_V7A_MP_SEC \ ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ 0) -/* v7-a+idiv+mp+sec+virt. */ -#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \ - ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \ - | ARM_EXT_DIV | ARM_EXT_ADIV \ - | ARM_EXT_VIRT, 0) /* v7-r+idiv. */ #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) /* Features that are present in v6M and v6S-M but not other v6 cores. */ diff --git a/binutils-2.25/include/opcode/avr.h b/binutils-2.25/include/opcode/avr.h index f1d73ad9..56838486 100644 --- a/binutils-2.25/include/opcode/avr.h +++ b/binutils-2.25/include/opcode/avr.h @@ -1,6 +1,6 @@ /* Opcode table for the Atmel AVR micro controllers. - Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc. + Copyright (C) 2000-2014 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This program is free software; you can redistribute it and/or modify @@ -22,6 +22,7 @@ #define AVR_ISA_LPM 0x0002 /* device has LPM */ #define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ #define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ +#define AVR_ISA_TINY 0x0010 /* device has Tiny core specific encodings */ #define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL supported, no 8K wrap on RJMP and RCALL) */ #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ @@ -37,6 +38,7 @@ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) +#define AVR_ISA_2xxxa (AVR_ISA_1200 | AVR_ISA_SRAM) /* For the attiny26 which is missing LPM Rd,Z+. */ #define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) @@ -72,6 +74,9 @@ AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW) +#define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \ + AVR_ISA_TINY) + #define REGISTER_P(x) ((x) == 'r' \ || (x) == 'd' \ || (x) == 'w' \ @@ -94,7 +99,7 @@ `ld r,b' or `st b,r' respectively - next opcode entry)? */ #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) -/* constraint letters +/* Constraint letters: r - any register d - `ldi' register (r16-r31) v - `movw' even register (r0, r2, ..., r28, r30) @@ -110,6 +115,7 @@ p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) K - immediate value from 0 to 63 (used in `adiw', `sbiw') i - immediate value + j - 7 bit immediate value from 0x40 to 0xBF (for 16-bit 'lds'/'sts') l - signed pc relative offset from -64 to 63 L - signed pc relative offset from -2048 to 2047 h - absolute code address (call, jmp) @@ -156,12 +162,12 @@ AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) - /* Same as {cl,se}[chinstvz] above. */ +/* Same as {cl,se}[chinstvz] above. */ AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) -AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) -AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) +AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxxa,0x9509) +AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxxa,0x9409) AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) @@ -190,7 +196,7 @@ AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) - /* Shorthand for {eor,add,adc,and} r,r above. */ +/* Shorthand for {eor,add,adc,and} r,r above. */ AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) @@ -245,7 +251,7 @@ AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) - /* Same as br?? above. */ +/* Same as br?? above. */ AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) @@ -261,18 +267,18 @@ AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) -AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) -AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) +AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxxa,0x900f) +AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxxa,0x920f) AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) - /* Atomic memory operations for XMEGA. List before `sts'. */ +/* Atomic memory operations for XMEGA. List before `sts'. */ AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) - /* Known to be decoded as `nop' by the old core. */ +/* Known to be decoded as `nop' by the old core. */ AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) @@ -280,21 +286,23 @@ AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) -AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) -AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) +AVR_INSN (sts, "j,d", "10101kkkddddkkkk", 1, AVR_ISA_TINY, 0xA800) +AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) +AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000) +AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) - /* Special case for b+0, `e' must be next entry after `b', - b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ +/* Special case for b+0, `e' must be next entry after `b', + b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) - /* These are for devices that don't exist yet - (>128K program memory, PC = EIND:Z). */ +/* These are for devices that don't exist yet + (>128K program memory, PC = EIND:Z). */ AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) -/* DES instruction for encryption and decryption */ +/* DES instruction for encryption and decryption. */ AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) diff --git a/binutils-2.25/include/opcode/bfin.h b/binutils-2.25/include/opcode/bfin.h index 26f01938..fafe0d8a 100755..100644 --- a/binutils-2.25/include/opcode/bfin.h +++ b/binutils-2.25/include/opcode/bfin.h @@ -1,5 +1,5 @@ /* bfin.h -- Header file for ADI Blackfin opcode table - Copyright 2005, 2010, 2011 Free Software Foundation, Inc. + Copyright (C) 2005-2014 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/cgen.h b/binutils-2.25/include/opcode/cgen.h index b7e82d4d..905ae9a5 100644 --- a/binutils-2.25/include/opcode/cgen.h +++ b/binutils-2.25/include/opcode/cgen.h @@ -1,7 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010 - Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. diff --git a/binutils-2.25/include/opcode/convex.h b/binutils-2.25/include/opcode/convex.h index 4643f5e0..cbf7076a 100644 --- a/binutils-2.25/include/opcode/convex.h +++ b/binutils-2.25/include/opcode/convex.h @@ -1,5 +1,5 @@ /* Information for instruction disassembly on the Convex. - Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GDB. diff --git a/binutils-2.25/include/opcode/cr16.h b/binutils-2.25/include/opcode/cr16.h index 1f1191dc..e4050dc3 100644 --- a/binutils-2.25/include/opcode/cr16.h +++ b/binutils-2.25/include/opcode/cr16.h @@ -1,5 +1,5 @@ /* cr16.h -- Header file for CR16 opcode and register tables. - Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc. + Copyright (C) 2007-2014 Free Software Foundation, Inc. Contributed by M R Swami Reddy This file is part of GAS, GDB and the GNU binutils. diff --git a/binutils-2.25/include/opcode/cris.h b/binutils-2.25/include/opcode/cris.h index e57a8825..ea0b135c 100644 --- a/binutils-2.25/include/opcode/cris.h +++ b/binutils-2.25/include/opcode/cris.h @@ -1,5 +1,5 @@ /* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc. + Copyright (C) 2000-2014 Free Software Foundation, Inc. Contributed by Axis Communications AB, Lund, Sweden. Originally written for GAS 1.38.1 by Mikael Asker. Updated, BFDized and GNUified by Hans-Peter Nilsson. diff --git a/binutils-2.25/include/opcode/crx.h b/binutils-2.25/include/opcode/crx.h index 6081ea35..8c305b45 100644 --- a/binutils-2.25/include/opcode/crx.h +++ b/binutils-2.25/include/opcode/crx.h @@ -1,5 +1,5 @@ /* crx.h -- Header file for CRX opcode and register tables. - Copyright 2004, 2010, 2012 Free Software Foundation, Inc. + Copyright (C) 2004-2014 Free Software Foundation, Inc. Contributed by Tomer Levi, NSC, Israel. Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. Updates, BFDizing, GNUifying and ELF support by Tomer Levi. diff --git a/binutils-2.25/include/opcode/d10v.h b/binutils-2.25/include/opcode/d10v.h index d0e115fa..1451f437 100644 --- a/binutils-2.25/include/opcode/d10v.h +++ b/binutils-2.25/include/opcode/d10v.h @@ -1,6 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010 - Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/d30v.h b/binutils-2.25/include/opcode/d30v.h index 62c041da..3c08729e 100644 --- a/binutils-2.25/include/opcode/d30v.h +++ b/binutils-2.25/include/opcode/d30v.h @@ -1,6 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010 - Free Software Foundation, Inc. + Copyright (C) 1997-2014 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/dlx.h b/binutils-2.25/include/opcode/dlx.h index 54dadd07..19aff9ab 100644 --- a/binutils-2.25/include/opcode/dlx.h +++ b/binutils-2.25/include/opcode/dlx.h @@ -1,5 +1,5 @@ /* Table of opcodes for the DLX microprocess. - Copyright 2002, 2010 Free Software Foundation, Inc. + Copyright (C) 2002-2014 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/binutils-2.25/include/opcode/h8300.h b/binutils-2.25/include/opcode/h8300.h index 3296deba..63b5682e 100644 --- a/binutils-2.25/include/opcode/h8300.h +++ b/binutils-2.25/include/opcode/h8300.h @@ -1,5 +1,5 @@ /* Opcode table for the H8/300 - Copyright 1991-2013 Free Software Foundation, Inc. + Copyright (C) 1991-2014 Free Software Foundation, Inc. Written by Steve Chamberlain <sac@cygnus.com>. This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/binutils-2.25/include/opcode/hppa.h b/binutils-2.25/include/opcode/hppa.h index 489ca550..a9f87af0 100644 --- a/binutils-2.25/include/opcode/hppa.h +++ b/binutils-2.25/include/opcode/hppa.h @@ -1,7 +1,5 @@ /* Table of opcodes for the PA-RISC. - Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, - 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010 - Free Software Foundation, Inc. + Copyright (C) 1990-2014 Free Software Foundation, Inc. Contributed by the Center for Software Science at the University of Utah (pa-gdb-bugs@cs.utah.edu). diff --git a/binutils-2.25/include/opcode/i370.h b/binutils-2.25/include/opcode/i370.h index e3b7166d..4f346502 100644 --- a/binutils-2.25/include/opcode/i370.h +++ b/binutils-2.25/include/opcode/i370.h @@ -1,6 +1,5 @@ /* i370.h -- Header file for S/390 opcode table - Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010 - Free Software Foundation, Inc. + Copyright (C) 1994-2014 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> diff --git a/binutils-2.25/include/opcode/i386.h b/binutils-2.25/include/opcode/i386.h index 6021002b..160a76f2 100644 --- a/binutils-2.25/include/opcode/i386.h +++ b/binutils-2.25/include/opcode/i386.h @@ -1,7 +1,5 @@ /* opcode/i386.h -- Intel 80386 opcode macros - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 - Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. diff --git a/binutils-2.25/include/opcode/i860.h b/binutils-2.25/include/opcode/i860.h index 7f4aafd9..70f0ea79 100644 --- a/binutils-2.25/include/opcode/i860.h +++ b/binutils-2.25/include/opcode/i860.h @@ -1,6 +1,5 @@ /* Table of opcodes for the i860. - Copyright 1989, 1991, 2000, 2002, 2003, 2010 - Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. diff --git a/binutils-2.25/include/opcode/i960.h b/binutils-2.25/include/opcode/i960.h index 7b8e1f5d..650b6dac 100644 --- a/binutils-2.25/include/opcode/i960.h +++ b/binutils-2.25/include/opcode/i960.h @@ -1,6 +1,6 @@ /* Basic 80960 instruction formats. - Copyright 2001-2013 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/ia64.h b/binutils-2.25/include/opcode/ia64.h index 433c5058..f18353f2 100644 --- a/binutils-2.25/include/opcode/ia64.h +++ b/binutils-2.25/include/opcode/ia64.h @@ -1,6 +1,5 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010 - Free Software Foundation, Inc. + Copyright (C) 1998-2014 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of BFD, the Binary File Descriptor library. diff --git a/binutils-2.25/include/opcode/m68hc11.h b/binutils-2.25/include/opcode/m68hc11.h index 1a002008..8781e6c0 100644 --- a/binutils-2.25/include/opcode/m68hc11.h +++ b/binutils-2.25/include/opcode/m68hc11.h @@ -1,6 +1,5 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000, 2002, 2003, 2010, 2012 - Free Software Foundation, Inc. + Copyright (C) 1999-2014 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/m68k.h b/binutils-2.25/include/opcode/m68k.h index f7bd8b45..2d2d41b4 100644 --- a/binutils-2.25/include/opcode/m68k.h +++ b/binutils-2.25/include/opcode/m68k.h @@ -1,6 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, - 2003, 2004, 2006, 2010 Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/m88k.h b/binutils-2.25/include/opcode/m88k.h index 739c0e90..35c7416f 100644 --- a/binutils-2.25/include/opcode/m88k.h +++ b/binutils-2.25/include/opcode/m88k.h @@ -1,6 +1,5 @@ /* Table of opcodes for the Motorola M88k family. - Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010 - Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/binutils-2.25/include/opcode/metag.h b/binutils-2.25/include/opcode/metag.h index c9bb6680..6fc77186 100644 --- a/binutils-2.25/include/opcode/metag.h +++ b/binutils-2.25/include/opcode/metag.h @@ -1,5 +1,5 @@ /* Imagination Technologies Meta opcode table. - Copyright (C) 2013 Free Software Foundation, Inc. + Copyright (C) 2013-2014 Free Software Foundation, Inc. Contributed by Imagination Technologies Ltd. This file is part of GDB and GAS. diff --git a/binutils-2.25/include/opcode/mips.h b/binutils-2.25/include/opcode/mips.h index cb16d2a4..ef261674 100644 --- a/binutils-2.25/include/opcode/mips.h +++ b/binutils-2.25/include/opcode/mips.h @@ -1,7 +1,5 @@ /* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005, 2008, 2009, 2010, 2013 - Free Software Foundation, Inc. + Copyright (C) 1993-2014 Free Software Foundation, Inc. Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support @@ -419,7 +417,17 @@ enum mips_operand_type { OP_IMM_INDEX, /* An index selected by a register, e.g. [$2]. */ - OP_REG_INDEX + OP_REG_INDEX, + + /* The operand spans two 5-bit register fields, both of which must be set to + the source register. */ + OP_SAME_RS_RT, + + /* Described by mips_prev_operand. */ + OP_CHECK_PREV, + + /* A register operand that must not be zero. */ + OP_NON_ZERO_REG }; /* Enumerates the types of MIPS register. */ @@ -555,6 +563,18 @@ struct mips_reg_operand const unsigned char *reg_map; }; +/* Describes an operand that which must match a condition based on the + previous operand. */ +struct mips_check_prev_operand +{ + struct mips_operand root; + + bfd_boolean greater_than_ok; + bfd_boolean less_than_ok; + bfd_boolean equal_ok; + bfd_boolean zero_ok; +}; + /* Describes an operand that encodes a pair of registers. */ struct mips_reg_pair_operand { @@ -910,10 +930,10 @@ struct mips_opcode "+k" 5-bit GPR at bit 6 "+l" 5-bit MSA control register at bit 6 "+n" 5-bit MSA control register at bit 11 - "+o" 5-bit vector element index at bit 16 - "+u" 4-bit vector element index at bit 16 - "+v" 3-bit vector element index at bit 16 - "+w" 2-bit vector element index at bit 16 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 "+T" (-512 .. 511) << 0 at bit 16 "+U" (-512 .. 511) << 1 at bit 16 "+V" (-512 .. 511) << 2 at bit 16 @@ -929,6 +949,28 @@ struct mips_opcode "+*" 5-bit register vector element index at bit 16 "+|" 8-bit mask at bit 16 + MIPS R6: + "+:" 11-bit mask at bit 0 + "+'" 26 bit PC relative branch target address + "+"" 21 bit PC relative branch target address + "+;" 5 bit same register in both OP_*_RS and OP_*_RT + "+I" 2bit unsigned bit position at bit 6 + "+O" 3bit unsigned bit position at bit 6 + "+R" must be program counter + "-a" (-262144 .. 262143) << 2 at bit 0 + "-b" (-131072 .. 131071) << 3 at bit 0 + "-d" Same as destination register GP + "-s" 5 bit source register specifier (OP_*_RS) not $0 + "-t" 5 bit source register specifier (OP_*_RT) not $0 + "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS + "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS + "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS + "-x" 5 bit source register specifier (OP_*_RT) greater than or + equal to OP_*_RS + "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS + "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 + "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + Other: "()" parens surrounding optional value "," separates operands @@ -936,16 +978,21 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!#$*&\~" + "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "~!@#$%^&*|" - "ABCEFGHJKLMNPQSTUVWXZ" + "~!@#$%^&*|:'";" + "ABCEFGHIJKLMNOPQRSTUVWXZ" "abcdefghijklmnopqrstuvwxyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "AB" + "abdstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -973,18 +1020,18 @@ struct mips_opcode #define INSN_TLB 0x00000200 /* Reads coprocessor register other than floating point register. */ #define INSN_COP 0x00000400 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00000800 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00001000 +/* Instruction loads value from memory. */ +#define INSN_LOAD_MEMORY 0x00000800 +/* Instruction loads value from coprocessor, (may require delay). */ +#define INSN_LOAD_COPROC 0x00001000 /* Instruction has unconditional branch delay slot. */ #define INSN_UNCOND_BRANCH_DELAY 0x00002000 /* Instruction has conditional branch delay slot. */ #define INSN_COND_BRANCH_DELAY 0x00004000 /* Conditional branch likely: if branch not taken, insn nullified. */ #define INSN_COND_BRANCH_LIKELY 0x00008000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00010000 +/* Moves to coprocessor register, (may require delay). */ +#define INSN_COPROC_MOVE 0x00010000 /* Loads coprocessor register from memory, requiring delay. */ #define INSN_COPROC_MEMORY_DELAY 0x00020000 /* Reads the HI register. */ @@ -1053,6 +1100,8 @@ struct mips_opcode #define INSN2_READ_GPR_16 0x00002000 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 +/* Instruction has a forbidden slot. */ +#define INSN2_FORBIDDEN_SLOT 0x00008000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that @@ -1060,7 +1109,7 @@ struct mips_opcode word constructed using these macros is a bitmask of the remaining INSN_* values below. */ -#define INSN_ISA_MASK 0x0000000ful +#define INSN_ISA_MASK 0x0000001ful /* We cannot start at zero due to ISA_UNKNOWN below. */ #define INSN_ISA1 1 @@ -1070,28 +1119,75 @@ struct mips_opcode #define INSN_ISA5 5 #define INSN_ISA32 6 #define INSN_ISA32R2 7 -#define INSN_ISA64 8 -#define INSN_ISA64R2 9 +#define INSN_ISA32R3 8 +#define INSN_ISA32R5 9 +#define INSN_ISA32R6 10 +#define INSN_ISA64 11 +#define INSN_ISA64R2 12 +#define INSN_ISA64R3 13 +#define INSN_ISA64R5 14 +#define INSN_ISA64R6 15 /* Below this point the INSN_* values correspond to combinations of ISAs. They are only for use in the opcodes table to indicate membership of a combination of ISAs that cannot be expressed using the usual inclusion ordering on the above INSN_* values. */ -#define INSN_ISA3_32 10 -#define INSN_ISA3_32R2 11 -#define INSN_ISA4_32 12 -#define INSN_ISA4_32R2 13 -#define INSN_ISA5_32R2 14 - -/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through - INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, - this table describes whether at least one of the ISAs described by X - is/are implemented by ISA Y. (Think of Y as the ISA level supported by - a particular core and X as the ISA level(s) at which a certain instruction - is defined.) The ISA(s) described by X is/are implemented by Y iff - (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 - is non-zero. */ -static const unsigned int mips_isa_table[] = - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; +#define INSN_ISA3_32 16 +#define INSN_ISA3_32R2 17 +#define INSN_ISA4_32 18 +#define INSN_ISA4_32R2 19 +#define INSN_ISA5_32R2 20 + +/* The R6 definitions shown below state that they support all previous ISAs. + This is not actually true as some instructions are removed in R6. + The problem is that the removed instructions in R6 come from different + ISAs. One approach to solve this would be to describe in the membership + field of the opcode table the different ISAs an instruction belongs to. + This would require us to create a large amount of different ISA + combinations which is hard to manage. A cleaner approach (which is + implemented here) is to say that R6 is an extension of R5 and then to + deal with the removed instructions by adding instruction exclusions + for R6 in the opcode table. */ + +/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ + +#define ISAF(X) (1 << (INSN_ISA##X - 1)) +#define INSN_UPTO1 ISAF(1) +#define INSN_UPTO2 INSN_UPTO1 | ISAF(2) +#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) +#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) +#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) +#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) +#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ + | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) +#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) +#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) +#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) +#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) +#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) +#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) +#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) +#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) + +/* The same information in table form: bit INSN_ISA<X> - 1 of index + INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ +static const unsigned int mips_isa_table[] = { + INSN_UPTO1, + INSN_UPTO2, + INSN_UPTO3, + INSN_UPTO4, + INSN_UPTO5, + INSN_UPTO32, + INSN_UPTO32R2, + INSN_UPTO32R3, + INSN_UPTO32R5, + INSN_UPTO32R6, + INSN_UPTO64, + INSN_UPTO64R2, + INSN_UPTO64R3, + INSN_UPTO64R5, + INSN_UPTO64R6 +}; +#undef ISAF /* Masks used for Chip specific instructions. */ #define INSN_CHIP_MASK 0xc3ff0f20 @@ -1157,6 +1253,8 @@ static const unsigned int mips_isa_table[] = /* MSA Extension */ #define ASE_MSA 0x00000800 #define ASE_MSA64 0x00001000 +/* eXtended Physical Address (XPA) Extension. */ +#define ASE_XPA 0x00002000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1171,8 +1269,14 @@ static const unsigned int mips_isa_table[] = #define ISA_MIPS64 INSN_ISA64 #define ISA_MIPS32R2 INSN_ISA32R2 +#define ISA_MIPS32R3 INSN_ISA32R3 +#define ISA_MIPS32R5 INSN_ISA32R5 #define ISA_MIPS64R2 INSN_ISA64R2 +#define ISA_MIPS64R3 INSN_ISA64R3 +#define ISA_MIPS64R5 INSN_ISA64R5 +#define ISA_MIPS32R6 INSN_ISA32R6 +#define ISA_MIPS64R6 INSN_ISA64R6 /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -1203,9 +1307,15 @@ static const unsigned int mips_isa_table[] = #define CPU_MIPS16 16 #define CPU_MIPS32 32 #define CPU_MIPS32R2 33 +#define CPU_MIPS32R3 34 +#define CPU_MIPS32R5 36 +#define CPU_MIPS32R6 37 #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 +#define CPU_MIPS64R3 66 +#define CPU_MIPS64R5 68 +#define CPU_MIPS64R6 69 #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 @@ -1281,6 +1391,13 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_MIPS32R6: + return (mask & INSN_ISA_MASK) == INSN_ISA32R6; + + case CPU_MIPS64R6: + return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) + || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); + default: return FALSE; } @@ -2018,7 +2135,6 @@ extern const int bfd_mips16_num_opcodes; "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) - "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes @@ -2043,6 +2159,8 @@ extern const int bfd_mips16_num_opcodes; "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. + "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code + (MICROMIPSOP_*_CODE10) PC-relative addition (ADDIUPC) instruction: "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) @@ -2093,10 +2211,10 @@ extern const int bfd_mips16_num_opcodes; "+k" 5-bit GPR at bit 6 "+l" 5-bit MSA control register at bit 6 "+n" 5-bit MSA control register at bit 11 - "+o" 5-bit vector element index at bit 16 - "+u" 4-bit vector element index at bit 16 - "+v" 3-bit vector element index at bit 16 - "+w" 2-bit vector element index at bit 16 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 "+x" 5-bit shift amount at bit 16 "+T" (-512 .. 511) << 0 at bit 16 "+U" (-512 .. 511) << 1 at bit 16 @@ -2121,7 +2239,7 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "12345678 0" - "<>(),+.@\^|~" + "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" @@ -2129,7 +2247,7 @@ extern const int bfd_mips16_num_opcodes; following), for quick reference when adding more: "" "~!@#$%^&*|" - "ABCEFGHTUVW" + "ABCEFGHJTUVW" "dehijklnouvwx" Extension character sequences used so far ("m" followed by the @@ -2138,6 +2256,12 @@ extern const int bfd_mips16_num_opcodes; "" " BCDEFGHIJ LMNOPQ U WXYZ" " bcdefghij lmn pq st xyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "" + "" + <none so far> */ extern const struct mips_operand *decode_micromips_operand (const char *); diff --git a/binutils-2.25/include/opcode/mmix.h b/binutils-2.25/include/opcode/mmix.h index f931545d..f0d7a8ff 100644 --- a/binutils-2.25/include/opcode/mmix.h +++ b/binutils-2.25/include/opcode/mmix.h @@ -1,5 +1,5 @@ /* mmix.h -- Header file for MMIX opcode table - Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. Written by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/mn10200.h b/binutils-2.25/include/opcode/mn10200.h index b597d7b4..f327d10f 100644 --- a/binutils-2.25/include/opcode/mn10200.h +++ b/binutils-2.25/include/opcode/mn10200.h @@ -1,5 +1,5 @@ /* mn10200.h -- Header file for Matsushita 10200 opcode table - Copyright 1996, 1997, 2010 Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/mn10300.h b/binutils-2.25/include/opcode/mn10300.h index 16a139bc..eaa82e2e 100644 --- a/binutils-2.25/include/opcode/mn10300.h +++ b/binutils-2.25/include/opcode/mn10300.h @@ -1,5 +1,5 @@ /* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/moxie.h b/binutils-2.25/include/opcode/moxie.h index dae40c8e..6c5a0039 100644 --- a/binutils-2.25/include/opcode/moxie.h +++ b/binutils-2.25/include/opcode/moxie.h @@ -1,5 +1,5 @@ /* Definitions for decoding the moxie opcode table. - Copyright 2009 Free Software Foundation, Inc. + Copyright (C) 2009-2014 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com). This program is free software; you can redistribute it and/or modify diff --git a/binutils-2.25/include/opcode/msp430-decode.h b/binutils-2.25/include/opcode/msp430-decode.h index 0653aded..70fff07a 100644 --- a/binutils-2.25/include/opcode/msp430-decode.h +++ b/binutils-2.25/include/opcode/msp430-decode.h @@ -1,5 +1,5 @@ /* Opcode decoder for the TI MSP430 - Copyright 2012-2013 Free Software Foundation, Inc. + Copyright (C) 2012-2014 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger. diff --git a/binutils-2.25/include/opcode/msp430.h b/binutils-2.25/include/opcode/msp430.h index caddc42d..0e73815a 100644 --- a/binutils-2.25/include/opcode/msp430.h +++ b/binutils-2.25/include/opcode/msp430.h @@ -1,6 +1,6 @@ /* Opcode table for the TI MSP430 microcontrollers - Copyright 2002-2013 Free Software Foundation, Inc. + Copyright (C) 2002-2014 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This program is free software; you can redistribute it and/or modify @@ -26,7 +26,8 @@ struct msp430_operand_s int ol; /* Operand length words. */ int am; /* Addr mode. */ int reg; /* Register. */ - int mode; /* Pperand mode. */ + int mode; /* Operand mode. */ + int vshift; /* Number of bytes to shift operand down. */ #define OP_REG 0 #define OP_EXP 1 #ifndef DASM_SECTION diff --git a/binutils-2.25/include/opcode/nds32.h b/binutils-2.25/include/opcode/nds32.h new file mode 100644 index 00000000..9592be66 --- /dev/null +++ b/binutils-2.25/include/opcode/nds32.h @@ -0,0 +1,831 @@ +/* nds32.h -- Header file for nds32 opcode table + Copyright (C) 2012-2014 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef OPCODE_NDS32_H +#define OPCODE_NDS32_H + +/* Registers. */ +#define REG_R5 5 +#define REG_R8 8 +#define REG_R10 10 +#define REG_R12 12 +#define REG_R15 15 +#define REG_R16 16 +#define REG_R20 20 +#define REG_TA 15 +#define REG_TP 27 +#define REG_FP 28 +#define REG_GP 29 +#define REG_LP 30 +#define REG_SP 31 + +/* Macros for extracting fields or making an instruction. */ +static const int nds32_r45map[] = +{ + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 16, 17, 18, 19 +}; + +static const int nds32_r54map[] = +{ + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, -1, -1, -1, -1, + 12, 13, 14, 15, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1 +}; + +#define __BIT(n) (1 << (n)) +#define __MASK(n) (__BIT (n) - 1) +#define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) +#define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) +#define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1))) + +/* Make nds32 instructions. */ + +#define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ + (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ + | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ + | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) +#define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ + (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ + | __MF (sub10, 0, 10)) +#define N32_TYPE2(op6, rt5, ra5, imm15) \ + (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) +#define N32_TYPE1(op6, rt5, imm20) \ + (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) +#define N32_TYPE0(op6, imm25) \ + (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) +#define N32_ALU1(sub, rt, ra, rb) \ + N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) +#define N32_ALU1_SH(sub, rt, ra, rb, rd) \ + N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) +#define N32_ALU2(sub, rt, ra, rb) \ + N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) +#define N32_BR1(sub, rt, ra, imm14s) \ + N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) +#define N32_BR2(sub, rt, imm16s) \ + N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) +#define N32_BR3(sub, rt, imm11s, imm8s) \ + N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ + | ((imm11s & __MASK (11)) << 8) \ + | (imm8s & __MASK (8))) +#define N32_JI(sub, imm24s) \ + N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) +#define N32_JREG(sub, rt, rb, dtit, hint) \ + N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) +#define N32_MEM(sub, rt, ra, rb, sv) \ + N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) + +#define N16_TYPE55(op5, rt5, ra5) \ + (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ + | __MF (ra5, 0, 5)) +#define N16_TYPE45(op6, rt4, ra5) \ + (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ + | __MF (ra5, 0, 5)) +#define N16_TYPE333(op6, rt3, ra3, rb3) \ + (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ + | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) +#define N16_TYPE36(op6, rt3, imm6) \ + (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ + | __MF (imm6, 0, 6)) +#define N16_TYPE38(op4, rt3, imm8) \ + (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ + | __MF (imm8, 0, 8)) +#define N16_TYPE37(op4, rt3, ls, imm7) \ + (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ + | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) +#define N16_TYPE5(op10, imm5) \ + (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) +#define N16_TYPE8(op7, imm8) \ + (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) +#define N16_TYPE9(op6, imm9) \ + (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) +#define N16_TYPE10(op5, imm10) \ + (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) +#define N16_TYPE25(op8, re, imm5) \ + (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ + | __MF (imm5, 0, 5)) + +#define N16_MISC33(sub, rt, ra) \ + N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) +#define N16_BFMI333(sub, rt, ra) \ + N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) + +/* Get instruction fields. + + Macros used for handling 32-bit and 16-bit instructions are + prefixed with N32_ and N16_ respectively. */ + +#define N32_OP6(insn) (((insn) >> 25) & 0x3f) +#define N32_RT5(insn) (((insn) >> 20) & 0x1f) +#define N32_RT53(insn) (N32_RT5 (insn) & 0x7) +#define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] +#define N32_RA5(insn) (((insn) >> 15) & 0x1f) +#define N32_RA53(insn) (N32_RA5 (insn) & 0x7) +#define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] +#define N32_RB5(insn) (((insn) >> 10) & 0x1f) +#define N32_UB5(insn) (((insn) >> 10) & 0x1f) +#define N32_RB53(insn) (N32_RB5 (insn) & 0x7) +#define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] +#define N32_RD5(insn) (((insn) >> 5) & 0x1f) +#define N32_SH5(insn) (((insn) >> 5) & 0x1f) +#define N32_SUB5(insn) (((insn) >> 0) & 0x1f) +#define N32_SWID(insn) (((insn) >> 5) & 0x3ff) +#define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) +#define N32_IMMS(insn, bs) ((signed) __SEXT (((insn) & __MASK (bs)), bs)) +#define N32_IMM5U(insn) N32_IMMU (insn, 5) +#define N32_IMM12S(insn) N32_IMMS (insn, 12) +#define N32_IMM14S(insn) N32_IMMS (insn, 14) +#define N32_IMM15U(insn) N32_IMMU (insn, 15) +#define N32_IMM15S(insn) N32_IMMS (insn, 15) +#define N32_IMM16S(insn) N32_IMMS (insn, 16) +#define N32_IMM17S(insn) N32_IMMS (insn, 17) +#define N32_IMM20S(insn) N32_IMMS (insn, 20) +#define N32_IMM20U(insn) N32_IMMU (insn, 20) +#define N32_IMM24S(insn) N32_IMMS (insn, 24) + +#define N16_RT5(insn) (((insn) >> 5) & 0x1f) +#define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] +#define N16_RT3(insn) (((insn) >> 6) & 0x7) +#define N16_RT38(insn) (((insn) >> 8) & 0x7) +#define N16_RT8(insn) (((insn) >> 8) & 0x7) +#define N16_RA5(insn) ((insn) & 0x1f) +#define N16_RA3(insn) (((insn) >> 3) & 0x7) +#define N16_RB3(insn) ((insn) & 0x7) +#define N16_IMM3U(insn) N32_IMMU (insn, 3) +#define N16_IMM5U(insn) N32_IMMU (insn, 5) +#define N16_IMM5S(insn) N32_IMMS (insn, 5) +#define N16_IMM6U(insn) N32_IMMU (insn, 6) +#define N16_IMM7U(insn) N32_IMMU (insn, 7) +#define N16_IMM8S(insn) N32_IMMS (insn, 8) +#define N16_IMM9U(insn) N32_IMMU (insn, 9) +#define N16_IMM10S(insn) N32_IMMS (insn, 10) + +#define IS_WITHIN_U(v, n) (((v) >> n) == 0) +#define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) + +/* Get fields for specific instruction. */ +#define N32_JREG_T(insn) (((insn) >> 8) & 0x3) +#define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) +#define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) +#define N32_COP_SUB(insn) ((insn) & 0xf) +#define N32_COP_CP(insn) (((insn) >> 4) & 0x3) + +/* Check fields. */ +#define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) +#define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) +#define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) +#define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) +#define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) +#define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) + + +/* These are opcodes for Nxx_TYPE macros. + They are prefixed by corresponding TYPE to avoid misusing. */ + +enum n32_opcodes +{ + /* Main opcodes (OP6). */ + + N32_OP6_LBI = 0x0, + N32_OP6_LHI, + N32_OP6_LWI, + N32_OP6_LDI, + N32_OP6_LBI_BI, + N32_OP6_LHI_BI, + N32_OP6_LWI_BI, + N32_OP6_LDI_BI, + + N32_OP6_SBI = 0x8, + N32_OP6_SHI, + N32_OP6_SWI, + N32_OP6_SDI, + N32_OP6_SBI_BI, + N32_OP6_SHI_BI, + N32_OP6_SWI_BI, + N32_OP6_SDI_BI, + + N32_OP6_LBSI = 0x10, + N32_OP6_LHSI, + N32_OP6_LWSI, + N32_OP6_DPREFI, + N32_OP6_LBSI_BI, + N32_OP6_LHSI_BI, + N32_OP6_LWSI_BI, + N32_OP6_LBGP, + + N32_OP6_LWC = 0x18, + N32_OP6_SWC, + N32_OP6_LDC, + N32_OP6_SDC, + N32_OP6_MEM, + N32_OP6_LSMW, + N32_OP6_HWGP, + N32_OP6_SBGP, + + N32_OP6_ALU1 = 0x20, + N32_OP6_ALU2, + N32_OP6_MOVI, + N32_OP6_SETHI, + N32_OP6_JI, + N32_OP6_JREG, + N32_OP6_BR1, + N32_OP6_BR2, + + N32_OP6_ADDI = 0x28, + N32_OP6_SUBRI, + N32_OP6_ANDI, + N32_OP6_XORI, + N32_OP6_ORI, + N32_OP6_BR3, + N32_OP6_SLTI, + N32_OP6_SLTSI, + + N32_OP6_AEXT = 0x30, + N32_OP6_CEXT, + N32_OP6_MISC, + N32_OP6_BITCI, + N32_OP6_0x34, + N32_OP6_COP, + N32_OP6_0x36, + N32_OP6_0x37, + + N32_OP6_SIMD = 0x38, + + /* Sub-opcodes of specific opcode. */ + + /* bit-24 */ + N32_BR1_BEQ = 0, + N32_BR1_BNE = 1, + + /* bit[16:19] */ + N32_BR2_IFCALL = 0, + N32_BR2_BEQZ = 2, + N32_BR2_BNEZ = 3, + N32_BR2_BGEZ = 4, + N32_BR2_BLTZ = 5, + N32_BR2_BGTZ = 6, + N32_BR2_BLEZ = 7, + N32_BR2_BGEZAL = 0xc, + N32_BR2_BLTZAL = 0xd, + + /* bit-19 */ + N32_BR3_BEQC = 0, + N32_BR3_BNEC = 1, + + /* bit-24 */ + N32_JI_J = 0, + N32_JI_JAL = 1, + + /* bit[0:4] */ + N32_JREG_JR = 0, + N32_JREG_JRAL = 1, + N32_JREG_JRNEZ = 2, + N32_JREG_JRALNEZ = 3, + + /* bit[0:4] */ + N32_ALU1_ADD_SLLI = 0x0, + N32_ALU1_SUB_SLLI, + N32_ALU1_AND_SLLI, + N32_ALU1_XOR_SLLI, + N32_ALU1_OR_SLLI, + N32_ALU1_ADD = 0x0, + N32_ALU1_SUB, + N32_ALU1_AND, + N32_ALU1_XOR, + N32_ALU1_OR, + N32_ALU1_NOR, + N32_ALU1_SLT, + N32_ALU1_SLTS, + N32_ALU1_SLLI = 0x8, + N32_ALU1_SRLI, + N32_ALU1_SRAI, + N32_ALU1_ROTRI, + N32_ALU1_SLL, + N32_ALU1_SRL, + N32_ALU1_SRA, + N32_ALU1_ROTR, + N32_ALU1_SEB = 0x10, + N32_ALU1_SEH, + N32_ALU1_BITC, + N32_ALU1_ZEH, + N32_ALU1_WSBH, + N32_ALU1_OR_SRLI, + N32_ALU1_DIVSR, + N32_ALU1_DIVR, + N32_ALU1_SVA = 0x18, + N32_ALU1_SVS, + N32_ALU1_CMOVZ, + N32_ALU1_CMOVN, + N32_ALU1_ADD_SRLI, + N32_ALU1_SUB_SRLI, + N32_ALU1_AND_SRLI, + N32_ALU1_XOR_SRLI, + + /* bit[0:5], where bit[6:9] == 0 */ + N32_ALU2_MAX = 0, + N32_ALU2_MIN, + N32_ALU2_AVE, + N32_ALU2_ABS, + N32_ALU2_CLIPS, + N32_ALU2_CLIP, + N32_ALU2_CLO, + N32_ALU2_CLZ, + N32_ALU2_BSET = 0x8, + N32_ALU2_BCLR, + N32_ALU2_BTGL, + N32_ALU2_BTST, + N32_ALU2_BSE, + N32_ALU2_BSP, + N32_ALU2_FFB, + N32_ALU2_FFMISM, + N32_ALU2_ADD_SC = 0x10, + N32_ALU2_SUB_SC, + N32_ALU2_ADD_WC, + N32_ALU2_SUB_WC, + N32_ALU2_KMxy, + N32_ALU2_0x15, + N32_ALU2_0x16, + N32_ALU2_FFZMISM, + N32_ALU2_KADD = 0x18, + N32_ALU2_KSUB, + N32_ALU2_KSLRA, + N32_ALU2_MFUSR = 0x20, + N32_ALU2_MTUSR, + N32_ALU2_0x22, + N32_ALU2_0x23, + N32_ALU2_MUL, + N32_ALU2_0x25, + N32_ALU2_0x26, + N32_ALU2_MULTS64 = 0x28, + N32_ALU2_MULT64, + N32_ALU2_MADDS64, + N32_ALU2_MADD64, + N32_ALU2_MSUBS64, + N32_ALU2_MSUB64, + N32_ALU2_DIVS, + N32_ALU2_DIV, + N32_ALU2_0x30 = 0x30, + N32_ALU2_MULT32, + N32_ALU2_0x32, + N32_ALU2_MADD32, + N32_ALU2_0x34, + N32_ALU2_MSUB32, + + /* bit[0:5], where bit[6:9] != 0 */ + N32_ALU2_FFBI = 0xe, + N32_ALU2_FLMISM = 0xf, + N32_ALU2_MULSR64 = 0x28, + N32_ALU2_MULR64 = 0x29, + N32_ALU2_MADDR32 = 0x33, + N32_ALU2_MSUBR32 = 0x35, + + /* bit[0:5] */ + N32_MEM_LB = 0, + N32_MEM_LH, + N32_MEM_LW, + N32_MEM_LD, + N32_MEM_LB_BI, + N32_MEM_LH_BI, + N32_MEM_LW_BI, + N32_MEM_LD_BI, + N32_MEM_SB, + N32_MEM_SH, + N32_MEM_SW, + N32_MEM_SD, + N32_MEM_SB_BI, + N32_MEM_SH_BI, + N32_MEM_SW_BI, + N32_MEM_SD_BI, + N32_MEM_LBS, + N32_MEM_LHS, + N32_MEM_LWS, /* Not used. */ + N32_MEM_DPREF, + N32_MEM_LBS_BI, + N32_MEM_LHS_BI, + N32_MEM_LWS_BI, /* Not used. */ + N32_MEM_0x17, /* Not used. */ + N32_MEM_LLW, + N32_MEM_SCW, + N32_MEM_LBUP = 0x20, + N32_MEM_LWUP = 0x22, + N32_MEM_SBUP = 0x28, + N32_MEM_SWUP = 0x2a, + + /* bit[0:1] */ + N32_LSMW_LSMW = 0, + N32_LSMW_LSMWA, + N32_LSMW_LSMWZB, + + /* bit[2:4] */ + N32_LSMW_BI = 0, + N32_LSMW_BIM, + N32_LSMW_BD, + N32_LSMW_BDM, + N32_LSMW_AI, + N32_LSMW_AIM, + N32_LSMW_AD, + N32_LSMW_ADM, + + /* bit[0:4] */ + N32_MISC_STANDBY = 0, + N32_MISC_CCTL, + N32_MISC_MFSR, + N32_MISC_MTSR, + N32_MISC_IRET, + N32_MISC_TRAP, + N32_MISC_TEQZ, + N32_MISC_TNEZ, + N32_MISC_DSB = 0x8, + N32_MISC_ISB, + N32_MISC_BREAK, + N32_MISC_SYSCALL, + N32_MISC_MSYNC, + N32_MISC_ISYNC, + N32_MISC_TLBOP, + N32_MISC_0xf, + + /* bit[0:4] */ + N32_SIMD_PBSAD = 0, + N32_SIMD_PBSADA = 1, + + /* bit[0:3] */ + N32_COP_CPE1 = 0, + N32_COP_MFCP, + N32_COP_CPLW, + N32_COP_CPLD, + N32_COP_CPE2, + N32_COP_CPE3 = 8, + N32_COP_MTCP, + N32_COP_CPSW, + N32_COP_CPSD, + N32_COP_CPE4, + + /* cop/0 b[3:0] */ + N32_FPU_FS1 = 0, + N32_FPU_MFCP, + N32_FPU_FLS, + N32_FPU_FLD, + N32_FPU_FS2, + N32_FPU_FD1 = 8, + N32_FPU_MTCP, + N32_FPU_FSS, + N32_FPU_FSD, + N32_FPU_FD2, + + /* FS1 b[9:6] */ + N32_FPU_FS1_FADDS = 0, + N32_FPU_FS1_FSUBS, + N32_FPU_FS1_FCPYNSS, + N32_FPU_FS1_FCPYSS, + N32_FPU_FS1_FMADDS, + N32_FPU_FS1_FMSUBS, + N32_FPU_FS1_FCMOVNS, + N32_FPU_FS1_FCMOVZS, + N32_FPU_FS1_FNMADDS, + N32_FPU_FS1_FNMSUBS, + N32_FPU_FS1_10, + N32_FPU_FS1_11, + N32_FPU_FS1_FMULS = 12, + N32_FPU_FS1_FDIVS, + N32_FPU_FS1_14, + N32_FPU_FS1_F2OP = 15, + + /* FS1/F2OP b[14:10] */ + N32_FPU_FS1_F2OP_FS2D = 0x00, + N32_FPU_FS1_F2OP_FSQRTS = 0x01, + N32_FPU_FS1_F2OP_FABSS = 0x05, + N32_FPU_FS1_F2OP_FUI2S = 0x08, + N32_FPU_FS1_F2OP_FSI2S = 0x0c, + N32_FPU_FS1_F2OP_FS2UI = 0x10, + N32_FPU_FS1_F2OP_FS2UI_Z = 0x14, + N32_FPU_FS1_F2OP_FS2SI = 0x18, + N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c, + + /* FS2 b[9:6] */ + N32_FPU_FS2_FCMPEQS = 0x0, + N32_FPU_FS2_FCMPLTS = 0x2, + N32_FPU_FS2_FCMPLES = 0x4, + N32_FPU_FS2_FCMPUNS = 0x6, + N32_FPU_FS2_FCMPEQS_E = 0x1, + N32_FPU_FS2_FCMPLTS_E = 0x3, + N32_FPU_FS2_FCMPLES_E = 0x5, + N32_FPU_FS2_FCMPUNS_E = 0x7, + + /* FD1 b[9:6] */ + N32_FPU_FD1_FADDD = 0, + N32_FPU_FD1_FSUBD, + N32_FPU_FD1_FCPYNSD, + N32_FPU_FD1_FCPYSD, + N32_FPU_FD1_FMADDD, + N32_FPU_FD1_FMSUBD, + N32_FPU_FD1_FCMOVND, + N32_FPU_FD1_FCMOVZD, + N32_FPU_FD1_FNMADDD, + N32_FPU_FD1_FNMSUBD, + N32_FPU_FD1_10, + N32_FPU_FD1_11, + N32_FPU_FD1_FMULD = 12, + N32_FPU_FD1_FDIVD, + N32_FPU_FD1_14, + N32_FPU_FD1_F2OP = 15, + + /* FD1/F2OP b[14:10] */ + N32_FPU_FD1_F2OP_FD2S = 0x00, + N32_FPU_FD1_F2OP_FSQRTD = 0x01, + N32_FPU_FD1_F2OP_FABSD = 0x05, + N32_FPU_FD1_F2OP_FUI2D = 0x08, + N32_FPU_FD1_F2OP_FSI2D = 0x0c, + N32_FPU_FD1_F2OP_FD2UI = 0x10, + N32_FPU_FD1_F2OP_FD2UI_Z = 0x14, + N32_FPU_FD1_F2OP_FD2SI = 0x18, + N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c, + + /* FD2 b[9:6] */ + N32_FPU_FD2_FCMPEQD = 0x0, + N32_FPU_FD2_FCMPLTD = 0x2, + N32_FPU_FD2_FCMPLED = 0x4, + N32_FPU_FD2_FCMPUND = 0x6, + N32_FPU_FD2_FCMPEQD_E = 0x1, + N32_FPU_FD2_FCMPLTD_E = 0x3, + N32_FPU_FD2_FCMPLED_E = 0x5, + N32_FPU_FD2_FCMPUND_E = 0x7, + + /* MFCP b[9:6] */ + N32_FPU_MFCP_FMFSR = 0x0, + N32_FPU_MFCP_FMFDR = 0x1, + N32_FPU_MFCP_XR = 0xc, + + /* MFCP/XR b[14:10] */ + N32_FPU_MFCP_XR_FMFCFG = 0x0, + N32_FPU_MFCP_XR_FMFCSR = 0x1, + + /* MTCP b[9:6] */ + N32_FPU_MTCP_FMTSR = 0x0, + N32_FPU_MTCP_FMTDR = 0x1, + N32_FPU_MTCP_XR = 0xc, + + /* MTCP/XR b[14:10] */ + N32_FPU_MTCP_XR_FMTCSR = 0x1 +}; + +enum n16_opcodes +{ + N16_T55_MOV55 = 0x0, + N16_T55_MOVI55 = 0x1, + + N16_T45_0 = 0, + N16_T45_ADD45 = 0x4, + N16_T45_SUB45 = 0x5, + N16_T45_ADDI45 = 0x6, + N16_T45_SUBI45 = 0x7, + N16_T45_SRAI45 = 0x8, + N16_T45_SRLI45 = 0x9, + N16_T45_LWI45_FE = 0x19, + N16_T45_LWI450 = 0x1a, + N16_T45_SWI450 = 0x1b, + N16_T45_SLTS45 = 0x30, + N16_T45_SLT45 = 0x31, + N16_T45_SLTSI45 = 0x32, + N16_T45_SLTI45 = 0x33, + N16_T45_MOVPI45 = 0x3d, + + N15_T44_MOVD44 = 0x7d, + + N16_T333_0 = 0, + N16_T333_SLLI333 = 0xa, + N16_T333_BFMI333 = 0xb, + N16_T333_ADD333 = 0xc, + N16_T333_SUB333 = 0xd, + N16_T333_ADDI333 = 0xe, + N16_T333_SUBI333 = 0xf, + N16_T333_LWI333 = 0x10, + N16_T333_LWI333_BI = 0x11, + N16_T333_LHI333 = 0x12, + N16_T333_LBI333 = 0x13, + N16_T333_SWI333 = 0x14, + N16_T333_SWI333_BI = 0x15, + N16_T333_SHI333 = 0x16, + N16_T333_SBI333 = 0x17, + N16_T333_MISC33 = 0x3f, + + N16_T36_ADDRI36_SP = 0x18, + + N16_T37_XWI37 = 0x7, + N16_T37_XWI37SP = 0xe, + + N16_T38_BEQZ38 = 0x8, + N16_T38_BNEZ38 = 0x9, + N16_T38_BEQS38 = 0xa, + N16_T38_BNES38 = 0xb, + + N16_T5_JR5 = 0x2e8, + N16_T5_JRAL5 = 0x2e9, + N16_T5_EX9IT = 0x2ea, + /* 0x2eb reserved. */ + N16_T5_RET5 = 0x2ec, + N16_T5_ADD5PC = 0x2ed, + /* 0x2e[ef] reserved. */ + N16_T5_BREAK16 = 0x350, + + N16_T8_J8 = 0x55, + N16_T8_BEQZS8 = 0x68, + N16_T8_BNEZS8 = 0x69, + + /* N16_T9_BREAK16 = 0x35 + Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */ + N16_T9_EX9IT = 0x35, + N16_T9_IFCALL9 = 0x3c, + + N16_T10_ADDI10S = 0x1b, + + N16_T25_PUSH25 = 0xf8, + N16_T25_POP25 = 0xf9, + + /* Sub-opcodes. */ + N16_MISC33_0 = 0, + N16_MISC33_1 = 1, + N16_MISC33_NEG33 = 2, + N16_MISC33_NOT33 = 3, + N16_MISC33_MUL33 = 4, + N16_MISC33_XOR33 = 5, + N16_MISC33_AND33 = 6, + N16_MISC33_OR33 = 7, + + N16_BFMI333_ZEB33 = 0, + N16_BFMI333_ZEH33 = 1, + N16_BFMI333_SEB33 = 2, + N16_BFMI333_SEH33 = 3, + N16_BFMI333_XLSB33 = 4, + N16_BFMI333_X11B33 = 5, + N16_BFMI333_BMSKI33 = 6, + N16_BFMI333_FEXTI33 = 7 +}; + +/* These macros a deprecated. DO NOT use them anymore. + And please help rewrite code used them. */ + +/* 32-bit instructions without operands. */ +#define INSN_SETHI 0x46000000 +#define INSN_ORI 0x58000000 +#define INSN_JR 0x4a000000 +#define INSN_RET 0x4a000020 +#define INSN_JAL 0x49000000 +#define INSN_J 0x48000000 +#define INSN_JRAL 0x4a000001 +#define INSN_BGEZAL 0x4e0c0000 +#define INSN_BLTZAL 0x4e0d0000 +#define INSN_BEQ 0x4c000000 +#define INSN_BNE 0x4c004000 +#define INSN_BEQZ 0x4e020000 +#define INSN_BNEZ 0x4e030000 +#define INSN_BGEZ 0x4e040000 +#define INSN_BLTZ 0x4e050000 +#define INSN_BGTZ 0x4e060000 +#define INSN_BLEZ 0x4e070000 +#define INSN_MOVI 0x44000000 +#define INSN_ADDI 0x50000000 +#define INSN_ANDI 0x54000000 +#define INSN_LDI 0x06000000 +#define INSN_SDI 0x16000000 +#define INSN_LWI 0x04000000 +#define INSN_LWSI 0x24000000 +#define INSN_LWIP 0x0c000000 +#define INSN_LHI 0x02000000 +#define INSN_LHSI 0x22000000 +#define INSN_LBI 0x00000000 +#define INSN_LBSI 0x20000000 +#define INSN_SWI 0x14000000 +#define INSN_SWIP 0x1c000000 +#define INSN_SHI 0x12000000 +#define INSN_SBI 0x10000000 +#define INSN_SLTI 0x5c000000 +#define INSN_SLTSI 0x5e000000 +#define INSN_ADD 0x40000000 +#define INSN_SUB 0x40000001 +#define INSN_SLT 0x40000006 +#define INSN_SLTS 0x40000007 +#define INSN_SLLI 0x40000008 +#define INSN_SRLI 0x40000009 +#define INSN_SRAI 0x4000000a +#define INSN_SEB 0x40000010 +#define INSN_SEH 0x40000011 +#define INSN_ZEB INSN_ANDI + 0xFF +#define INSN_ZEH 0x40000013 +#define INSN_BREAK 0x6400000a +#define INSN_NOP 0x40000009 +#define INSN_FLSI 0x30000000 +#define INSN_FSSI 0x32000000 +#define INSN_FLDI 0x34000000 +#define INSN_FSDI 0x36000000 +#define INSN_BEQC 0x5a000000 +#define INSN_BNEC 0x5a080000 +#define INSN_DSB 0x64000008 +#define INSN_IFCALL 0x4e000000 +#define INSN_IFRET 0x4a000060 +#define INSN_BR1 0x4c000000 +#define INSN_BR2 0x4e000000 + +/* 16-bit instructions without operand. */ +#define INSN_MOV55 0x8000 +#define INSN_MOVI55 0x8400 +#define INSN_ADD45 0x8800 +#define INSN_SUB45 0x8a00 +#define INSN_ADDI45 0x8c00 +#define INSN_SUBI45 0x8e00 +#define INSN_SRAI45 0x9000 +#define INSN_SRLI45 0x9200 +#define INSN_SLLI333 0x9400 +#define INSN_BFMI333 0x9600 +#define INSN_ADD333 0x9800 +#define INSN_SUB333 0x9a00 +#define INSN_ADDI333 0x9c00 +#define INSN_SUBI333 0x9e00 +#define INSN_LWI333 0xa000 +#define INSN_LWI333P 0xa200 +#define INSN_LHI333 0xa400 +#define INSN_LBI333 0xa600 +#define INSN_SWI333 0xa800 +#define INSN_SWI333P 0xaa00 +#define INSN_SHI333 0xac00 +#define INSN_SBI333 0xae00 +#define INSN_RSV01 0xb000 +#define INSN_RSV02 0xb200 +#define INSN_LWI450 0xb400 +#define INSN_SWI450 0xb600 +#define INSN_LWI37 0xb800 +#define INSN_SWI37 0xb880 +#define INSN_BEQZ38 0xc000 +#define INSN_BNEZ38 0xc800 +#define INSN_BEQS38 0xd000 +#define INSN_J8 0xd500 +#define INSN_BNES38 0xd800 +#define INSN_JR5 0xdd00 +#define INSN_RET5 0xdd80 +#define INSN_JRAL5 0xdd20 +#define INSN_EX9_IT_2 0xdd40 +#define INSN_SLTS45 0xe000 +#define INSN_SLT45 0xe200 +#define INSN_SLTSI45 0xe400 +#define INSN_SLTI45 0xe600 +#define INSN_BEQZS8 0xe800 +#define INSN_BNEZS8 0xe900 +#define INSN_BREAK16 0xea00 +#define INSN_EX9_IT_1 0xea00 +#define INSN_NOP16 0x9200 +/* 16-bit version 2. */ +#define INSN_ADDI10_SP 0xec00 +#define INSN_LWI37SP 0xf000 +#define INSN_SWI37SP 0xf080 +/* 16-bit version 3. */ +#define INSN_IFRET16 0x83ff +#define INSN_ADDRI36_SP 0xb000 +#define INSN_LWI45_FE 0xb200 +#define INSN_IFCALL9 0xf800 +#define INSN_MISC33 0xfe00 + +/* Instruction with specific operands. */ +#define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */ +#define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */ +#define INSN_MOVI_TO_FP 0x45c00000 +#define INSN_MFUSR_PC 0x420F8020 +#define INSN_MFUSR_PC_MASK 0xFE0FFFFF + +/* Instructions use $ta register as operand. */ +#define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20)) +#define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15)) +#define INSN_ADD_TA (INSN_ADD | (REG_TA << 20)) +#define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5)) +#define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0)) +#define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0)) +#define INSN_JR_TA (INSN_JR | (REG_TA << 10)) +#define INSN_RET_TA (INSN_RET | (REG_TA << 10)) +#define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10)) +#define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0)) +#define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20)) +#define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20)) +#define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20)) +#define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15)) +#define INSN_BNE_TA (INSN_BNE | (REG_TA << 15)) + +/* Instructions use $r5 register as operand. */ +#define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15)) +#define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15)) + +#endif diff --git a/binutils-2.25/include/opcode/nios2.h b/binutils-2.25/include/opcode/nios2.h index aa670981..04beff93 100644 --- a/binutils-2.25/include/opcode/nios2.h +++ b/binutils-2.25/include/opcode/nios2.h @@ -1,5 +1,5 @@ /* Nios II opcode list for GAS, the GNU assembler. - Copyright (C) 2012, 2013 Free Software Foundation, Inc. + Copyright (C) 2012-2014 Free Software Foundation, Inc. Contributed by Nigel Gray (ngray@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/binutils-2.25/include/opcode/np1.h b/binutils-2.25/include/opcode/np1.h index 6dadafde..f054d02d 100644 --- a/binutils-2.25/include/opcode/np1.h +++ b/binutils-2.25/include/opcode/np1.h @@ -1,5 +1,5 @@ /* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. + Copyright (C) 1986-2014 Free Software Foundation, Inc. This file is part of GDB. diff --git a/binutils-2.25/include/opcode/ns32k.h b/binutils-2.25/include/opcode/ns32k.h index 34c42f87..4f0fc01d 100644 --- a/binutils-2.25/include/opcode/ns32k.h +++ b/binutils-2.25/include/opcode/ns32k.h @@ -1,5 +1,5 @@ /* ns32k-opcode.h -- Opcode table for National Semi 32k processor - Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc. + Copyright (C) 1987-2014 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. diff --git a/binutils-2.25/include/opcode/or32.h b/binutils-2.25/include/opcode/or32.h deleted file mode 100644 index 153d91ec..00000000 --- a/binutils-2.25/include/opcode/or32.h +++ /dev/null @@ -1,181 +0,0 @@ -/* Table of opcodes for the OpenRISC 1000 ISA. - Copyright 2002, 2003, 2010 Free Software Foundation, Inc. - Contributed by Damjan Lampret (lampret@opencores.org). - - This file is part of or1k_gen_isa, or1ksim, GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* We treat all letters the same in encode/decode routines so - we need to assign some characteristics to them like signess etc. */ - -#ifndef OR32_H_ISA -#define OR32_H_ISA - -#define NUM_UNSIGNED (0) -#define NUM_SIGNED (1) - -#define MAX_GPRS 32 -#define PAGE_SIZE 4096 -#undef __HALF_WORD_INSN__ - -#define OPERAND_DELIM (',') - -#define OR32_IF_DELAY (1) -#define OR32_W_FLAG (2) -#define OR32_R_FLAG (4) - -struct or32_letter -{ - char letter; - int sign; - /* int reloc; relocation per letter ?? */ -}; - -/* Main instruction specification array. */ -struct or32_opcode -{ - /* Name of the instruction. */ - char *name; - - /* A string of characters which describe the operands. - Valid characters are: - ,() Itself. Characters appears in the assembly code. - rA Register operand. - rB Register operand. - rD Register operand. - I An immediate operand, range -32768 to 32767. - J An immediate operand, range . (unused) - K An immediate operand, range 0 to 65535. - L An immediate operand, range 0 to 63. - M An immediate operand, range . (unused) - N An immediate operand, range -33554432 to 33554431. - O An immediate operand, range . (unused). */ - char *args; - - /* Opcode and operand encoding. */ - char *encoding; - void (*exec) (void); - unsigned int flags; -}; - -#define OPTYPE_LAST (0x80000000) -#define OPTYPE_OP (0x40000000) -#define OPTYPE_REG (0x20000000) -#define OPTYPE_SIG (0x10000000) -#define OPTYPE_DIS (0x08000000) -#define OPTYPE_DST (0x04000000) -#define OPTYPE_SBIT (0x00001F00) -#define OPTYPE_SHR (0x0000001F) -#define OPTYPE_SBIT_SHR (8) - -/* MM: Data how to decode operands. */ -extern struct insn_op_struct -{ - unsigned long type; - unsigned long data; -} **op_start; - -#ifdef HAS_EXECUTION -extern void l_invalid (void); -extern void l_sfne (void); -extern void l_bf (void); -extern void l_add (void); -extern void l_sw (void); -extern void l_sb (void); -extern void l_sh (void); -extern void l_lwz (void); -extern void l_lbs (void); -extern void l_lbz (void); -extern void l_lhs (void); -extern void l_lhz (void); -extern void l_movhi (void); -extern void l_and (void); -extern void l_or (void); -extern void l_xor (void); -extern void l_sub (void); -extern void l_mul (void); -extern void l_div (void); -extern void l_divu (void); -extern void l_sll (void); -extern void l_sra (void); -extern void l_srl (void); -extern void l_j (void); -extern void l_jal (void); -extern void l_jalr (void); -extern void l_jr (void); -extern void l_rfe (void); -extern void l_nop (void); -extern void l_bnf (void); -extern void l_sfeq (void); -extern void l_sfgts (void); -extern void l_sfges (void); -extern void l_sflts (void); -extern void l_sfles (void); -extern void l_sfgtu (void); -extern void l_sfgeu (void); -extern void l_sfltu (void); -extern void l_sfleu (void); -extern void l_mtspr (void); -extern void l_mfspr (void); -extern void l_sys (void); -extern void l_trap (void); /* CZ 21/06/01. */ -extern void l_macrc (void); -extern void l_mac (void); -extern void l_msb (void); -extern void l_invalid (void); -extern void l_cust1 (void); -extern void l_cust2 (void); -extern void l_cust3 (void); -extern void l_cust4 (void); -#endif -extern void l_none (void); - -extern const struct or32_letter or32_letters[]; - -extern const struct or32_opcode or32_opcodes[]; - -extern const unsigned int or32_num_opcodes; - -/* Calculates instruction length in bytes. Always 4 for OR32. */ -extern int insn_len (int); - -/* Is individual insn's operand signed or unsigned? */ -extern int letter_signed (char); - -/* Number of letters in the individual lettered operand. */ -extern int letter_range (char); - -/* MM: Returns index of given instruction name. */ -extern int insn_index (char *); - -/* MM: Returns instruction name from index. */ -extern const char *insn_name (int); - -/* MM: Constructs new FSM, based on or32_opcodes. */ -extern void build_automata (void); - -/* MM: Destructs FSM. */ -extern void destruct_automata (void); - -/* MM: Decodes instruction using FSM. Call build_automata first. */ -extern int insn_decode (unsigned int); - -/* Disassemble one instruction from insn to disassemble. - Return the size of the instruction. */ -int disassemble_insn (unsigned long); - -#endif diff --git a/binutils-2.25/include/opcode/pdp11.h b/binutils-2.25/include/opcode/pdp11.h index 24e13b25..b44cd464 100644 --- a/binutils-2.25/include/opcode/pdp11.h +++ b/binutils-2.25/include/opcode/pdp11.h @@ -1,5 +1,5 @@ /* PDP-11 opcde list. - Copyright 2001, 2002, 2010 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/binutils-2.25/include/opcode/pj.h b/binutils-2.25/include/opcode/pj.h index e6ffacc4..37515c84 100644 --- a/binutils-2.25/include/opcode/pj.h +++ b/binutils-2.25/include/opcode/pj.h @@ -1,5 +1,5 @@ /* Definitions for decoding the picoJava opcode table. - Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 1999-2014 Free Software Foundation, Inc. Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify diff --git a/binutils-2.25/include/opcode/pn.h b/binutils-2.25/include/opcode/pn.h index 6674030c..2189d723 100644 --- a/binutils-2.25/include/opcode/pn.h +++ b/binutils-2.25/include/opcode/pn.h @@ -1,5 +1,5 @@ /* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. + Copyright (C) 1986-2014 Free Software Foundation, Inc. This file is part of GDB. diff --git a/binutils-2.25/include/opcode/ppc.h b/binutils-2.25/include/opcode/ppc.h index df971302..c797fa55 100644 --- a/binutils-2.25/include/opcode/ppc.h +++ b/binutils-2.25/include/opcode/ppc.h @@ -1,6 +1,5 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, - 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. + Copyright (C) 1994-2014 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/pyr.h b/binutils-2.25/include/opcode/pyr.h index 2fffd946..b31ce304 100644 --- a/binutils-2.25/include/opcode/pyr.h +++ b/binutils-2.25/include/opcode/pyr.h @@ -1,6 +1,6 @@ /* pyramid.opcode.h -- gdb initial attempt. - Copyright 2001, 2010 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/rl78.h b/binutils-2.25/include/opcode/rl78.h index 0f3c64d6..6b0e639f 100644 --- a/binutils-2.25/include/opcode/rl78.h +++ b/binutils-2.25/include/opcode/rl78.h @@ -1,6 +1,5 @@ /* Opcode decoder for the Renesas RL78 - Copyright 2011 - Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/binutils-2.25/include/opcode/rx.h b/binutils-2.25/include/opcode/rx.h index aa85fe4a..76f2035c 100644 --- a/binutils-2.25/include/opcode/rx.h +++ b/binutils-2.25/include/opcode/rx.h @@ -1,6 +1,5 @@ /* Opcode decoder for the Renesas RX - Copyright 2008, 2009, 2010 - Free Software Foundation, Inc. + Copyright (C) 2008-2014 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/binutils-2.25/include/opcode/s390.h b/binutils-2.25/include/opcode/s390.h index 531011e0..0884eb65 100644 --- a/binutils-2.25/include/opcode/s390.h +++ b/binutils-2.25/include/opcode/s390.h @@ -1,5 +1,5 @@ /* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 2000-2014 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. diff --git a/binutils-2.25/include/opcode/score-datadep.h b/binutils-2.25/include/opcode/score-datadep.h index 10ddf32f..5e4ff78a 100644 --- a/binutils-2.25/include/opcode/score-datadep.h +++ b/binutils-2.25/include/opcode/score-datadep.h @@ -1,5 +1,5 @@ /* score-datadep.h -- Score Instructions data dependency table - Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 2006-2014 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/binutils-2.25/include/opcode/score-inst.h b/binutils-2.25/include/opcode/score-inst.h index ecb18da2..04b7c85f 100644 --- a/binutils-2.25/include/opcode/score-inst.h +++ b/binutils-2.25/include/opcode/score-inst.h @@ -1,5 +1,5 @@ /* score-inst.h -- Score Instructions Table - Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 2006-2014 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/binutils-2.25/include/opcode/sparc.h b/binutils-2.25/include/opcode/sparc.h index f05909fe..cf4ff1c6 100644 --- a/binutils-2.25/include/opcode/sparc.h +++ b/binutils-2.25/include/opcode/sparc.h @@ -1,6 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005, 2010, 2011 Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -101,6 +100,7 @@ typedef struct sparc_opcode /* This was called "delayed" in versions before the flags. */ unsigned int flags; unsigned int hwcaps; + unsigned int hwcaps2; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; @@ -116,7 +116,8 @@ typedef struct sparc_opcode #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) -/* These must match the HWCAP_* values precisely. */ +/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* + values precisely. See include/elf/sparc.h. */ #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ @@ -149,6 +150,20 @@ typedef struct sparc_opcode #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ +#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ +#define HWCAP2_VIS3B 0x00000002 /* VIS3 present on multiple chips */ +#define HWCAP2_ADP 0x00000004 /* Application Data Protection */ +#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ +#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ +#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ +#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ +#define HWCAP2_NSEC \ + 0x00000080 /* pause insn with support for nsec timings */ +#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ +#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ +#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ + + /* All sparc opcodes are 32 bits, except for the `set' instruction (really a macro), which is 64 bits. It is handled as a special case. @@ -174,6 +189,7 @@ typedef struct sparc_opcode g frsd floating point register. H frsd floating point register (double/even). J frsd floating point register (quad/multiple of 4). + } frsd floating point register (double/even) that is == frs2 b crs1 coprocessor register c crs2 coprocessor register D crsd coprocessor register @@ -215,6 +231,7 @@ typedef struct sparc_opcode s %fprs. (v9) P %pc. (v9) W %tick. (v9) + { %mcdper. (v9b) o %asi. (v9) 6 %fcc0. (v9) 7 %fcc1. (v9) diff --git a/binutils-2.25/include/opcode/spu-insns.h b/binutils-2.25/include/opcode/spu-insns.h index d6c260aa..e8259e6a 100644 --- a/binutils-2.25/include/opcode/spu-insns.h +++ b/binutils-2.25/include/opcode/spu-insns.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright 2006, 2007, 2010 Free Software Foundation, Inc. + Copyright (C) 2006-2014 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. diff --git a/binutils-2.25/include/opcode/spu.h b/binutils-2.25/include/opcode/spu.h index c6468303..64882f58 100644 --- a/binutils-2.25/include/opcode/spu.h +++ b/binutils-2.25/include/opcode/spu.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright 2006, 2010 Free Software Foundation, Inc. + Copyright (C) 2006-2014 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/tahoe.h b/binutils-2.25/include/opcode/tahoe.h index 70fcf623..664f3b5f 100644 --- a/binutils-2.25/include/opcode/tahoe.h +++ b/binutils-2.25/include/opcode/tahoe.h @@ -2,7 +2,7 @@ * Ported by the State University of New York at Buffalo by the Distributed * Computer Systems Lab, Department of Computer Science, 1991. */ -/* Copyright 2012 Free Software Foundation, Inc. +/* Copyright (C) 2012-2014 Free Software Foundation, Inc. This file is part of GDB and BINUTILS. diff --git a/binutils-2.25/include/opcode/tic30.h b/binutils-2.25/include/opcode/tic30.h index 3f4d3071..1a1c05a4 100644 --- a/binutils-2.25/include/opcode/tic30.h +++ b/binutils-2.25/include/opcode/tic30.h @@ -1,5 +1,5 @@ /* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 1998-2014 Free Software Foundation, Inc. Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/tic4x.h b/binutils-2.25/include/opcode/tic4x.h index 6f16fcb4..15c837e5 100644 --- a/binutils-2.25/include/opcode/tic4x.h +++ b/binutils-2.25/include/opcode/tic4x.h @@ -1,6 +1,6 @@ /* Table of opcodes for the Texas Instruments TMS320C[34]X family. - Copyright (C) 2002, 2003, 2010 Free Software Foundation. + Copyright (C) 2002-2014 Free Software Foundation, Inc. Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) diff --git a/binutils-2.25/include/opcode/tic54x.h b/binutils-2.25/include/opcode/tic54x.h index f468714e..ca2911e3 100644 --- a/binutils-2.25/include/opcode/tic54x.h +++ b/binutils-2.25/include/opcode/tic54x.h @@ -1,5 +1,5 @@ /* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 1999-2014 Free Software Foundation, Inc. Written by Timothy Wall (twall@cygnus.com) This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/tic6x-control-registers.h b/binutils-2.25/include/opcode/tic6x-control-registers.h index b4387779..2afb8d64 100644 --- a/binutils-2.25/include/opcode/tic6x-control-registers.h +++ b/binutils-2.25/include/opcode/tic6x-control-registers.h @@ -1,6 +1,5 @@ /* TI C6X control register information. - Copyright 2010 - Free Software Foundation, Inc. + Copyright (C) 2010-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/tic6x-insn-formats.h b/binutils-2.25/include/opcode/tic6x-insn-formats.h index 80bc9fac..5aea2712 100644 --- a/binutils-2.25/include/opcode/tic6x-insn-formats.h +++ b/binutils-2.25/include/opcode/tic6x-insn-formats.h @@ -1,5 +1,5 @@ /* TI C6X instruction format information. - Copyright 2010-2013 Free Software Foundation, Inc. + Copyright (C) 2010-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/tic6x-opcode-table.h b/binutils-2.25/include/opcode/tic6x-opcode-table.h index d876c564..b93d71e8 100644 --- a/binutils-2.25/include/opcode/tic6x-opcode-table.h +++ b/binutils-2.25/include/opcode/tic6x-opcode-table.h @@ -1,5 +1,5 @@ /* TI C6X opcode table. - Copyright 2010-2013 Free Software Foundation, Inc. + Copyright (C) 2010-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/tic6x.h b/binutils-2.25/include/opcode/tic6x.h index d76c5e1a..7ccffb09 100644 --- a/binutils-2.25/include/opcode/tic6x.h +++ b/binutils-2.25/include/opcode/tic6x.h @@ -1,5 +1,5 @@ /* TI C6X opcode information. - Copyright 2010-2013 Free Software Foundation, Inc. + Copyright (C) 2010-2014 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/tic80.h b/binutils-2.25/include/opcode/tic80.h index 43c84be5..e13f2a60 100644 --- a/binutils-2.25/include/opcode/tic80.h +++ b/binutils-2.25/include/opcode/tic80.h @@ -1,5 +1,5 @@ /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Written by Fred Fish (fnf@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/tilegx.h b/binutils-2.25/include/opcode/tilegx.h index c11fc166..9dd074d6 100644 --- a/binutils-2.25/include/opcode/tilegx.h +++ b/binutils-2.25/include/opcode/tilegx.h @@ -1,6 +1,6 @@ /* TILE-Gx opcode information. * - * Copyright 2011 Free Software Foundation, Inc. + * Copyright (C) 2011-2014 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/tilepro.h b/binutils-2.25/include/opcode/tilepro.h index 767926bd..410ee410 100644 --- a/binutils-2.25/include/opcode/tilepro.h +++ b/binutils-2.25/include/opcode/tilepro.h @@ -1,6 +1,6 @@ /* TILEPro opcode information. * - * Copyright 2011 Free Software Foundation, Inc. + * Copyright (C) 2011-2014 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/include/opcode/v850.h b/binutils-2.25/include/opcode/v850.h index 02ef3d4c..d19ff80f 100644 --- a/binutils-2.25/include/opcode/v850.h +++ b/binutils-2.25/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright 1996-2013 Free Software Foundation, Inc. + Copyright (C) 1996-2014 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/binutils-2.25/include/opcode/vax.h b/binutils-2.25/include/opcode/vax.h index f5cdd243..3b384135 100644 --- a/binutils-2.25/include/opcode/vax.h +++ b/binutils-2.25/include/opcode/vax.h @@ -1,5 +1,5 @@ /* Vax opcde list. - Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/binutils-2.25/include/opcode/xgate.h b/binutils-2.25/include/opcode/xgate.h index 8451e66c..9124b84b 100644 --- a/binutils-2.25/include/opcode/xgate.h +++ b/binutils-2.25/include/opcode/xgate.h @@ -1,5 +1,5 @@ /* xgate.h -- Freescale XGATE opcode list - Copyright 2010, 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2010-2014 Free Software Foundation, Inc. Written by Sean Keys (skeys@ipdatasys.com) This file is part of the GNU opcodes library. |