diff options
Diffstat (limited to 'binutils-2.25/include/opcode/aarch64.h')
| -rw-r--r-- | binutils-2.25/include/opcode/aarch64.h | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/binutils-2.25/include/opcode/aarch64.h b/binutils-2.25/include/opcode/aarch64.h index eaf3cda5..c0afd74a 100644 --- a/binutils-2.25/include/opcode/aarch64.h +++ b/binutils-2.25/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright (C) 2009-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -38,6 +38,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ +#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -85,6 +86,7 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_ADDRESS, AARCH64_OPND_CLASS_IMMEDIATE, AARCH64_OPND_CLASS_SYSTEM, + AARCH64_OPND_CLASS_COND, }; /* Operand code that helps both parsing and coding. @@ -105,6 +107,7 @@ enum aarch64_opnd AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ @@ -168,6 +171,7 @@ enum aarch64_opnd AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ AARCH64_OPND_COND, /* Standard condition as the last operand. */ + AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ @@ -338,6 +342,7 @@ enum aarch64_insn_class loadlit, log_imm, log_shift, + lse_atomic, movewide, pcreladdr, ic_system, @@ -548,7 +553,9 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_N (1 << 23) /* Opcode dependent field. */ #define F_OD(X) (((X) & 0x7) << 24) -/* Next bit is 27. */ +/* Instruction has the field of 'sz'. */ +#define F_LSE_SZ (1 << 27) +/* Next bit is 28. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -597,7 +604,7 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) static inline bfd_boolean opcode_has_special_coder (const aarch64_opcode *opcode) { - return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T + return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE : FALSE; } @@ -609,13 +616,22 @@ struct aarch64_name_value_pair }; extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; -extern const struct aarch64_name_value_pair aarch64_sys_regs []; -extern const struct aarch64_name_value_pair aarch64_pstatefields []; extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; extern const struct aarch64_name_value_pair aarch64_prfops [32]; typedef struct { + const char * name; + aarch64_insn value; + uint32_t flags; +} aarch64_sys_reg; + +extern const aarch64_sys_reg aarch64_sys_regs []; +extern const aarch64_sys_reg aarch64_pstatefields []; +extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); + +typedef struct +{ const char *template; uint32_t value; int has_xt; |