diff options
Diffstat (limited to 'binutils-2.25/gas/doc')
61 files changed, 1065 insertions, 234 deletions
diff --git a/binutils-2.25/gas/doc/Makefile.am b/binutils-2.25/gas/doc/Makefile.am index 3d1e9339..c2ddc023 100644 --- a/binutils-2.25/gas/doc/Makefile.am +++ b/binutils-2.25/gas/doc/Makefile.am @@ -1,6 +1,6 @@ ## Process this file with automake to generate Makefile.in # -# Copyright 2012 Free Software Foundation +# Copyright (C) 2012-2014 Free Software Foundation, Inc. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -75,6 +75,7 @@ CPU_DOCS = \ c-mt.texi \ c-msp430.texi \ c-nios2.texi \ + c-nds32.texi \ c-ns32k.texi \ c-pdp11.texi \ c-pj.texi \ @@ -111,8 +112,6 @@ MAINTAINERCLEANFILES = asconfig.texi BASEDIR = $(srcdir)/../.. BFDDIR = $(BASEDIR)/bfd -CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in - # Maintenance # We need it for the taz target in ../../Makefile.in. diff --git a/binutils-2.25/gas/doc/Makefile.in b/binutils-2.25/gas/doc/Makefile.in index 4c3c4fb8..2db51216 100644 --- a/binutils-2.25/gas/doc/Makefile.in +++ b/binutils-2.25/gas/doc/Makefile.in @@ -16,7 +16,7 @@ @SET_MAKE@ # -# Copyright 2012 Free Software Foundation +# Copyright (C) 2012-2014 Free Software Foundation, Inc. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -72,7 +72,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \ $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \ - $(top_srcdir)/configure.in + $(top_srcdir)/../bfd/version.m4 $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs @@ -317,6 +317,7 @@ CPU_DOCS = \ c-mt.texi \ c-msp430.texi \ c-nios2.texi \ + c-nds32.texi \ c-ns32k.texi \ c-pdp11.texi \ c-pj.texi \ @@ -346,7 +347,6 @@ noinst_TEXINFOS = internals.texi MAINTAINERCLEANFILES = asconfig.texi as.info BASEDIR = $(srcdir)/../.. BFDDIR = $(BASEDIR)/bfd -CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in # Automake 1.9 will only build info files in the objdir if they are # mentioned in DISTCLEANFILES. It doesn't have to be unconditional, diff --git a/binutils-2.25/gas/doc/all.texi b/binutils-2.25/gas/doc/all.texi index 99dbf8ff..94b88bff 100644 --- a/binutils-2.25/gas/doc/all.texi +++ b/binutils-2.25/gas/doc/all.texi @@ -1,6 +1,4 @@ -@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002, -@c 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1992-2014 Free Software Foundation, Inc. @c This file is part of the documentation for the GAS manual @c Configuration settings for all-inclusive version of manual @@ -59,6 +57,7 @@ @set MS1 @set MSP430 @set NIOSII +@set NDS32 @set NS32K @set PDP11 @set PJ diff --git a/binutils-2.25/gas/doc/as.texinfo b/binutils-2.25/gas/doc/as.texinfo index 98435742..243851be 100644 --- a/binutils-2.25/gas/doc/as.texinfo +++ b/binutils-2.25/gas/doc/as.texinfo @@ -1,5 +1,5 @@ \input texinfo @c -*-Texinfo-*- -@c Copyright 1991-2013 Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c UPDATE!! On future updates-- @c (1) check for new machine-dep cmdline options in @c md_parse_option definitions in config/tc-*.c @@ -100,7 +100,7 @@ This file documents the GNU Assembler "@value{AS}". @c man begin COPYRIGHT -Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 @@ -149,7 +149,7 @@ done. @end tex @vskip 0pt plus 1filll -Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 @@ -399,9 +399,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}] [@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}] [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}] + [@b{-mfp64}] [@b{-mgp64}] [@b{-mfpxx}] + [@b{-modd-spreg}] [@b{-mno-odd-spreg}] [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] - [@b{-mips64}] [@b{-mips64r2}] + [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips32r6}] [@b{-mips64}] [@b{-mips64r2}] + [@b{-mips64r3}] [@b{-mips64r5}] [@b{-mips64r6}] [@b{-construct-floats}] [@b{-no-construct-floats}] [@b{-mnan=@var{encoding}}] [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] @@ -413,10 +416,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mdsp}] [@b{-mno-dsp}] [@b{-mdspr2}] [@b{-mno-dspr2}] [@b{-mmsa}] [@b{-mno-msa}] + [@b{-mxpa}] [@b{-mno-xpa}] [@b{-mmt}] [@b{-mno-mt}] [@b{-mmcu}] [@b{-mno-mcu}] [@b{-minsn32}] [@b{-mno-insn32}] [@b{-mfix7000}] [@b{-mno-fix7000}] + [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}] [@b{-mfix-vr4120}] [@b{-mno-fix-vr4120}] [@b{-mfix-vr4130}] [@b{-mno-fix-vr4130}] [@b{-mdebug}] [@b{-no-mdebug}] @@ -436,6 +441,18 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-relax-all}] [@b{-relax-section}] [@b{-no-relax}] [@b{-EB}] [@b{-EL}] @end ifset +@ifset NDS32 + +@emph{Target NDS32 options:} + [@b{-EL}] [@b{-EB}] [@b{-O}] [@b{-Os}] [@b{-mcpu=@var{cpu}}] + [@b{-misa=@var{isa}}] [@b{-mabi=@var{abi}}] [@b{-mall-ext}] + [@b{-m[no-]16-bit}] [@b{-m[no-]perf-ext}] [@b{-m[no-]perf2-ext}] + [@b{-m[no-]string-ext}] [@b{-m[no-]dsp-ext}] [@b{-m[no-]mac}] [@b{-m[no-]div}] + [@b{-m[no-]audio-isa-ext}] [@b{-m[no-]fpu-sp-ext}] [@b{-m[no-]fpu-dp-ext}] + [@b{-m[no-]fpu-fma}] [@b{-mfpu-freg=@var{FREG}}] [@b{-mreduced-regs}] + [@b{-mfull-regs}] [@b{-m[no-]dx-regs}] [@b{-mpic}] [@b{-mno-relax}] + [@b{-mb2bb}] +@end ifset @ifset PDP11 @emph{Target PDP11 options:} @@ -464,6 +481,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-msolaris}|@b{-mno-solaris}] [@b{-nops=@var{count}}] @end ifset +@ifset RL78 + +@emph{Target RL78 options:} + [@b{-mg10}] + [@b{-m32bit-doubles}|@b{-m64bit-doubles}] +@end ifset @ifset RX @emph{Target RX options:} @@ -530,6 +553,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{--[no-]target-align}] [@b{--[no-]longcalls}] [@b{--[no-]transform}] [@b{--rename-section} @var{oldname}=@var{newname}] + [@b{--[no-]trampolines}] @end ifset @ifset Z80 @@ -835,6 +859,8 @@ Select either big-endian (-EB) or little-endian (-EL) output. @item -mthumb-interwork Specify that the code has been generated with interworking between Thumb and ARM code in mind. +@item -mccs +Turns on CodeComposer Studio assembly syntax compatibility mode. @item -k Specify that PIC code has been generated. @end table @@ -1249,15 +1275,24 @@ Generate ``little endian'' format output. @itemx -mips5 @itemx -mips32 @itemx -mips32r2 +@itemx -mips32r3 +@itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 +@itemx -mips64r3 +@itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an alias for @samp{-march=r6000}, @samp{-mips3} is an alias for @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS64, and MIPS64 Release 2 ISA processors, respectively. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to generic +MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 +Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and +MIPS64 Release 6 ISA processors, respectively. @item -march=@var{cpu} Generate code for a particular MIPS CPU. @@ -1270,6 +1305,11 @@ Schedule and tune for a particular MIPS CPU. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-rm7000 +@itemx -mno-fix-rm7000 +Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. + @item -mdebug @itemx -no-mdebug Cause stabs-style debugging output to go into an ECOFF-style .mdebug @@ -1286,6 +1326,25 @@ flags force a certain group of registers to be treated as 32 bits wide at all times. @samp{-mgp32} controls the size of general-purpose registers and @samp{-mfp32} controls the size of floating-point registers. +@item -mgp64 +@itemx -mfp64 +The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 64 bits wide at +all times. @samp{-mgp64} controls the size of general-purpose registers +and @samp{-mfp64} controls the size of floating-point registers. + +@item -mfpxx +The register sizes are normally inferred from the ISA and ABI, but using +this flag in combination with @samp{-mabi=32} enables an ABI variant +which will operate correctly with floating-point registers which are +32 or 64 bits wide. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. @samp{-mfpxx} implies +@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}. + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -1336,6 +1395,12 @@ Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. @samp{-mno-msa} turns off this option. +@item -mxpa +@itemx -mno-xpa +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +@samp{-mno-xpa} turns off this option. + @item -mmt @itemx -mno-mt Generate code for the MT Application Specific Extension. @@ -1465,6 +1530,25 @@ Meta processor. See the info pages for documentation of the MMIX-specific options. @end ifset +@ifset NDS32 + +@ifclear man +@xref{NDS32 Options}, for the options available when @value{AS} is configured +for a NDS32 processor. +@end ifclear +@c ended inside the included file +@end ifset + +@ifset man +@c man begin OPTIONS +The following options are available when @value{AS} is configured for a +NDS32 processor. +@c man end +@c man begin INCLUDE +@include c-nds32.texi +@c ended inside the included file +@end ifset + @c man end @ifset PPC @@ -4310,7 +4394,7 @@ required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate. The way the required alignment is specified varies from system to system. -For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, +For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k, s390, sparc, tic4x, tic80 and xtensa, the first expression is the alignment request in bytes. For example @samp{.align 8} advances the location counter until it is a multiple of 8. If the location counter @@ -6946,16 +7030,27 @@ The floating-point ABI used by this object file. The value will be: @item 0 for files not affected by the floating-point ABI. @item -1 for files using the hardware floating-point with a standard double-precision -FPU. +1 for files using the hardware floating-point ABI with a standard +double-precision FPU. @item 2 for files using the hardware floating-point ABI with a single-precision FPU. @item 3 for files using the software floating-point ABI. @item -4 for files using the hardware floating-point ABI with 64-bit wide -double-precision floating-point registers and 32-bit wide general -purpose registers. +4 for files using the deprecated hardware floating-point ABI which used 64-bit +floating-point registers, 32-bit general-purpose registers and increased the +number of callee-saved floating-point registers. +@item +5 for files using the hardware floating-point ABI with a double-precision FPU +with either 32-bit or 64-bit floating-point registers and 32-bit +general-purpose registers. +@item +6 for files using the hardware floating-point ABI with 64-bit floating-point +registers and 32-bit general-purpose registers. +@item +7 for files using the hardware floating-point ABI with 64-bit floating-point +registers, 32-bit general-purpose registers and a rule that forbids the +direct use of odd-numbered single-precision floating-point registers. @end itemize @end table @@ -7121,6 +7216,9 @@ subject, see the hardware manufacturer's manual. @ifset MSP430 * MSP430-Dependent:: MSP430 Dependent Features @end ifset +@ifset NDS32 +* NDS32-Dependent:: Andes NDS32 Dependent Features +@end ifset @ifset NIOSII * NiosII-Dependent:: Altera Nios II Dependent Features @end ifset @@ -7335,6 +7433,10 @@ family. @include c-msp430.texi @end ifset +@ifset NDS32 +@include c-nds32.texi +@end ifset + @ifset NIOSII @include c-nios2.texi @end ifset diff --git a/binutils-2.25/gas/doc/c-aarch64.texi b/binutils-2.25/gas/doc/c-aarch64.texi index 60190063..8fbae061 100644 --- a/binutils-2.25/gas/doc/c-aarch64.texi +++ b/binutils-2.25/gas/doc/c-aarch64.texi @@ -1,4 +1,4 @@ -@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c Contributed by ARM Ltd. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -16,9 +16,9 @@ @end ifclear @cindex AArch64 support -@cindex Thumb support @menu * AArch64 Options:: Options +* AArch64 Extensions:: Extensions * AArch64 Syntax:: Syntax * AArch64 Floating Point:: Floating Point * AArch64 Directives:: AArch64 Machine Directives @@ -34,25 +34,104 @@ @c man begin OPTIONS @table @gcctabopt -@cindex @code{-EB} command line option, AArch64 +@cindex @option{-EB} command line option, AArch64 @item -EB This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -@cindex @code{-EL} command line option, AArch64 +@cindex @option{-EL} command line option, AArch64 @item -EL This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. -@cindex @code{-mabi=} command line option, AArch64 +@cindex @option{-mabi=} command line option, AArch64 @item -mabi=@var{abi} Specify which ABI the source code uses. The recognized arguments are: @code{ilp32} and @code{lp64}, which decides the generated object file in ELF32 and ELF64 format respectively. The default is @code{lp64}. +@cindex @option{-mcpu=} command line option, AArch64 +@item -mcpu=@var{processor}[+@var{extension}@dots{}] +This option specifies the target processor. The assembler will issue an error +message if an attempt is made to assemble an instruction which will not execute +on the target processor. The following processor names are recognized: +@code{cortex-a53}, +@code{cortex-a57}, +@code{xgene1}, +and +@code{xgene2}. +The special name @code{all} may be used to allow the assembler to accept +instructions valid for any supported processor, including all optional +extensions. + +In addition to the basic instruction set, the assembler can be told to +accept, or restrict, various extension mnemonics that extend the +processor. @xref{AArch64 Extensions}. + +If some implementations of a particular processor can have an +extension, then then those extensions are automatically enabled. +Consequently, you will not normally have to specify any additional +extensions. + +@cindex @option{-march=} command line option, AArch64 +@item -march=@var{architecture}[+@var{extension}@dots{}] +This option specifies the target architecture. The assembler will +issue an error message if an attempt is made to assemble an +instruction which will not execute on the target architecture. The +only value for @var{architecture} is @code{armv8-a}. + +If both @option{-mcpu} and @option{-march} are specified, the +assembler will use the setting for @option{-mcpu}. If neither are +specified, the assembler will default to @option{-mcpu=all}. + +The architecture option can be extended with the same instruction set +extension options as the @option{-mcpu} option. Unlike +@option{-mcpu}, extensions are not always enabled by default, +@xref{AArch64 Extensions}. + +@cindex @code{-mverbose-error} command line option, AArch64 +@item -mverbose-error +This option enables verbose error messages for AArch64 gas. This option +is enabled by default. + +@cindex @code{-mno-verbose-error} command line option, AArch64 +@item -mno-verbose-error +This option disables verbose error messages in AArch64 gas. + @end table @c man end +@node AArch64 Extensions +@section Architecture Extensions + +The table below lists the permitted architecture extensions that are +supported by the assembler and the conditions under which they are +automatically enabled. + +Multiple extensions may be specified, separated by a @code{+}. +Extension mnemonics may also be removed from those the assembler +accepts. This is done by prepending @code{no} to the option that adds +the extension. Extensions that are removed must be listed after all +extensions that have been added. + +Enabling an extension that requires other extensions will +automatically cause those extensions to be enabled. Similarly, +disabling an extension that is required by other extensions will +automatically cause those extensions to be disabled. + +@multitable @columnfractions .12 .17 .17 .54 +@headitem Extension @tab Minimum Architecture @tab Enabled by default + @tab Description +@item @code{crc} @tab ARMv8-A @tab No + @tab Enable CRC instructions. +@item @code{crypto} @tab ARMv8-A @tab No + @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. +@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later + @tab Enable floating-point extensions. +@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later + @tab Enable Advanced SIMD extensions. This implies @code{fp}. +@end multitable + @node AArch64 Syntax @section Syntax @menu @@ -108,24 +187,24 @@ For example to load the 48-bit absolute address of @var{foo} into x0: @cindex ADRP, ADD, LDR/STR group relocations, AArch64 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} instructions can be generated by prefixing the label with -@samp{#:pg_hi21:} and @samp{#:lo12:} respectively. +@samp{:pg_hi21:} and @samp{#:lo12:} respectively. For example to use 33-bit (+/-4GB) pc-relative addressing to load the address of @var{foo} into x0: @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo add x0, x0, #:lo12:foo @end smallexample Or to load the value of @var{foo} into x0: @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo ldr x0, [x0, #:lo12:foo] @end smallexample -Note that @samp{#:pg_hi21:} is optional. +Note that @samp{:pg_hi21:} is optional. @smallexample adrp x0, foo @@ -134,7 +213,7 @@ Note that @samp{#:pg_hi21:} is optional. is equivalent to @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo @end smallexample @node AArch64 Floating Point @@ -174,12 +253,12 @@ This directive switches to the @code{.bss} section. This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). -@code{GAS} maintains a separate literal pool for each section and each +GAS maintains a separate literal pool for each section and each sub-section. The @code{.ltorg} directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped. -Note - older versions of @code{GAS} would dump the current literal +Note - older versions of GAS would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools. @@ -240,7 +319,7 @@ should only be done if it is really necessary. @cindex AArch64 opcodes @cindex opcodes for AArch64 -@code{@value{AS}} implements all the standard AArch64 opcodes. It also +GAS implements all the standard AArch64 opcodes. It also implements several pseudo opcodes, including several synthetic load instructions. diff --git a/binutils-2.25/gas/doc/c-alpha.texi b/binutils-2.25/gas/doc/c-alpha.texi index dd484138..302ed0fd 100644 --- a/binutils-2.25/gas/doc/c-alpha.texi +++ b/binutils-2.25/gas/doc/c-alpha.texi @@ -1,5 +1,4 @@ -@c Copyright 2002, 2003, 2005, 2009, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-arc.texi b/binutils-2.25/gas/doc/c-arc.texi index 38bd3c85..c7bbb66e 100644 --- a/binutils-2.25/gas/doc/c-arc.texi +++ b/binutils-2.25/gas/doc/c-arc.texi @@ -1,4 +1,4 @@ -@c Copyright 2000-2013 Free Software Foundation, Inc. +@c Copyright (C) 2000-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-arm.texi b/binutils-2.25/gas/doc/c-arm.texi index 37756a06..7bcce943 100644 --- a/binutils-2.25/gas/doc/c-arm.texi +++ b/binutils-2.25/gas/doc/c-arm.texi @@ -1,4 +1,4 @@ -@c Copyright 1996-2013 Free Software Foundation, Inc. +@c Copyright (C) 1996-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -200,6 +200,7 @@ names are recognized: @code{armv6s-m}, @code{armv7}, @code{armv7-a}, +@code{armv7ve}, @code{armv7-r}, @code{armv7-m}, @code{armv7e-m}, @@ -368,6 +369,10 @@ the linker option of the same name. Enable or disable warnings about using deprecated options or features. The default is to warn. +@cindex @code{-mccs} command line option, ARM +@item -mccs +Turns on CodeComposer Studio assembly syntax compatibility mode. + @end table @@ -563,13 +568,6 @@ incrementally to the architecture being compiled for. @item .arm This performs the same action as @var{.code 32}. -@anchor{arm_pad} -@cindex @code{.pad} directive, ARM -@item .pad #@var{count} -Generate unwinder annotations for a stack adjustment of @var{count} bytes. -A positive value indicates the function prologue allocated stack space by -decrementing the stack pointer. - @c BBBBBBBBBBBBBBBBBBBBBBBBBB @cindex @code{.bss} directive, ARM @@ -769,6 +767,7 @@ This directive writes 12-byte packed floating-point values to the output section. These are not compatible with current ARM processors or ABIs. +@anchor{arm_pad} @cindex @code{.pad} directive, ARM @item .pad #@var{count} Generate unwinder annotations for a stack adjustment of @var{count} bytes. diff --git a/binutils-2.25/gas/doc/c-avr.texi b/binutils-2.25/gas/doc/c-avr.texi index 213e82c3..75b5d20f 100644 --- a/binutils-2.25/gas/doc/c-avr.texi +++ b/binutils-2.25/gas/doc/c-avr.texi @@ -1,4 +1,4 @@ -@c Copyright 2006-2013 Free Software Foundation, Inc. +@c Copyright (C) 2006-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -45,7 +45,7 @@ space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, -at86rf401). +attiny828, at86rf401, ata6289, ata5272). Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711). @@ -54,64 +54,75 @@ Instruction set avr31 is for the classic AVR core with exactly 128K program memory space (MCU types: atmega103, at43usb320). Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP -instructions (MCU types: attiny167, at90usb82, at90usb162, atmega8u2, -atmega16u2, atmega32u2). +instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, +atmega8u2, atmega16u2, atmega32u2, ata5505). Instruction set avr4 is for the enhanced AVR core with up to 8K program -memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88, -atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, -at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6289). +memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, +atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, +atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, +ata6285, ata6286). Instruction set avr5 is for the enhanced AVR core with up to 128K program -memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, -atmega163, atmega164a, atmega164p, atmega165, atmega165a, atmega165p, -atmega168, atmega168a, atmega168p, atmega169, atmega169a, atmega169p, -atmega169pa, atmega32, atmega323, atmega324a, atmega324p, atmega325, -atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, -atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, -atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, -atmega3290p, atmega3290pa, atmega406, atmega64, atmega640, atmega644, -atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, -atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, -atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, -atmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, atmega16hvb, -atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, -at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, -atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, -atmega32u6, at90usb646, at90usb647, at94k, at90scr100). - -Instruction set avr51 is for the enhanced AVR core with exactly 128K program -memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p, -atmega128rfa1, -atmega128rfr2, atmega1284rfr2, -at90can128, at90usb1286, at90usb1287, m3000). - -Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: -atmega2560, atmega2561, -atmega256rfr2, atmega2564rfr2). - -Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program -memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4, -atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1). - -Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program -memory space and greater than 64K data space (MCU types: none). - -Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program -memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3). - -Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program -memory space and greater than 64K data space (MCU types: atxmega64a1, -atxmega64a1u). - -Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program -memory space and less than 64K data space (MCU types: atxmega128a3, -atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3, -atxmega256a3b, atxmega256a3bu, atxmega192d3). - -Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program -memory space and greater than 64K data space (MCU types: atxmega128a1, -atxmega128a1u). +memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, +atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, +atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, +atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, +atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, +atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, +atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, +atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, +atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, +atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, +atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, +atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, +atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, +atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, +at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, +atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, +at90scr100, ata5790, ata5795). + +Instruction set avr51 is for the enhanced AVR core with exactly 128K +program memory space (MCU types: atmega128, atmega128a, atmega1280, +atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, +atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). + +Instruction set avr6 is for the enhanced AVR core with a 3-byte PC +(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). + +Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K +program memory space and less than 64K data space (MCU types: +atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, +atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, +atxmega8e5, atxmega32e5, atxmega32x1). + +Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K +program memory space and greater than 64K data space (MCU types: +none). + +Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K +program memory space and less than 64K data space (MCU types: +atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, +atxmega64c3, atxmega64d3, atxmega64d4). + +Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K +program memory space and greater than 64K data space (MCU types: +atxmega64a1, atxmega64a1u). + +Instruction set avrxmega6 is for the XMEGA AVR core with larger than +64K program memory space and less than 64K data space (MCU types: +atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, +atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, +atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, +atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, +atxmega256d3). + +Instruction set avrxmega7 is for the XMEGA AVR core with larger than +64K program memory space and greater than 64K data space (MCU types: +atxmega128a1, atxmega128a1u, atxmega128a4u). + +Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 +microcontrollers. @cindex @code{-mall-opcodes} command line option, AVR @item -mall-opcodes @@ -125,6 +136,10 @@ This option disable warnings for skipping two-word instructions. @item -mno-wrap This option reject @code{rjmp/rcall} instructions with 8K wrap-around. +@cindex @code{-mrmw} command line option, AVR +@item -mrmw +Accept Read-Modify-Write (@code{XCH,LAC,LAS,LAT}) instructions. + @end table diff --git a/binutils-2.25/gas/doc/c-bfin.texi b/binutils-2.25/gas/doc/c-bfin.texi index 870e0dbc..35de1fae 100644 --- a/binutils-2.25/gas/doc/c-bfin.texi +++ b/binutils-2.25/gas/doc/c-bfin.texi @@ -1,5 +1,4 @@ -@c Copyright 2005, 2006, 2009, 2010, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2005-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-cr16.texi b/binutils-2.25/gas/doc/c-cr16.texi index b996d732..20b118df 100644 --- a/binutils-2.25/gas/doc/c-cr16.texi +++ b/binutils-2.25/gas/doc/c-cr16.texi @@ -1,4 +1,4 @@ -@c Copyright 2007-2013 Free Software Foundation, Inc. +@c Copyright (C) 2007-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-cris.texi b/binutils-2.25/gas/doc/c-cris.texi index ff27921b..73ba059f 100644 --- a/binutils-2.25/gas/doc/c-cris.texi +++ b/binutils-2.25/gas/doc/c-cris.texi @@ -1,4 +1,4 @@ -@c Copyright 2002, 2004 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c CRIS description contributed by Axis Communications. diff --git a/binutils-2.25/gas/doc/c-d10v.texi b/binutils-2.25/gas/doc/c-d10v.texi index d6c0bb62..3dd52b5a 100644 --- a/binutils-2.25/gas/doc/c-d10v.texi +++ b/binutils-2.25/gas/doc/c-d10v.texi @@ -1,4 +1,4 @@ -@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc. +@c Copyright (C) 1996-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-d30v.texi b/binutils-2.25/gas/doc/c-d30v.texi index aec7f68f..6e86f4d4 100644 --- a/binutils-2.25/gas/doc/c-d30v.texi +++ b/binutils-2.25/gas/doc/c-d30v.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1997, 2011 Free Software Foundation, Inc. +@c Copyright (C) 1997-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-epiphany.texi b/binutils-2.25/gas/doc/c-epiphany.texi index 8e2b94dd..29862c23 100644 --- a/binutils-2.25/gas/doc/c-epiphany.texi +++ b/binutils-2.25/gas/doc/c-epiphany.texi @@ -1,4 +1,4 @@ -@c Copyright 1999, 2002, 2011 Free Software Foundation, Inc. +@c Copyright (C) 1999-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-h8300.texi b/binutils-2.25/gas/doc/c-h8300.texi index 5245c666..cbdebbab 100644 --- a/binutils-2.25/gas/doc/c-h8300.texi +++ b/binutils-2.25/gas/doc/c-h8300.texi @@ -1,5 +1,4 @@ -@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003, 2008, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-hppa.texi b/binutils-2.25/gas/doc/c-hppa.texi index 2bb1ae4f..0e0e152d 100644 --- a/binutils-2.25/gas/doc/c-hppa.texi +++ b/binutils-2.25/gas/doc/c-hppa.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1998, 2004, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @page diff --git a/binutils-2.25/gas/doc/c-i370.texi b/binutils-2.25/gas/doc/c-i370.texi index a580a7cd..2a05a942 100644 --- a/binutils-2.25/gas/doc/c-i370.texi +++ b/binutils-2.25/gas/doc/c-i370.texi @@ -1,4 +1,4 @@ -@c Copyright 2000, 2002 Free Software Foundation, Inc. +@c Copyright (C) 2000-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-i386.texi b/binutils-2.25/gas/doc/c-i386.texi index 8a4a5f16..fd6c3804 100644 --- a/binutils-2.25/gas/doc/c-i386.texi +++ b/binutils-2.25/gas/doc/c-i386.texi @@ -1,4 +1,4 @@ -@c Copyright 1991-2013 Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end @@ -151,16 +151,28 @@ accept various extension mnemonics. For example, @code{smap}, @code{mpx}, @code{sha}, +@code{prefetchwt1}, +@code{clflushopt}, +@code{se1}, +@code{clwb}, +@code{pcommit}, @code{avx512f}, @code{avx512cd}, @code{avx512er}, @code{avx512pf}, +@code{avx512vl}, +@code{avx512bw}, +@code{avx512dq}, +@code{avx512ifma}, +@code{avx512vbmi}, @code{noavx}, @code{vmx}, @code{vmfunc}, @code{smx}, @code{xsave}, @code{xsaveopt}, +@code{xsavec}, +@code{xsaves}, @code{aes}, @code{pclmul}, @code{fsgsbase}, @@ -283,6 +295,36 @@ The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. +@cindex @samp{-mbig-obj} option, x86-64 +@item -mbig-obj +On x86-64 PE/COFF target this option forces the use of big object file +format, which allows more than 32768 sections. + +@cindex @samp{-momit-lock-prefix=} option, i386 +@cindex @samp{-momit-lock-prefix=} option, x86-64 +@item -momit-lock-prefix=@var{no} +@itemx -momit-lock-prefix=@var{yes} +These options control how the assembler should encode lock prefix. +This option is intended as a workaround for processors, that fail on +lock prefix. This option can only be safely used with single-core, +single-thread computers +@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. +@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, +which is the default. + +@cindex @samp{-mevexrcig=} option, i386 +@cindex @samp{-mevexrcig=} option, x86-64 +@item -mevexrcig=@var{rne} +@itemx -mevexrcig=@var{rd} +@itemx -mevexrcig=@var{ru} +@itemx -mevexrcig=@var{rz} +These options control how the assembler should encode SAE-only +EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits +of EVEX instruction with 00, which is the default. +@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} +and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. + @end table @c man end @@ -1061,17 +1103,15 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} -@item @samp{.smap} @tab @samp{.mpx} -@item @samp{.smap} @tab @samp{.sha} +@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} +@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} +@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} +@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} +@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} -@item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} -@item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} -@item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} -@item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} -@item @samp{.cx16} @tab @samp{.padlock} @end multitable Apart from the warning, there are only two other effects on diff --git a/binutils-2.25/gas/doc/c-i860.texi b/binutils-2.25/gas/doc/c-i860.texi index a66024e3..7940a944 100644 --- a/binutils-2.25/gas/doc/c-i860.texi +++ b/binutils-2.25/gas/doc/c-i860.texi @@ -1,4 +1,4 @@ -@c Copyright 2000, 2003, 2011 Free Software Foundation, Inc. +@c Copyright (C) 2000-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-i960.texi b/binutils-2.25/gas/doc/c-i960.texi index e8a2e61f..65f0a07e 100644 --- a/binutils-2.25/gas/doc/c-i960.texi +++ b/binutils-2.25/gas/doc/c-i960.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 2002, 2006, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-ia64.texi b/binutils-2.25/gas/doc/c-ia64.texi index eb928363..afbec2fc 100644 --- a/binutils-2.25/gas/doc/c-ia64.texi +++ b/binutils-2.25/gas/doc/c-ia64.texi @@ -1,5 +1,4 @@ -@c Copyright 2002, 2003, 2005 -@c Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c Contributed by David Mosberger-Tang <davidm@hpl.hp.com> @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-ip2k.texi b/binutils-2.25/gas/doc/c-ip2k.texi index c33042b4..7f881763 100644 --- a/binutils-2.25/gas/doc/c-ip2k.texi +++ b/binutils-2.25/gas/doc/c-ip2k.texi @@ -1,5 +1,4 @@ -@c Copyright 2002, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-lm32.texi b/binutils-2.25/gas/doc/c-lm32.texi index d09fd27d..767748be 100644 --- a/binutils-2.25/gas/doc/c-lm32.texi +++ b/binutils-2.25/gas/doc/c-lm32.texi @@ -1,5 +1,4 @@ -@c Copyright 2008, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2008-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-m32c.texi b/binutils-2.25/gas/doc/c-m32c.texi index 16acc8d3..2a4ee362 100644 --- a/binutils-2.25/gas/doc/c-m32c.texi +++ b/binutils-2.25/gas/doc/c-m32c.texi @@ -1,5 +1,4 @@ -@c Copyright 2005, 2008 -@c Free Software Foundation, Inc. +@c Copyright (C) 2005-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-m32r.texi b/binutils-2.25/gas/doc/c-m32r.texi index abb07285..079f372a 100644 --- a/binutils-2.25/gas/doc/c-m32r.texi +++ b/binutils-2.25/gas/doc/c-m32r.texi @@ -1,4 +1,4 @@ -@c Copyright 1991-2013 Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-m68hc11.texi b/binutils-2.25/gas/doc/c-m68hc11.texi index 2583c016..cf066677 100644 --- a/binutils-2.25/gas/doc/c-m68hc11.texi +++ b/binutils-2.25/gas/doc/c-m68hc11.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, -@c 2006, 2011, 2012 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-m68k.texi b/binutils-2.25/gas/doc/c-m68k.texi index 7beca110..d260d3d7 100644 --- a/binutils-2.25/gas/doc/c-m68k.texi +++ b/binutils-2.25/gas/doc/c-m68k.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, -@c 2004, 2006, 2007, 2011 Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-metag.texi b/binutils-2.25/gas/doc/c-metag.texi index f55db22e..09f89582 100644 --- a/binutils-2.25/gas/doc/c-metag.texi +++ b/binutils-2.25/gas/doc/c-metag.texi @@ -1,4 +1,4 @@ -@c Copyright 2013 Free Software Foundation, Inc. +@c Copyright (C) 2013-2014 Free Software Foundation, Inc. @c Contributed by Imagination Technologies Ltd. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-microblaze.texi b/binutils-2.25/gas/doc/c-microblaze.texi index 0027019a..a1c71cee 100644 --- a/binutils-2.25/gas/doc/c-microblaze.texi +++ b/binutils-2.25/gas/doc/c-microblaze.texi @@ -1,5 +1,4 @@ -@c Copyright 2009, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-mips.texi b/binutils-2.25/gas/doc/c-mips.texi index 7927893c..d960022c 100644 --- a/binutils-2.25/gas/doc/c-mips.texi +++ b/binutils-2.25/gas/doc/c-mips.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, -@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -30,6 +28,7 @@ Assembly Language Programming'' in the same work. * MIPS assembly options:: Directives to control code generation * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction +* MIPS FP ABIs:: Marking which FP ABI is in use * MIPS NaN Encodings:: Directives to record which NaN encoding is being used * MIPS Option Stack:: Directives to save and restore options * MIPS ASE Instruction Generation Overrides:: Directives to control @@ -83,17 +82,26 @@ VxWorks-style position-independent macro expansions. @itemx -mips5 @itemx -mips32 @itemx -mips32r2 +@itemx -mips32r3 +@itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 +@itemx -mips64r3 +@itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the R2000 and R3000 processors, @samp{-mips2} to the R6000 processor, @samp{-mips3} to the R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also -switch instruction sets during the assembly; see @ref{MIPS ISA, -Directives to override the ISA level}. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to +generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 +Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 +Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, +respectively. You can also switch instruction sets during the assembly; +see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 @itemx -mfp32 @@ -121,6 +129,22 @@ The @code{.set gp=64} and @code{.set fp=64} directives allow the size of registers to be changed for parts of an object. The default value is restored by @code{.set gp=default} and @code{.set fp=default}. +@item -mfpxx +Make no assumptions about whether 32-bit or 64-bit floating-point +registers are available. This is provided to support having modules +compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can +only be used with MIPS II and above. + +The @code{.set fp=xx} directive allows a part of an object to be marked +as not making assumptions about 32-bit or 64-bit FP registers. The +default value is restored by @code{.set fp=default}. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. @samp{-mfpxx} implies +@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -185,6 +209,12 @@ Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. @samp{-mno-msa} turns off this option. +@item -mxpa +@itemx -mno-xpa +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +@samp{-mno-xpa} turns off this option. + @item -mvirt @itemx -mno-virt Generate code for the Virtualization Application Specific Extension. @@ -206,6 +236,11 @@ selected, allowing all instructions to be used. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-rm7000 +@itemx -mno-fix-rm7000 +Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. + @item -mfix-loongson2f-jump @itemx -mno-fix-loongson2f-jump Eliminate instruction fetch from outside 256M region to work around the @@ -334,6 +369,7 @@ m14kec, 1004kf2_1, 1004kf, 1004kf1_1, +p5600, 5kc, 5kf, 20kc, @@ -642,8 +678,8 @@ Small data is not supported for SVR4-style PIC. @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 -or 64r2. +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, +32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions @@ -677,6 +713,20 @@ Traditional MIPS assemblers do not support this directive. @node MIPS assembly options @section Directives to control code generation +@cindex MIPS directives to override command line options +@kindex @code{.module} +The @code{.module} directive allows command line options to be set directly +from assembly. The format of the directive matches the @code{.set} +directive but only those options which are relevant to a whole module are +supported. The effect of a @code{.module} directive is the same as the +corresponding command line option. Where @code{.set} directives support +returning to a default then the @code{.module} directives do not as they +define the defaults. + +These module-level directives must appear first in assembly. + +Traditional MIPS assemblers do not support this directive. + @cindex MIPS 32-bit microMIPS instruction generation override @kindex @code{.set insn32} @kindex @code{.set noinsn32} @@ -719,9 +769,9 @@ The @code{.global} and @code{.globl} directives supported by region of data not code. This means that, for example, any instructions following such a symbol will not be disassembled by @code{objdump} as it will regard them as data. To change this -behaviour an optional section name can be placed after the symbol name +behavior an optional section name can be placed after the symbol name in the @code{.global} directive. If this section exists and is known -to be a code section, then the symbol will be marked as poiting at +to be a code section, then the symbol will be marked as pointing at code not data. Ie the syntax for the directive is: @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, @@ -739,6 +789,115 @@ baz: @end example +@node MIPS FP ABIs +@section Directives to control the FP ABI +@menu +* MIPS FP ABI History:: History of FP ABIs +* MIPS FP ABI Variants:: Supported FP ABIs +* MIPS FP ABI Selection:: Automatic selection of FP ABI +* MIPS FP ABI Compatibility:: Linking different FP ABI variants +@end menu + +@node MIPS FP ABI History +@subsection History of FP ABIs +@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS +@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS +The MIPS ABIs support a variety of different floating-point extensions +where calling-convention and register sizes vary for floating-point data. +The extensions exist to support a wide variety of optional architecture +features. The resulting ABI variants are generally incompatible with each +other and must be tracked carefully. + +Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} +directive is used to indicate which ABI is in use by a specific module. +It was then left to the user to ensure that command line options and the +selected ABI were compatible with some potential for inconsistencies. + +@node MIPS FP ABI Variants +@subsection Supported FP ABIs +The supported floating-point ABI variants are: + +@table @code +@item 0 - No floating-point +This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. + +@item 1 - Double-precision +This variant indicates that double-precision support is used. For 64-bit +ABIs this means that 64-bit wide floating-point registers are required. +For 32-bit ABIs this means that 32-bit wide floating-point registers are +required and double-precision operations use pairs of registers. + +@item 2 - Single-precision +This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. + +@item 3 - Soft-float +This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. + +@item 4 - Deprecated +This variant existed as an initial attempt at supporting 64-bit wide +floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been +superseded by 5, 6 and 7. + +@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module has been designed to operate correctly with either +32-bit wide or 64-bit wide floating-point registers. Double-precision +support is used. Only O32 currently supports this variant and requires +a minimum architecture of MIPS II. + +@item 6 - Double-precision 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. Only O32 currently supports this +variant and requires a minimum architecture of MIPS32r2. + +@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. This differs from the previous ABI +as it restricts use of odd-numbered single-precision registers. Only +O32 currently supports this variant and requires a minimum architecture +of MIPS32r2. +@end table + +@node MIPS FP ABI Selection +@subsection Automatic selection of FP ABI +@cindex @code{.module fp=@var{nn}} directive, MIPS +In order to simplify and add safety to the process of selecting the +correct floating-point ABI, the assembler will automatically infer the +correct @code{.gnu_attribute 4, @var{n}} directive based on command line +options and @code{.module} overrides. Where an explicit +@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning +will be raised if it does not match an inferred setting. + +The floating-point ABI is inferred as follows. If @samp{-msoft-float} +has been used the module will be marked as soft-float. If +@samp{-msingle-float} has been used then the module will be marked as +single-precision. The remaining ABIs are then selected based +on the FP register width. Double-precision is selected if the width +of GP and FP registers match and the special double-precision variants +for 32-bit ABIs are then selected depending on @samp{-mfpxx}, +@samp{-mfp64} and @samp{-mno-odd-spreg}. + +@node MIPS FP ABI Compatibility +@subsection Linking different FP ABI variants +Modules using the default FP ABI (no floating-point) can be linked with +any other (singular) FP ABI variant. + +Special compatibility support exists for O32 with the four +double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically +designed to be compatible with the standard double-precision ABI and the +@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be +built as @samp{-mfpxx} to ensure the maximum compatibility with other +modules produced for more specific needs. The only FP ABIs which cannot +be linked together are the standard double-precision ABI and the full +@samp{-mfp64} ABI with @samp{-modd-spreg}. + @node MIPS NaN Encodings @section Directives to record which NaN encoding is being used @@ -839,7 +998,7 @@ Release 1 instructions from being accepted. @kindex @code{.set nodspr2} The directive @code{.set dspr2} makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point -on in the assembly. This dirctive implies @code{.set dsp}. The +on in the assembly. This directive implies @code{.set dsp}. The @code{.set nodspr2} directive prevents DSP Release 2 instructions from being accepted. @@ -875,6 +1034,13 @@ from the Virtualization Application Specific Extension from that point on in the assembly. The @code{.set novirt} directive prevents Virtualization instructions from being accepted. +@cindex MIPS eXtended Physical Address (XPA) instruction generation override +@kindex @code{.set xpa} +@kindex @code{.set noxpa} +The directive @code{.set xpa} makes the assembler accept instructions +from the XPA Extension from that point on in the assembly. The +@code{.set noxpa} directive prevents XPA instructions from being accepted. + Traditional MIPS assemblers do not support these directives. @node MIPS Floating-Point diff --git a/binutils-2.25/gas/doc/c-mmix.texi b/binutils-2.25/gas/doc/c-mmix.texi index 009f9d3e..24d242c4 100644 --- a/binutils-2.25/gas/doc/c-mmix.texi +++ b/binutils-2.25/gas/doc/c-mmix.texi @@ -1,4 +1,4 @@ -@c Copyright 2001, 2002, 2003, 2006, 2011 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c MMIX description by Hans-Peter Nilsson, hp@bitrange.com diff --git a/binutils-2.25/gas/doc/c-msp430.texi b/binutils-2.25/gas/doc/c-msp430.texi index 2927add4..cae3d8a6 100644 --- a/binutils-2.25/gas/doc/c-msp430.texi +++ b/binutils-2.25/gas/doc/c-msp430.texi @@ -1,4 +1,4 @@ -@c Copyright 2002-2013 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -29,13 +29,12 @@ @table @code @item -mmcu -selects the mpu arch. If the architecture is 430Xv2 then this also -enables NOP generation unless the @option{-mN} is also specified. +selects the mcu architecture. If the architecture is 430Xv2 then this +also enables NOP generation unless the @option{-mN} is also specified. @item -mcpu selects the cpu architecture. If the architecture is 430Xv2 then this -also enables NOP generation unless the @option{-mN} is also -specified. +also enables NOP generation unless the @option{-mN} is also specified. @item -mP enables polymorph instructions handler. @@ -46,16 +45,33 @@ enables relaxation at assembly time. DANGEROUS! @item -ml indicates that the input uses the large code model. +@item -mn +enables the generation of a NOP instruction following any instruction +that might change the interrupts enabled/disabled state. The +pipelined nature of the MSP430 core means that any instruction that +changes the interrupt state (@code{EINT}, @code{DINT}, @code{BIC #8, +SR}, @code{BIS #8, SR} or @code{MOV.W <>, SR}) must be +followed by a NOP instruction in order to ensure the correct +processing of interrupts. By default it is up to the programmer to +supply these NOP instructions, but this command line option enables +the automatic insertion by the assembler, if they are missing. + @item -mN disables the generation of a NOP instruction following any instruction -that might change the interrupts enabled/disabled state. For the -430Xv2 architecture the instructions: @code{EINT}, @code{DINT}, -@code{BIC #8, SR}, @code{BIS #8, SR} and @code{MOV.W <>, SR} must be -followed by a NOP instruction in order to ensure the correct -processing of interrupts. By default generation of the NOP -instruction happens automatically, but this command line option -disables this behaviour. It is then up to the programmer to ensure -that interrupts are enabled and disabled correctly. +that might change the interrupts enabled/disabled state. This is the +default behaviour. + +@item -my +tells the assembler to generate a warning message if a NOP does not +immediately forllow an instruction that enables or disables +interrupts. This is the default. + +Note that this option can be stacked with the @option{-mn} option so +that the assembler will both warn about missing NOP instructions and +then insert them automatically. + +@item -mY +disables warnings about missing NOP instructions. @item -md mark the object file as one that requires data to copied from ROM to @@ -254,6 +270,15 @@ command line option. @item .profiler This directive instructs assembler to add new profile entry to the object file. +@cindex @code{refsym} directive, MSP 430 +@item .refsym +This directive instructs assembler to add an undefined reference to +the symbol following the directive. The maximum symbol name length is +1023 characters. No relocation is created for this symbol; it will +exist purely for pulling in object files from archives. Note that +this reloc is not sufficient to prevent garbage collection; use a +KEEP() directive in the linker file to preserve such objects. + @end table @node MSP430 Opcodes diff --git a/binutils-2.25/gas/doc/c-mt.texi b/binutils-2.25/gas/doc/c-mt.texi index 02843f2c..f6ee21d8 100644 --- a/binutils-2.25/gas/doc/c-mt.texi +++ b/binutils-2.25/gas/doc/c-mt.texi @@ -1,5 +1,4 @@ -@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 -@c Free Software Foundation, Inc. +@c Copyright (C) 1996-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-nds32.texi b/binutils-2.25/gas/doc/c-nds32.texi new file mode 100644 index 00000000..21f3b829 --- /dev/null +++ b/binutils-2.25/gas/doc/c-nds32.texi @@ -0,0 +1,299 @@ +@c Copyright (C) 2013-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end + +@ifset GENERIC +@page +@node NDS32-Dependent +@chapter NDS32 Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter NDS32 Dependent Features +@end ifclear + +@cindex NDS32 processor +The NDS32 processors family includes high-performance and low-power 32-bit +processors for high-end to low-end. @sc{gnu} @code{@value{AS}} for NDS32 +architectures supports NDS32 ISA version 3. For detail about NDS32 +instruction set, please see the AndeStar ISA User Manual which is availible +at http://www.andestech.com/en/index/index.htm + +@menu +* NDS32 Options:: Assembler options +* NDS32 Syntax:: High-level assembly macros +@end menu + +@node NDS32 Options +@section NDS32 Options + +@cindex NDS32 options +@cindex options for NDS32 +The NDS32 configurations of @sc{gnu} @code{@value{AS}} support these +special options: + +@c man begin OPTIONS +@table @code + +@item -O1 +Optimize for performance. + +@item -Os +Optimize for space. + +@item -EL +Produce little endian data output. + +@item -EB +Produce little endian data output. + +@item -mpic +Generate PIC. + +@item -mno-fp-as-gp-relax +Suppress fp-as-gp relaxation for this file. + +@item -mb2bb-relax +Back-to-back branch optimization. + +@item -mno-all-relax +Suppress all relaxation for this file. + +@item -march=<arch name> +Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, +v3s, v2, v2j, v2f, v2s. + +@item -mbaseline=<baseline> +Assemble for baseline <baseline> which could be v2, v3, v3m. + +@item -mfpu-freg=@var{FREG} +Specify a FPU configuration. +@table @code +@item 0 8 SP / 4 DP registers +@item 1 16 SP / 8 DP registers +@item 2 32 SP / 16 DP registers +@item 3 32 SP / 32 DP registers +@end table + +@item -mabi=@var{abi} +Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. + +@item -m[no-]mac +Enable/Disable Multiply instructions support. + +@item -m[no-]div +Enable/Disable Divide instructions support. + +@item -m[no-]16bit-ext +Enable/Disable 16-bit extension + +@item -m[no-]dx-regs +Enable/Disable d0/d1 registers + +@item -m[no-]perf-ext +Enable/Disable Performance extension + +@item -m[no-]perf2-ext +Enable/Disable Performance extension 2 + +@item -m[no-]string-ext +Enable/Disable String extension + +@item -m[no-]reduced-regs +Enable/Disable Reduced Register configuration (GPR16) option + +@item -m[no-]audio-isa-ext +Enable/Disable AUDIO ISA extension + +@item -m[no-]fpu-sp-ext +Enable/Disable FPU SP extension + +@item -m[no-]fpu-dp-ext +Enable/Disable FPU DP extension + +@item -m[no-]fpu-fma +Enable/Disable FPU fused-multiply-add instructions + +@item -mall-ext +Turn on all extensions and instructions support +@end table +@c man end + +@node NDS32 Syntax +@section Syntax + +@menu +* NDS32-Chars:: Special Characters +* NDS32-Regs:: Register Names +* NDS32-Ops:: Pseudo Instructions +@end menu + +@node NDS32-Chars +@subsection Special Characters + +Use @samp{#} at column 1 and @samp{!} anywhere in the line except inside +quotes. + +Multiple instructions in a line are allowed though not recommended and +should be separated by @samp{;}. + +Assembler is not case-sensitive in general except user defined label. +For example, @samp{jral F1} is different from @samp{jral f1} while it is +the same as @samp{JRAL F1}. + +@node NDS32-Regs +@subsection Register Names +@table @code +@item General purpose registers (GPR) +There are 32 32-bit general purpose registers $r0 to $r31. + +@item Accumulators d0 and d1 +64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. + +@item Assembler reserved register $ta +Register $ta ($r15) is reserved for assembler using. + +@item Operating system reserved registers $p0 and $p1 +Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch +registers. + +@item Frame pointer $fp +Register $r28 is regarded as the frame pointer. + +@item Global pointer +Register $r29 is regarded as the global pointer. + +@item Link pointer +Register $r30 is regarded as the link pointer. + +@item Stack pointer +Register $r31 is regarded as the stack pointer. +@end table + +@node NDS32-Ops +@subsection Pseudo Instructions +@table @code +@item li rt5,imm32 +load 32-bit integer into register rt5. @samp{sethi rt5,hi20(imm32)} and then +@samp{ori rt5,reg,lo12(imm32)}. + +@item la rt5,var +Load 32-bit address of var into register rt5. @samp{sethi rt5,hi20(var)} and +then @samp{ori reg,rt5,lo12(var)} + +@item l.[bhw] rt5,var +Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then +@samp{l[bhw]i rt5,[$ta+lo12(var)]} + +@item l.[bh]s rt5,var +Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then +@samp{l[bh]si rt5,[$ta+lo12(var)]} + +@item l.[bhw]p rt5,var,inc +Load value of var into register rt5 and increment $ta by amount inc. +@samp{la $ta,var} and then @samp{l[bhw]i.bi rt5,[$ta],inc} + +@item l.[bhw]pc rt5,inc +Continue loading value of var into register rt5 and increment $ta by amount inc. +@samp{l[bhw]i.bi rt5,[$ta],inc.} + +@item l.[bh]sp rt5,var,inc +Load value of var into register rt5 and increment $ta by amount inc. +@samp{la $ta,var} and then @samp{l[bh]si.bi rt5,[$ta],inc} + +@item l.[bh]spc rt5,inc +Continue loading value of var into register rt5 and increment $ta by amount inc. +@samp{l[bh]si.bi rt5,[$ta],inc.} + +@item s.[bhw] rt5,var +Store register rt5 to var. +@samp{sethi $ta,hi20(var)} and then @samp{s[bhw]i rt5,[$ta+lo12(var)]} + +@item s.[bhw]p rt5,var,inc +Store register rt5 to var and increment $ta by amount inc. +@samp{la $ta,var} and then @samp{s[bhw]i.bi rt5,[$ta],inc} + +@item s.[bhw]pc rt5,inc +Continue storing register rt5 to var and increment $ta by amount inc. +@samp{s[bhw]i.bi rt5,[$ta],inc.} + +@item not rt5,ra5 +Alias of @samp{nor rt5,ra5,ra5}. + +@item neg rt5,ra5 +Alias of @samp{subri rt5,ra5,0}. + +@item br rb5 +Depending on how it is assembled, it is translated into @samp{r5 rb5} +or @samp{jr rb5}. + +@item b label +Branch to label depending on how it is assembled, it is translated into +@samp{j8 label}, @samp{j label}, or "@samp{la $ta,label} @samp{br $ta}". + +@item bral rb5 +Alias of jral br5 depending on how it is assembled, it is translated +into @samp{jral5 rb5} or @samp{jral rb5}. + +@item bal fname +Alias of jal fname depending on how it is assembled, it is translated into +@samp{jal fname} or "@samp{la $ta,fname} @samp{bral $ta}". + +@item call fname +Call function fname same as @samp{jal fname}. + +@item move rt5,ra5 +For 16-bit, this is @samp{mov55 rt5,ra5}. +For no 16-bit, this is @samp{ori rt5,ra5,0}. + +@item move rt5,var +This is the same as @samp{l.w rt5,var}. + +@item move rt5,imm32 +This is the same as @samp{li rt5,imm32}. + +@item pushm ra5,rb5 +Push contents of registers from ra5 to rb5 into stack. + +@item push ra5 +Push content of register ra5 into stack. (same @samp{pushm ra5,ra5}). + +@item push.d var +Push value of double-word variable var into stack. + +@item push.w var +Push value of word variable var into stack. + +@item push.h var +Push value of half-word variable var into stack. + +@item push.b var +Push value of byte variable var into stack. + +@item pusha var +Push 32-bit address of variable var into stack. + +@item pushi imm32 +Push 32-bit immediate value into stack. + +@item popm ra5,rb5 +Pop top of stack values into registers ra5 to rb5. + +@item pop rt5 +Pop top of stack value into register. (same as @samp{popm rt5,rt5}.) + +@item pop.d var,ra5 +Pop value of double-word variable var from stack using register ra5 +as 2nd scratch register. (1st is $ta) + +@item pop.w var,ra5 +Pop value of word variable var from stack using register ra5. + +@item pop.h var,ra5 +Pop value of half-word variable var from stack using register ra5. + +@item pop.b var,ra5 +Pop value of byte variable var from stack using register ra5. + +@end table diff --git a/binutils-2.25/gas/doc/c-nios2.texi b/binutils-2.25/gas/doc/c-nios2.texi index 1d45dd20..e2aa125f 100644 --- a/binutils-2.25/gas/doc/c-nios2.texi +++ b/binutils-2.25/gas/doc/c-nios2.texi @@ -1,4 +1,4 @@ -@c Copyright 2012, 2013 Free Software Foundation, Inc. +@c Copyright (C) 2012-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end @@ -131,7 +131,11 @@ fastint: @end smallexample @cindex @code{call} directive, Nios II +@cindex @code{call_lo} directive, Nios II +@cindex @code{call_hiadj} directive, Nios II @cindex @code{got} directive, Nios II +@cindex @code{got_lo} directive, Nios II +@cindex @code{got_hiadj} directive, Nios II @cindex @code{gotoff} directive, Nios II @cindex @code{gotoff_lo} directive, Nios II @cindex @code{gotoff_hiadj} directive, Nios II @@ -141,7 +145,11 @@ fastint: @cindex @code{tls_ldm} directive, Nios II @cindex @code{tls_ldo} directive, Nios II @item %call(@var{expression}) +@item %call_lo(@var{expression}) +@item %call_hiadj(@var{expression}) @itemx %got(@var{expression}) +@itemx %got_lo(@var{expression}) +@itemx %got_hiadj(@var{expression}) @itemx %gotoff(@var{expression}) @itemx %gotoff_lo(@var{expression}) @itemx %gotoff_hiadj(@var{expression}) diff --git a/binutils-2.25/gas/doc/c-ns32k.texi b/binutils-2.25/gas/doc/c-ns32k.texi index 7b6544cc..c2b8e536 100644 --- a/binutils-2.25/gas/doc/c-ns32k.texi +++ b/binutils-2.25/gas/doc/c-ns32k.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 2002 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-pdp11.texi b/binutils-2.25/gas/doc/c-pdp11.texi index c5e0c3de..62ed9d51 100644 --- a/binutils-2.25/gas/doc/c-pdp11.texi +++ b/binutils-2.25/gas/doc/c-pdp11.texi @@ -1,4 +1,4 @@ -@c Copyright 2001, 2002, 2006 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-pj.texi b/binutils-2.25/gas/doc/c-pj.texi index dcf32ab9..e124caec 100644 --- a/binutils-2.25/gas/doc/c-pj.texi +++ b/binutils-2.25/gas/doc/c-pj.texi @@ -1,4 +1,4 @@ -@c Copyright 1999, 2002, 2011 Free Software Foundation, Inc. +@c Copyright (C) 1999-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @page diff --git a/binutils-2.25/gas/doc/c-ppc.texi b/binutils-2.25/gas/doc/c-ppc.texi index c2209edc..c457a507 100644 --- a/binutils-2.25/gas/doc/c-ppc.texi +++ b/binutils-2.25/gas/doc/c-ppc.texi @@ -1,5 +1,4 @@ -@c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -@c 2012 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-rl78.texi b/binutils-2.25/gas/doc/c-rl78.texi index 0964ac45..a7145482 100644 --- a/binutils-2.25/gas/doc/c-rl78.texi +++ b/binutils-2.25/gas/doc/c-rl78.texi @@ -1,4 +1,4 @@ -@c Copyright 2011-2013 Free Software Foundation, Inc. +@c Copyright (C) 2011-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -32,6 +32,14 @@ Enable support for link-time relaxation. Mark the generated binary as targeting the G10 variant of the RL78 architecture. +@item m32bit-doubles +Mark the generated binary as one that uses 32-bits to hold the +@code{double} floating point type. This is the default. + +@item m64bit-doubles +Mark the generated binary as one that uses 64-bits to hold the +@code{double} floating point type. + @end table @node RL78-Modifiers @@ -85,8 +93,10 @@ In addition to the common directives, the RL78 adds these: @table @code @item .double -Output a constant in ``double'' format, which is a 32-bit floating -point value on RL78. +Output a constant in ``double'' format, which is either a 32-bit +or a 64-bit floating point value, depending upon the setting of the +@option{-m32bit-doubles}|@option{-m64bit-doubles} command line +option. @item .bss Select the BSS section. diff --git a/binutils-2.25/gas/doc/c-rx.texi b/binutils-2.25/gas/doc/c-rx.texi index 2b3ab396..5f24fd33 100644 --- a/binutils-2.25/gas/doc/c-rx.texi +++ b/binutils-2.25/gas/doc/c-rx.texi @@ -1,4 +1,4 @@ -@c Copyright 2008-2013 Free Software Foundation, Inc. +@c Copyright (C) 2008-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-s390.texi b/binutils-2.25/gas/doc/c-s390.texi index 1935fb3e..a4fdf4a3 100644 --- a/binutils-2.25/gas/doc/c-s390.texi +++ b/binutils-2.25/gas/doc/c-s390.texi @@ -1,5 +1,4 @@ -@c Copyright 2009, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-score.texi b/binutils-2.25/gas/doc/c-score.texi index 8335ae79..73dee164 100644 --- a/binutils-2.25/gas/doc/c-score.texi +++ b/binutils-2.25/gas/doc/c-score.texi @@ -1,5 +1,4 @@ -@c Copyright 2009, 2011, 2013 -@c Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-sh.texi b/binutils-2.25/gas/doc/c-sh.texi index 967cea4b..8e58282f 100644 --- a/binutils-2.25/gas/doc/c-sh.texi +++ b/binutils-2.25/gas/doc/c-sh.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, -@c 2005, 2008, 2010, 2011, 2012 Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @page diff --git a/binutils-2.25/gas/doc/c-sh64.texi b/binutils-2.25/gas/doc/c-sh64.texi index 6857f29e..7ccb2855 100644 --- a/binutils-2.25/gas/doc/c-sh64.texi +++ b/binutils-2.25/gas/doc/c-sh64.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2002, 2003, 2008, 2011, 2012 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @page diff --git a/binutils-2.25/gas/doc/c-sparc.texi b/binutils-2.25/gas/doc/c-sparc.texi index f6b98150..6036766a 100644 --- a/binutils-2.25/gas/doc/c-sparc.texi +++ b/binutils-2.25/gas/doc/c-sparc.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008, -@c 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -62,7 +60,9 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite. @kindex -Av9b @kindex -Av9c @kindex -Av9d +@kindex -Av9e @kindex -Av9v +@kindex -Av9m @kindex -Asparc @kindex -Asparcvis @kindex -Asparcvis2 @@ -72,7 +72,7 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite. @kindex -Asparcvis3r @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv -@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v +@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima @itemx -Asparcvis3 | -Asparcvis3r Use one of the @samp{-A} options to select one of the SPARC @@ -83,9 +83,10 @@ or feature requiring an incompatible or higher level. @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc}, @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment. -@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and -@samp{-Av9v} select a 64 bit environment and are not available unless GAS -is explicitly configured with 64 bit environment support. +@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, +@samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit +environment and are not available unless GAS is explicitly configured +with 64 bit environment support. @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions. @@ -100,10 +101,17 @@ as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}. multiply-add, VIS 3.0, and HPC extension instructions, as well as the instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}. -@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional -memory, floating point unfused multiply-add, integer multiply-add, and -cache sparing store instructions, as well as the instructions enabled -by @samp{-Av8plusd} and @samp{-Av9d}. +@samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic +instructions, as well as the instructions enabled by @samp{-Av8plusd} +and @samp{-Av9d}. + +@samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused +multiply-add, and integer multiply-add, as well as the instructions +enabled by @samp{-Av8pluse} and @samp{-Av9e}. + +@samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended, +xmpmul, xmontmul and xmontsqr instructions, as well as the instructions +enabled by @samp{-Av8plusv} and @samp{-Av9v}. @samp{-Asparc} specifies a v9 environment. It is equivalent to @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise. @@ -123,21 +131,22 @@ multiply-add instructions enabled. @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled. -@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, -HPC, transactional memory, random, and floating point unfused multiply-add -instructions enabled. +@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC, +and floating point unfused multiply-add instructions enabled. + +@samp{-Asparc5} is equivalent to @samp{-Av9m}. @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a -@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v +@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3 -@itemx -xarch=sparcvis3r +@itemx -xarch=sparcvis3r | -xarch=sparc5 For compatibility with the SunOS v9 assembler. These options are equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, --Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis, --Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r, -respectively. +-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m, +-Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, +-Asparcvis3, and -Asparcvis3r, respectively. @item -bump Warn whenever it is necessary to switch to another level. @@ -409,9 +418,17 @@ The hyperprivileged implementation version register is referred to as @samp{%hver}. @item +The hyperprivileged system tick offset register is referred to as +@samp{%hstick_offset}. Note that there is no @samp{%hstick} register, +the normal @samp{%stick} is used. + +@item +The hyperprivileged system tick enable register is referred to as +@samp{%hstick_enable}. + +@item The hyperprivileged system tick compare register is referred -to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick} -register, the normal @samp{%stick} is used. +to as @samp{%hstick_cmpr}. @end itemize @node Sparc-Constants diff --git a/binutils-2.25/gas/doc/c-tic54x.texi b/binutils-2.25/gas/doc/c-tic54x.texi index 8a373169..50b3611a 100644 --- a/binutils-2.25/gas/doc/c-tic54x.texi +++ b/binutils-2.25/gas/doc/c-tic54x.texi @@ -1,4 +1,4 @@ -@c Copyright 2000-2013 Free Software Foundation, Inc. +@c Copyright (C) 2000-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c TI TMS320C54X description by Timothy Wall, twall@cygnus.com diff --git a/binutils-2.25/gas/doc/c-tic6x.texi b/binutils-2.25/gas/doc/c-tic6x.texi index a39a9a71..cd449883 100644 --- a/binutils-2.25/gas/doc/c-tic6x.texi +++ b/binutils-2.25/gas/doc/c-tic6x.texi @@ -1,4 +1,4 @@ -@c Copyright 2010, 2011 Free Software Foundation, Inc. +@c Copyright (C) 2010-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-tilegx.texi b/binutils-2.25/gas/doc/c-tilegx.texi index 0d8c038b..528ae7fd 100644 --- a/binutils-2.25/gas/doc/c-tilegx.texi +++ b/binutils-2.25/gas/doc/c-tilegx.texi @@ -1,5 +1,4 @@ -@c Copyright 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2011-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end diff --git a/binutils-2.25/gas/doc/c-tilepro.texi b/binutils-2.25/gas/doc/c-tilepro.texi index 5d80c4f0..a8989ab1 100644 --- a/binutils-2.25/gas/doc/c-tilepro.texi +++ b/binutils-2.25/gas/doc/c-tilepro.texi @@ -1,5 +1,4 @@ -@c Copyright 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2011-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-v850.texi b/binutils-2.25/gas/doc/c-v850.texi index 2516a838..7fe3719a 100644 --- a/binutils-2.25/gas/doc/c-v850.texi +++ b/binutils-2.25/gas/doc/c-v850.texi @@ -1,4 +1,4 @@ -@c Copyright 1997-2013 Free Software Foundation, Inc. +@c Copyright (C) 1997-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-vax.texi b/binutils-2.25/gas/doc/c-vax.texi index 9eacd10d..1df7453e 100644 --- a/binutils-2.25/gas/doc/c-vax.texi +++ b/binutils-2.25/gas/doc/c-vax.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2002, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c VAX/VMS description enhanced and corrected by Klaus K"aempf, kkaempf@progis.de diff --git a/binutils-2.25/gas/doc/c-xc16x.texi b/binutils-2.25/gas/doc/c-xc16x.texi index 9589139c..fd5ff7ff 100644 --- a/binutils-2.25/gas/doc/c-xc16x.texi +++ b/binutils-2.25/gas/doc/c-xc16x.texi @@ -1,4 +1,4 @@ -@c Copyright 2006, 2011 Free Software Foundation, Inc. +@c Copyright (C) 2006-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-xgate.texi b/binutils-2.25/gas/doc/c-xgate.texi index 360554fd..46b94804 100644 --- a/binutils-2.25/gas/doc/c-xgate.texi +++ b/binutils-2.25/gas/doc/c-xgate.texi @@ -1,5 +1,4 @@ -@c Copyright 2012 -@c Free Software Foundation, Inc. +@c Copyright (C) 2012-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/c-xstormy16.texi b/binutils-2.25/gas/doc/c-xstormy16.texi index 31ba6f96..5196537d 100644 --- a/binutils-2.25/gas/doc/c-xstormy16.texi +++ b/binutils-2.25/gas/doc/c-xstormy16.texi @@ -1,4 +1,4 @@ -@c Copyright 2010, 2011 Free Software Foundation, Inc. +@c Copyright (C) 2010-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-xtensa.texi b/binutils-2.25/gas/doc/c-xtensa.texi index bf5b38b0..e763e368 100644 --- a/binutils-2.25/gas/doc/c-xtensa.texi +++ b/binutils-2.25/gas/doc/c-xtensa.texi @@ -1,5 +1,4 @@ -@c Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c @@ -92,6 +91,16 @@ instruction operands to be errors. @kindex --rename-section Rename the @var{oldname} section to @var{newname}. This option can be used multiple times to rename multiple sections. + +@item --trampolines | --no-trampolines +@kindex --trampolines +@kindex --no-trampolines +Enable or disable transformation of jump instructions to allow jumps +across a greater range of addresses. @xref{Xtensa Jump Relaxation, +,Jump Trampolines}. This option should be used when jump targets can +potentially be out of range. In the absence of such jumps this option +does not affect code size or performance. The default is +@samp{--trampolines}. @end table @c man end @@ -312,6 +321,7 @@ fields. @menu * Xtensa Branch Relaxation:: Relaxation of Branches. * Xtensa Call Relaxation:: Relaxation of Function Calls. +* Xtensa Jump Relaxation:: Relaxation of Jumps. * Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. @end menu @@ -399,6 +409,87 @@ and some of the calls are out of range, function call relaxation can be enabled using the @samp{--longcalls} command-line option or the @code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}). +@node Xtensa Jump Relaxation +@subsection Jump Relaxation +@cindex relaxation of jump instructions +@cindex jump instructions, relaxation + +Jump instruction may require relaxation because the Xtensa jump instruction +(@code{J}) provide a PC-relative offset of only 128 Kbytes in either +direction. One option is to use jump long (@code{J.L}) instruction, which +depending on jump distance may be assembled as jump (@code{J}) or indirect +jump (@code{JX}). However it needs a free register. When there's no spare +register it is possible to plant intermediate jump sites (trampolines) +between the jump instruction and its target. These sites may be located in +areas unreachable by normal code execution flow, in that case they only +contain intermediate jumps, or they may be inserted in the middle of code +block, in which case there's an additional jump from the beginning of the +trampoline to the instruction past its end. So, for example: + +@smallexample +@group + j 1f + ... + retw + ... + mov a10, a2 + call8 func + ... +1: + ... +@end group +@end smallexample + +might be relaxed to: + +@smallexample +@group + j .L0_TR_1 + ... + retw +.L0_TR_1: + j 1f + ... + mov a10, a2 + call8 func + ... +1: + ... +@end group +@end smallexample + +or to: + +@smallexample +@group + j .L0_TR_1 + ... + retw + ... + mov a10, a2 + j .L0_TR_0 +.L0_TR_1: + j 1f +.L0_TR_0: + call8 func + ... +1: + ... +@end group +@end smallexample + +The Xtensa assempler uses trampolines with jump around only when it cannot +find suitable unreachable trampoline. There may be multiple trampolines +between the jump instruction and its target. + +This relaxation does not apply to jumps to undefined symbols, assuming they +will reach their targets once resolved. + +Jump relaxation is enabled by default because it does not affect code size +or performance while the code itself is small. This relaxation may be +disabled completely with @samp{--no-trampolines} or @samp{--no-transform} +command-line options (@pxref{Xtensa Options, ,Command Line Options}). + @node Xtensa Immediate Relaxation @subsection Other Immediate Field Relaxation @cindex immediate fields, relaxation diff --git a/binutils-2.25/gas/doc/c-z80.texi b/binutils-2.25/gas/doc/c-z80.texi index df5a65fc..4e1f91c0 100644 --- a/binutils-2.25/gas/doc/c-z80.texi +++ b/binutils-2.25/gas/doc/c-z80.texi @@ -1,4 +1,4 @@ -@c Copyright 2011 Free Software Foundation, Inc. +@c Copyright (C) 2011-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/c-z8k.texi b/binutils-2.25/gas/doc/c-z8k.texi index 51f00e12..bc201502 100644 --- a/binutils-2.25/gas/doc/c-z8k.texi +++ b/binutils-2.25/gas/doc/c-z8k.texi @@ -1,5 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 2003, 2011 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC diff --git a/binutils-2.25/gas/doc/h8.texi b/binutils-2.25/gas/doc/h8.texi index 2b9e9dd3..59e51350 100644 --- a/binutils-2.25/gas/doc/h8.texi +++ b/binutils-2.25/gas/doc/h8.texi @@ -1,5 +1,4 @@ -@c Copyright 2012 -@c Free Software Foundation, Inc. +@c Copyright (C) 2012-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. diff --git a/binutils-2.25/gas/doc/internals.texi b/binutils-2.25/gas/doc/internals.texi index cf15fb51..cc4089bc 100644 --- a/binutils-2.25/gas/doc/internals.texi +++ b/binutils-2.25/gas/doc/internals.texi @@ -1,7 +1,5 @@ \input texinfo -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @setfilename internals.info @node Top @top Assembler Internals @@ -732,7 +730,7 @@ all the fixups (@code{fixup_segment}), resolves all the symbol values (using @cindex porting Each GAS target specifies two main things: the CPU file and the object format -file. Two main switches in the @file{configure.in} file handle this. The +file. Two main switches in the @file{configure.ac} file handle this. The first switches on CPU type to set the shell variable @code{cpu_type}. The second switches on the entire target to set the shell variable @code{fmt}. @@ -886,6 +884,8 @@ comment. @item tc_comment_chars @cindex tc_comment_chars If this macro is defined, GAS will use it instead of @code{comment_chars}. +This has the advantage that this macro does not have to refer to a constant +array. @item tc_symbol_chars @cindex tc_symbol_chars @@ -910,6 +910,13 @@ listed in this array). Note that line_separator_chars do not separate lines if found in a comment, such as after a character in line_comment_chars or comment_chars. +@item tc_line_separator_chars +@cindex tc_line_separator_chars +If this macro is defined, GAS will use it instead of +@code{line_separator_chars}. This has the advantage that this macro does not +have to refer to a constant array. + + @item EXP_CHARS @cindex EXP_CHARS This is a null terminated @code{const char} array of characters which may be |