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Diffstat (limited to 'binutils-2.25/gas/doc/c-aarch64.texi')
| -rw-r--r-- | binutils-2.25/gas/doc/c-aarch64.texi | 105 |
1 files changed, 92 insertions, 13 deletions
diff --git a/binutils-2.25/gas/doc/c-aarch64.texi b/binutils-2.25/gas/doc/c-aarch64.texi index 60190063..8fbae061 100644 --- a/binutils-2.25/gas/doc/c-aarch64.texi +++ b/binutils-2.25/gas/doc/c-aarch64.texi @@ -1,4 +1,4 @@ -@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c Contributed by ARM Ltd. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -16,9 +16,9 @@ @end ifclear @cindex AArch64 support -@cindex Thumb support @menu * AArch64 Options:: Options +* AArch64 Extensions:: Extensions * AArch64 Syntax:: Syntax * AArch64 Floating Point:: Floating Point * AArch64 Directives:: AArch64 Machine Directives @@ -34,25 +34,104 @@ @c man begin OPTIONS @table @gcctabopt -@cindex @code{-EB} command line option, AArch64 +@cindex @option{-EB} command line option, AArch64 @item -EB This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -@cindex @code{-EL} command line option, AArch64 +@cindex @option{-EL} command line option, AArch64 @item -EL This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. -@cindex @code{-mabi=} command line option, AArch64 +@cindex @option{-mabi=} command line option, AArch64 @item -mabi=@var{abi} Specify which ABI the source code uses. The recognized arguments are: @code{ilp32} and @code{lp64}, which decides the generated object file in ELF32 and ELF64 format respectively. The default is @code{lp64}. +@cindex @option{-mcpu=} command line option, AArch64 +@item -mcpu=@var{processor}[+@var{extension}@dots{}] +This option specifies the target processor. The assembler will issue an error +message if an attempt is made to assemble an instruction which will not execute +on the target processor. The following processor names are recognized: +@code{cortex-a53}, +@code{cortex-a57}, +@code{xgene1}, +and +@code{xgene2}. +The special name @code{all} may be used to allow the assembler to accept +instructions valid for any supported processor, including all optional +extensions. + +In addition to the basic instruction set, the assembler can be told to +accept, or restrict, various extension mnemonics that extend the +processor. @xref{AArch64 Extensions}. + +If some implementations of a particular processor can have an +extension, then then those extensions are automatically enabled. +Consequently, you will not normally have to specify any additional +extensions. + +@cindex @option{-march=} command line option, AArch64 +@item -march=@var{architecture}[+@var{extension}@dots{}] +This option specifies the target architecture. The assembler will +issue an error message if an attempt is made to assemble an +instruction which will not execute on the target architecture. The +only value for @var{architecture} is @code{armv8-a}. + +If both @option{-mcpu} and @option{-march} are specified, the +assembler will use the setting for @option{-mcpu}. If neither are +specified, the assembler will default to @option{-mcpu=all}. + +The architecture option can be extended with the same instruction set +extension options as the @option{-mcpu} option. Unlike +@option{-mcpu}, extensions are not always enabled by default, +@xref{AArch64 Extensions}. + +@cindex @code{-mverbose-error} command line option, AArch64 +@item -mverbose-error +This option enables verbose error messages for AArch64 gas. This option +is enabled by default. + +@cindex @code{-mno-verbose-error} command line option, AArch64 +@item -mno-verbose-error +This option disables verbose error messages in AArch64 gas. + @end table @c man end +@node AArch64 Extensions +@section Architecture Extensions + +The table below lists the permitted architecture extensions that are +supported by the assembler and the conditions under which they are +automatically enabled. + +Multiple extensions may be specified, separated by a @code{+}. +Extension mnemonics may also be removed from those the assembler +accepts. This is done by prepending @code{no} to the option that adds +the extension. Extensions that are removed must be listed after all +extensions that have been added. + +Enabling an extension that requires other extensions will +automatically cause those extensions to be enabled. Similarly, +disabling an extension that is required by other extensions will +automatically cause those extensions to be disabled. + +@multitable @columnfractions .12 .17 .17 .54 +@headitem Extension @tab Minimum Architecture @tab Enabled by default + @tab Description +@item @code{crc} @tab ARMv8-A @tab No + @tab Enable CRC instructions. +@item @code{crypto} @tab ARMv8-A @tab No + @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. +@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later + @tab Enable floating-point extensions. +@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later + @tab Enable Advanced SIMD extensions. This implies @code{fp}. +@end multitable + @node AArch64 Syntax @section Syntax @menu @@ -108,24 +187,24 @@ For example to load the 48-bit absolute address of @var{foo} into x0: @cindex ADRP, ADD, LDR/STR group relocations, AArch64 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} instructions can be generated by prefixing the label with -@samp{#:pg_hi21:} and @samp{#:lo12:} respectively. +@samp{:pg_hi21:} and @samp{#:lo12:} respectively. For example to use 33-bit (+/-4GB) pc-relative addressing to load the address of @var{foo} into x0: @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo add x0, x0, #:lo12:foo @end smallexample Or to load the value of @var{foo} into x0: @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo ldr x0, [x0, #:lo12:foo] @end smallexample -Note that @samp{#:pg_hi21:} is optional. +Note that @samp{:pg_hi21:} is optional. @smallexample adrp x0, foo @@ -134,7 +213,7 @@ Note that @samp{#:pg_hi21:} is optional. is equivalent to @smallexample - adrp x0, #:pg_hi21:foo + adrp x0, :pg_hi21:foo @end smallexample @node AArch64 Floating Point @@ -174,12 +253,12 @@ This directive switches to the @code{.bss} section. This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). -@code{GAS} maintains a separate literal pool for each section and each +GAS maintains a separate literal pool for each section and each sub-section. The @code{.ltorg} directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped. -Note - older versions of @code{GAS} would dump the current literal +Note - older versions of GAS would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools. @@ -240,7 +319,7 @@ should only be done if it is really necessary. @cindex AArch64 opcodes @cindex opcodes for AArch64 -@code{@value{AS}} implements all the standard AArch64 opcodes. It also +GAS implements all the standard AArch64 opcodes. It also implements several pseudo opcodes, including several synthetic load instructions. |