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author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-12-18 10:41:50 -0800 |
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committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-12-18 10:41:50 -0800 |
commit | b3e9a4171187f64c03d1858c2c840113df6b02de (patch) | |
tree | 24ed906374d33eabcbd3cfccc5d5b6ea9b4f5f51 /binutils-2.25/ld | |
parent | bbff162609624c737f72b070e2b53aeb5ed1e958 (diff) | |
download | toolchain_binutils-b3e9a4171187f64c03d1858c2c840113df6b02de.tar.gz toolchain_binutils-b3e9a4171187f64c03d1858c2c840113df6b02de.tar.bz2 toolchain_binutils-b3e9a4171187f64c03d1858c2c840113df6b02de.zip |
Add MIPS specific changes to binutils 2.25 (prerelease) for MIPSR6 bug fixes,
MXU support, and a fix to needed by gdbserver.
Diffstat (limited to 'binutils-2.25/ld')
-rw-r--r-- | binutils-2.25/ld/configure.tgt | 3 | ||||
-rw-r--r-- | binutils-2.25/ld/emultempl/mipself.em | 24 | ||||
-rw-r--r-- | binutils-2.25/ld/ld.texinfo | 7 | ||||
-rw-r--r-- | binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp | 7 | ||||
-rw-r--r-- | binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d | 23 | ||||
-rw-r--r-- | binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d | 23 | ||||
-rw-r--r-- | binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d | 23 | ||||
-rw-r--r-- | binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s | 25 |
8 files changed, 134 insertions, 1 deletions
diff --git a/binutils-2.25/ld/configure.tgt b/binutils-2.25/ld/configure.tgt index 24e36d10..828e1390 100644 --- a/binutils-2.25/ld/configure.tgt +++ b/binutils-2.25/ld/configure.tgt @@ -476,6 +476,9 @@ mips*el-*-vxworks*) targ_emul=elf32elmipvxworks mips*-*-vxworks*) targ_emul=elf32ebmipvxworks targ_extra_emuls="elf32elmipvxworks" ;; mips*-*-windiss) targ_emul=elf32mipswindiss ;; +mips64*el-*android*) targ_emul=elf64ltsmip + targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip" + targ_extra_libpath=$targ_extra_emuls ;; mips64*el-*-linux-*) targ_emul=elf32ltsmipn32 targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip" targ_extra_libpath=$targ_extra_emuls ;; diff --git a/binutils-2.25/ld/emultempl/mipself.em b/binutils-2.25/ld/emultempl/mipself.em index b6e17ceb..b3458aec 100644 --- a/binutils-2.25/ld/emultempl/mipself.em +++ b/binutils-2.25/ld/emultempl/mipself.em @@ -34,6 +34,7 @@ static lang_input_statement_type *stub_file; static bfd *stub_bfd; static bfd_boolean insn32; +static bfd_boolean compact_branches; static void mips_after_parse (void) @@ -205,7 +206,10 @@ mips_create_output_section_statements (void) _bfd_mips_elf_insn32 (&link_info, insn32); if (is_mips_elf (link_info.output_bfd)) - _bfd_mips_elf_init_stubs (&link_info, mips_add_stub_section); + { + _bfd_mips_elf_compact_branches (&link_info, compact_branches); + _bfd_mips_elf_init_stubs (&link_info, mips_add_stub_section); + } } /* This is called after we have merged the private data of the input bfds. */ @@ -252,11 +256,15 @@ EOF PARSE_AND_LIST_PROLOGUE=' #define OPTION_INSN32 301 #define OPTION_NO_INSN32 (OPTION_INSN32 + 1) +#define OPTION_COMPACT_BRANCHES (OPTION_NO_INSN32 + 1) +#define OPTION_NO_COMPACT_BRANCHES (OPTION_COMPACT_BRANCHES + 1) ' PARSE_AND_LIST_LONGOPTS=' { "insn32", no_argument, NULL, OPTION_INSN32 }, { "no-insn32", no_argument, NULL, OPTION_NO_INSN32 }, + { "compact-branches", no_argument, NULL, OPTION_COMPACT_BRANCHES }, + { "no-compact-branches", no_argument, NULL, OPTION_NO_COMPACT_BRANCHES }, ' PARSE_AND_LIST_OPTIONS=' @@ -266,6 +274,12 @@ PARSE_AND_LIST_OPTIONS=' fprintf (file, _("\ --no-insn32 Generate all microMIPS instructions\n" )); + fprintf (file, _("\ + --compact-branches Generate compact branches/jumps for MIPS R6\n" + )); + fprintf (file, _("\ + --no-compact-branches Generate delay slot branches/jumps for MIPS R6\n" + )); ' PARSE_AND_LIST_ARGS_CASES=' @@ -276,6 +290,14 @@ PARSE_AND_LIST_ARGS_CASES=' case OPTION_NO_INSN32: insn32 = FALSE; break; + + case OPTION_COMPACT_BRANCHES: + compact_branches = TRUE; + break; + + case OPTION_NO_COMPACT_BRANCHES: + compact_branches = FALSE; + break; ' LDEMUL_AFTER_PARSE=mips_after_parse diff --git a/binutils-2.25/ld/ld.texinfo b/binutils-2.25/ld/ld.texinfo index bb386e40..43973cc8 100644 --- a/binutils-2.25/ld/ld.texinfo +++ b/binutils-2.25/ld/ld.texinfo @@ -2819,6 +2819,13 @@ or in relaxation. If @samp{--insn32} is used, then the linker only uses used, all instruction encodings are used, including 16-bit ones where possible. +@kindex --compact-branches +@item --compact-branches +@kindex --no-compact-branches +@item --compact-branches +These options control the generation of compact instructions by the linker +in the PLT entries for MIPS R6. + @end table @c man end diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp b/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp index 91036de7..21c809fa 100644 --- a/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -434,6 +434,13 @@ if {$linux_gnu} { run_dump_test "jaloverflow" run_dump_test "jaloverflow-2" +run_dump_test "undefweak-overflow" + +if {$has_newabi} { + run_dump_test "undefweak-overflow-n32" + run_dump_test "undefweak-overflow-n64" +} + if {$has_newabi} { run_dump_test "jalbal" [list [list ld $abi_ldflags(n32)]] } diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d new file mode 100644 index 00000000..4d965b8d --- /dev/null +++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d @@ -0,0 +1,23 @@ +#name: undefined weak symbol overflow (n32) +#source: undefweak-overflow.s +#as: -n32 -EB +#ld: -melf32btsmipn32 -Ttext=0x20000000 -e start +#objdump: -dr +#... +0*20000000: d85fffff.* +0*20000004: 00000000.* +0*20000008: f85ffffd.* +0*2000000c: ec4ffffd.* +0*20000010: ec5bfffe.* +0*20000014: cbfffffa.* +0*20000018: 3c04e000.* +0*2000001c: 1000fff8.* +0*20000020: 2484ffe0.* +0*20000024: 0411fff6.* +0*20000028: 00000000.* +0*2000002c: 3c047fd0.* +0*20000030: 8e670c00.* +0*20000034: cfe50c00.* +0*20000038: 9400ffe2.* +0*2000003c: 0c000c00.* +#pass diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d new file mode 100644 index 00000000..e0d9fdad --- /dev/null +++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d @@ -0,0 +1,23 @@ +#name: undefined weak symbol overflow (n64) +#source: undefweak-overflow.s +#as: -64 -EB +#ld: -melf64btsmip -Ttext=0x20000000 -e start +#objdump: -dr +#... + 0*20000000: d85fffff.* + 0*20000004: 00000000.* + 0*20000008: f85ffffd.* + 0*2000000c: ec4ffffd.* + 0*20000010: ec5bfffe.* + 0*20000014: cbfffffa.* + 0*20000018: 3c04e000.* + 0*2000001c: 1000fff8.* + 0*20000020: 2484ffe0.* + 0*20000024: 0411fff6.* + 0*20000028: 00000000.* + 0*2000002c: 3c047fd0.* + 0*20000030: 8e670c00.* + 0*20000034: cfe50c00.* + 0*20000038: 9400ffe2.* + 0*2000003c: 0c000c00.* +#pass diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d new file mode 100644 index 00000000..18b3a900 --- /dev/null +++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d @@ -0,0 +1,23 @@ +#name: undefined weak symbol overflow +#source: undefweak-overflow.s +#as: -32 -EB +#ld: -melf32btsmip -Ttext=0x20000000 -e start +#objdump: -dr +#... +0*20000000: d85fffff.* +0*20000004: 00000000.* +0*20000008: f85ffffd.* +0*2000000c: ec4ffffd.* +0*20000010: ec5bfffe.* +0*20000014: cbfffffa.* +0*20000018: 3c04e000.* +0*2000001c: 1000fff8.* +0*20000020: 2484ffe0.* +0*20000024: 0411fff6.* +0*20000028: 00000000.* +0*2000002c: 3c047fd0.* +0*20000030: 8e670c00.* +0*20000034: cfe50c00.* +0*20000038: 9400ffe2.* +0*2000003c: 0c000c00.* +#pass diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s new file mode 100644 index 00000000..525f11b1 --- /dev/null +++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s @@ -0,0 +1,25 @@ +# relocs against undefined weak symbols should not be treated as +# overflowing + + + .globl start + .weak foo +start: + .set mips64r6 + beqzc $2, foo + bnezc $2, foo + lwpc $2, foo + ldpc $2, foo + bc foo + lui $4, %pcrel_hi(foo) + addiu $4, $4, %pcrel_lo(foo) + + .set mips32r2 + b foo + bal foo + lui $4, %gp_rel(foo) + + .set micromips + beqz16 $4, foo + b16 foo + b foo |