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authorSteve Ellcey <Steve.Ellcey@imgtec.com>2014-12-18 18:41:50 (GMT)
committerSteve Ellcey <Steve.Ellcey@imgtec.com>2014-12-18 18:41:50 (GMT)
commitb3e9a4171187f64c03d1858c2c840113df6b02de (patch)
tree24ed906374d33eabcbd3cfccc5d5b6ea9b4f5f51
parentbbff162609624c737f72b070e2b53aeb5ed1e958 (diff)
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Add MIPS specific changes to binutils 2.25 (prerelease) for MIPSR6 bug fixes,
MXU support, and a fix to needed by gdbserver.
-rw-r--r--binutils-2.25/bfd/elfxx-mips.c65
-rw-r--r--binutils-2.25/bfd/elfxx-mips.h2
-rw-r--r--binutils-2.25/binutils/doc/binutils.texi3
-rw-r--r--binutils-2.25/binutils/readelf.c2
-rw-r--r--binutils-2.25/gas/config/tc-mips.c184
-rwxr-xr-xbinutils-2.25/gas/configure5
-rw-r--r--binutils-2.25/gas/configure.ac5
-rw-r--r--binutils-2.25/gas/doc/as.texinfo7
-rw-r--r--binutils-2.25/gas/doc/c-mips.texi13
-rw-r--r--binutils-2.25/gas/testsuite/gas/mips/mips.exp1
-rw-r--r--binutils-2.25/gas/testsuite/gas/mips/mxu.d463
-rw-r--r--binutils-2.25/gas/testsuite/gas/mips/mxu.s340
-rw-r--r--binutils-2.25/include/elf/mips.h3
-rw-r--r--binutils-2.25/include/opcode/mips.h27
-rw-r--r--binutils-2.25/ld/configure.tgt3
-rw-r--r--binutils-2.25/ld/emultempl/mipself.em24
-rw-r--r--binutils-2.25/ld/ld.texinfo7
-rw-r--r--binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp7
-rw-r--r--binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d23
-rw-r--r--binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d23
-rw-r--r--binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d23
-rw-r--r--binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s25
-rw-r--r--binutils-2.25/opcodes/mips-dis.c78
-rw-r--r--binutils-2.25/opcodes/mips-formats.h10
-rw-r--r--binutils-2.25/opcodes/mips-opc.c196
25 files changed, 1488 insertions, 51 deletions
diff --git a/binutils-2.25/bfd/elfxx-mips.c b/binutils-2.25/bfd/elfxx-mips.c
index 2717610..2bd45d2 100644
--- a/binutils-2.25/bfd/elfxx-mips.c
+++ b/binutils-2.25/bfd/elfxx-mips.c
@@ -442,6 +442,9 @@ struct mips_elf_link_hash_table
/* True if we can only use 32-bit microMIPS instructions. */
bfd_boolean insn32;
+ /* True if we are targetting R6 compact branches. */
+ bfd_boolean compact_branches;
+
/* True if we're generating code for VxWorks. */
bfd_boolean is_vxworks;
@@ -1105,15 +1108,20 @@ static const bfd_vma mips_exec_plt_entry[] =
0x03200008 /* jr $25 */
};
-/* In the following PLT entry the JR and ADDIU instructions will
- be swapped in _bfd_mips_elf_finish_dynamic_symbol because
- LOAD_INTERLOCKS_P will be true for MIPS R6. */
static const bfd_vma mipsr6_exec_plt_entry[] =
{
0x3c0f0000, /* lui $15, %hi(.got.plt entry) */
0x01f90000, /* l[wd] $25, %lo(.got.plt entry)($15) */
+ 0x03200009, /* jr $25 */
+ 0x25f80000 /* addiu $24, $15, %lo(.got.plt entry) */
+};
+
+static const bfd_vma mipsr6_exec_plt_entry_compact[] =
+{
+ 0x3c0f0000, /* lui $15, %hi(.got.plt entry) */
+ 0x01f90000, /* l[wd] $25, %lo(.got.plt entry)($15) */
0x25f80000, /* addiu $24, $15, %lo(.got.plt entry) */
- 0x03200009 /* jr $25 */
+ 0xd8190000 /* jic $25, 0 */
};
/* The format of subsequent MIPS16 o32 PLT entries. We use v0 ($2)
@@ -5928,7 +5936,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
to them before. */
if (was_local_p)
value += gp0;
- overflowed_p = mips_elf_overflow_p (value, 16);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 16);
break;
case R_MIPS16_GOT16:
@@ -5983,7 +5992,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
return bfd_reloc_outofrange;
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 18);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 18);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -5996,7 +6006,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
return bfd_reloc_outofrange;
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 23);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 23);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6009,7 +6020,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
return bfd_reloc_outofrange;
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 28);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 28);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6022,7 +6034,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
return bfd_reloc_outofrange;
value = symbol + addend - ((p | 7) ^ 7);
- overflowed_p = mips_elf_overflow_p (value, 21);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 21);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6035,14 +6048,16 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
return bfd_reloc_outofrange;
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 21);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 21);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
case R_MIPS_PCHI16:
value = mips_elf_high (symbol + addend - p);
- overflowed_p = mips_elf_overflow_p (value, 16);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 16);
value &= howto->dst_mask;
break;
@@ -6057,7 +6072,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 8);
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 8);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 8);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6066,7 +6082,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 11);
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 11);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 11);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6075,7 +6092,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 17);
value = symbol + addend - p;
- overflowed_p = mips_elf_overflow_p (value, 17);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 17);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -6084,7 +6102,8 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 25);
value = symbol + addend - ((p | 3) ^ 3);
- overflowed_p = mips_elf_overflow_p (value, 25);
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 25);
value >>= howto->rightshift;
value &= howto->dst_mask;
break;
@@ -10546,7 +10565,10 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
/* Fill in the PLT entry itself. */
- if (MIPSR6_P (output_bfd))
+ if (MIPSR6_P (output_bfd)
+ && mips_elf_hash_table (info)->compact_branches)
+ plt_entry = mipsr6_exec_plt_entry_compact;
+ else if (MIPSR6_P (output_bfd))
plt_entry = mipsr6_exec_plt_entry;
else
plt_entry = mips_exec_plt_entry;
@@ -10554,7 +10576,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
bfd_put_32 (output_bfd, plt_entry[1] | got_address_low | load,
loc + 4);
- if (! LOAD_INTERLOCKS_P (output_bfd))
+ if (! LOAD_INTERLOCKS_P (output_bfd) || MIPSR6_P (output_bfd))
{
bfd_put_32 (output_bfd, plt_entry[2] | got_address_low, loc + 8);
bfd_put_32 (output_bfd, plt_entry[3], loc + 12);
@@ -13865,6 +13887,13 @@ _bfd_mips_elf_insn32 (struct bfd_link_info *info, bfd_boolean on)
{
mips_elf_hash_table (info)->insn32 = on;
}
+
+void
+_bfd_mips_elf_compact_branches (struct bfd_link_info *info, bfd_boolean on)
+{
+ mips_elf_hash_table (info)->compact_branches = on;
+}
+
/* Return the .MIPS.abiflags value representing each ISA Extension. */
@@ -15491,6 +15520,8 @@ print_mips_ases (FILE *file, unsigned int mask)
fputs ("\n\tDSP ASE", file);
if (mask & AFL_ASE_DSPR2)
fputs ("\n\tDSP R2 ASE", file);
+ if (mask & AFL_ASE_DSPR6)
+ fputs ("\n\tDSP R6 ASE", file);
if (mask & AFL_ASE_EVA)
fputs ("\n\tEnhanced VA Scheme", file);
if (mask & AFL_ASE_MCU)
diff --git a/binutils-2.25/bfd/elfxx-mips.h b/binutils-2.25/bfd/elfxx-mips.h
index 8f5c53e..c40db0d 100644
--- a/binutils-2.25/bfd/elfxx-mips.h
+++ b/binutils-2.25/bfd/elfxx-mips.h
@@ -150,6 +150,8 @@ extern void _bfd_mips_elf_use_plts_and_copy_relocs
(struct bfd_link_info *);
extern void _bfd_mips_elf_insn32
(struct bfd_link_info *, bfd_boolean);
+extern void _bfd_mips_elf_compact_branches
+ (struct bfd_link_info *, bfd_boolean);
extern bfd_boolean _bfd_mips_elf_init_stubs
(struct bfd_link_info *,
asection *(*) (const char *, asection *, asection *));
diff --git a/binutils-2.25/binutils/doc/binutils.texi b/binutils-2.25/binutils/doc/binutils.texi
index 39eb1d2..5d6c2d5 100644
--- a/binutils-2.25/binutils/doc/binutils.texi
+++ b/binutils-2.25/binutils/doc/binutils.texi
@@ -2136,6 +2136,9 @@ Disassemble the virtualization ASE instructions.
@item xpa
Disassemble the eXtended Physical Address (XPA) ASE instructions.
+@item mxu
+Disassemble the MXU ASE instructions.
+
@item gpr-names=@var{ABI}
Print GPR (general-purpose register) names as appropriate
for the specified ABI. By default, GPR names are selected according to
diff --git a/binutils-2.25/binutils/readelf.c b/binutils-2.25/binutils/readelf.c
index 0c00b2f..997b463 100644
--- a/binutils-2.25/binutils/readelf.c
+++ b/binutils-2.25/binutils/readelf.c
@@ -13120,6 +13120,8 @@ print_mips_ases (unsigned int mask)
fputs ("\n\tDSP ASE", stdout);
if (mask & AFL_ASE_DSPR2)
fputs ("\n\tDSP R2 ASE", stdout);
+ if (mask & AFL_ASE_DSPR6)
+ fputs ("\n\tDSP R6 ASE", stdout);
if (mask & AFL_ASE_EVA)
fputs ("\n\tEnhanced VA Scheme", stdout);
if (mask & AFL_ASE_MCU)
diff --git a/binutils-2.25/gas/config/tc-mips.c b/binutils-2.25/gas/config/tc-mips.c
index cfc4fa5..0f7e0c5 100644
--- a/binutils-2.25/gas/config/tc-mips.c
+++ b/binutils-2.25/gas/config/tc-mips.c
@@ -1409,10 +1409,14 @@ enum options
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
OPTION_NO_DSPR2,
+ OPTION_DSPR6,
+ OPTION_NO_DSPR6,
OPTION_EVA,
OPTION_NO_EVA,
OPTION_XPA,
OPTION_NO_XPA,
+ OPTION_MXU,
+ OPTION_NO_MXU,
OPTION_MICROMIPS,
OPTION_NO_MICROMIPS,
OPTION_MCU,
@@ -1521,6 +1525,8 @@ struct option md_longopts[] =
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
{"mdspr2", no_argument, NULL, OPTION_DSPR2},
{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
+ {"mdspr6", no_argument, NULL, OPTION_DSPR6},
+ {"mno-dspr6", no_argument, NULL, OPTION_NO_DSPR6},
{"meva", no_argument, NULL, OPTION_EVA},
{"mno-eva", no_argument, NULL, OPTION_NO_EVA},
{"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
@@ -1533,6 +1539,8 @@ struct option md_longopts[] =
{"mno-msa", no_argument, NULL, OPTION_NO_MSA},
{"mxpa", no_argument, NULL, OPTION_XPA},
{"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
+ {"mmxu", no_argument, NULL, OPTION_MXU},
+ {"mno-mxu", no_argument, NULL, OPTION_NO_MXU},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
@@ -1662,6 +1670,11 @@ static const struct mips_ase mips_ases[] = {
2, 2, 2, 2,
-1 },
+ { "dspr6", ASE_DSP | ASE_DSPR2 | ASE_DSPR6, 0,
+ OPTION_DSPR6, OPTION_NO_DSPR6,
+ 6, 6, 6, 6,
+ -1 },
+
{ "eva", ASE_EVA, 0,
OPTION_EVA, OPTION_NO_EVA,
2, 2, 2, 2,
@@ -1708,6 +1721,11 @@ static const struct mips_ase mips_ases[] = {
OPTION_XPA, OPTION_NO_XPA,
2, 2, -1, -1,
-1 },
+
+ { "mxu", ASE_MXU, 0,
+ OPTION_MXU, OPTION_NO_MXU,
+ 1, 1, -1, -1,
+ -1 },
};
/* The set of ASEs that require -mfp64. */
@@ -1715,7 +1733,7 @@ static const struct mips_ase mips_ases[] = {
/* Groups of ASE_* flags that represent different revisions of an ASE. */
static const unsigned int mips_ase_groups[] = {
- ASE_DSP | ASE_DSPR2
+ ASE_DSP | ASE_DSPR2 | ASE_DSPR6
};
/* Pseudo-op table.
@@ -2490,7 +2508,7 @@ struct regname {
};
#define RNUM_MASK 0x00000ff
-#define RTYPE_MASK 0x0ffff00
+#define RTYPE_MASK 0x1ffff00
#define RTYPE_NUM 0x0000100
#define RTYPE_FPU 0x0000200
#define RTYPE_FCC 0x0000400
@@ -2507,6 +2525,7 @@ struct regname {
#define RTYPE_R5900_R 0x0200000
#define RTYPE_R5900_ACC 0x0400000
#define RTYPE_MSA 0x0800000
+#define RTYPE_MXU 0x1000000
#define RWARN 0x8000000
#define GENERIC_REGISTER_NUMBERS \
@@ -2711,6 +2730,26 @@ struct regname {
{"$ac2", RTYPE_ACC | 2}, \
{"$ac3", RTYPE_ACC | 3}
+#define MXU_REGISTER_NAMES \
+ {"xr0", RTYPE_MXU | 0}, \
+ {"xr1", RTYPE_MXU | 1}, \
+ {"xr2", RTYPE_MXU | 2}, \
+ {"xr3", RTYPE_MXU | 3}, \
+ {"xr4", RTYPE_MXU | 4}, \
+ {"xr5", RTYPE_MXU | 5}, \
+ {"xr6", RTYPE_MXU | 6}, \
+ {"xr7", RTYPE_MXU | 7}, \
+ {"xr8", RTYPE_MXU | 8}, \
+ {"xr9", RTYPE_MXU | 9}, \
+ {"xr10", RTYPE_MXU | 10}, \
+ {"xr11", RTYPE_MXU | 11}, \
+ {"xr12", RTYPE_MXU | 12}, \
+ {"xr13", RTYPE_MXU | 13}, \
+ {"xr14", RTYPE_MXU | 14}, \
+ {"xr15", RTYPE_MXU | 15}, \
+ {"xr16", RTYPE_MXU | 16}, \
+ {"mxu_cr", RTYPE_MXU | 16}
+
static const struct regname reg_names[] = {
GENERIC_REGISTER_NUMBERS,
FPU_REGISTER_NAMES,
@@ -2730,6 +2769,7 @@ static const struct regname reg_names[] = {
R5900_R_NAMES,
R5900_ACC_NAMES,
MIPS_DSP_ACCUMULATOR_NAMES,
+ MXU_REGISTER_NAMES,
{0, 0}
};
@@ -3361,7 +3401,7 @@ validate_mips_insn (const struct mips_opcode *opcode,
used_bits &= ~(mask & 0x700);
}
/* Skip prefix characters. */
- if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
+ if (decode_operand && (*s == '+' || *s == 'm' || *s == '-' || *s == '`'))
++s;
opno += 1;
break;
@@ -4415,6 +4455,8 @@ operand_reg_mask (const struct mips_cl_insn *insn,
case OP_VU0_SUFFIX:
case OP_VU0_MATCH_SUFFIX:
case OP_IMM_INDEX:
+ case OP_MAPPED_STRING:
+ case OP_MXU_STRIDE:
abort ();
case OP_REG:
@@ -4788,6 +4830,12 @@ convert_reg_type (const struct mips_opcode *opcode,
{
switch (type)
{
+ case OP_REG_MXU:
+ return RTYPE_NUM | RTYPE_MXU;
+
+ case OP_REG_MXU_GP:
+ return RTYPE_GP | RTYPE_MXU;
+
case OP_REG_GP:
return RTYPE_NUM | RTYPE_GP;
@@ -5113,6 +5161,65 @@ match_msb_operand (struct mips_arg_info *arg,
return TRUE;
}
+
+/* OP_MAPPED_STRING matcher. */
+
+static bfd_boolean
+match_string_operand (struct mips_arg_info *arg,
+ const struct mips_operand *operand_base)
+{
+ const struct mips_mapped_string_operand *operand;
+ expressionS ex;
+ bfd_reloc_code_real_type r[3];
+ int i;
+ unsigned int store_val;
+ const char * symbol_name;
+ bfd_boolean match;
+
+ operand = (const struct mips_mapped_string_operand *) operand_base;
+
+ if (!match_expression (arg, &ex, r))
+ return FALSE;
+
+ if (operand->allow_constants && ex.X_op == O_constant
+ && r[0] == BFD_RELOC_UNUSED)
+ store_val = ex.X_add_number;
+ else if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_symbol
+ && ex.X_add_number == 0 && ex.X_op_symbol == NULL)
+ {
+ symbol_name = S_GET_NAME (ex.X_add_symbol);
+ match = FALSE;
+
+ for (i = 0 ; i < (1 << operand_base->size) ; i++)
+ {
+ if (strcmp (operand->strings[i], symbol_name) == 0)
+ {
+ store_val = i;
+ match = TRUE;
+ break;
+ }
+ }
+
+ if (!match)
+ {
+ set_insn_error (arg->argnum, _("Invalid string in operand"));
+ return FALSE;
+ }
+ }
+ else
+ return FALSE;
+
+ if (store_val >= (unsigned int) (1 << operand_base->size))
+ {
+ match_out_of_range (arg);
+ return FALSE;
+ }
+
+ insn_insert_operand (arg->insn, operand_base, store_val);
+ return TRUE;
+}
+
+
/* OP_REG matcher. */
static bfd_boolean
@@ -5138,6 +5245,13 @@ match_reg_operand (struct mips_arg_info *arg,
else
uval = regno;
+ if (operand_base->size > 0
+ && uval >= (unsigned int) (1 << operand_base->size))
+ {
+ match_out_of_range (arg);
+ return FALSE;
+ }
+
arg->last_regno = regno;
if (arg->opnum == 1)
arg->dest_regno = regno;
@@ -5665,6 +5779,24 @@ match_imm_index_operand (struct mips_arg_info *arg,
return TRUE;
}
+/* OP_MXU_STRIDE matcher. */
+
+static bfd_boolean
+match_mxu_stride_operand (struct mips_arg_info *arg,
+ const struct mips_operand *operand)
+{
+ offsetT sval;
+
+ if (!match_const_int (arg, &sval))
+ return FALSE;
+
+ if (sval < 0 || sval > 2)
+ return FALSE;
+
+ insn_insert_operand (arg->insn, operand, sval);
+ return TRUE;
+}
+
/* OP_REG_INDEX matcher. */
static bfd_boolean
@@ -5941,6 +6073,9 @@ match_operand (struct mips_arg_info *arg,
case OP_MSB:
return match_msb_operand (arg, operand);
+ case OP_MAPPED_STRING:
+ return match_string_operand (arg, operand);
+
case OP_REG:
case OP_OPTIONAL_REG:
return match_reg_operand (arg, operand);
@@ -6001,6 +6136,9 @@ match_operand (struct mips_arg_info *arg,
case OP_NON_ZERO_REG:
return match_non_zero_reg_operand (arg, operand);
+
+ case OP_MXU_STRIDE:
+ return match_mxu_stride_operand (arg, operand);
}
abort ();
}
@@ -6777,6 +6915,11 @@ get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
if (mips_relax.sequence == 2)
return APPEND_ADD;
+ /* Convert a non-compact to compact branch/jump instruction. */
+ if (ISA_IS_R6 (mips_opts.isa)
+ && (ip->insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT))
+ return APPEND_ADD_COMPACT;
+
/* We must not dabble with instructions in a ".set norerorder" block. */
if (mips_opts.noreorder)
return APPEND_ADD;
@@ -7455,12 +7598,20 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
break;
case APPEND_ADD_COMPACT:
- /* Convert MIPS16 jr/jalr into a "compact" jump. */
- gas_assert (mips_opts.mips16);
- ip->insn_opcode |= 0x0080;
- find_altered_mips16_opcode (ip);
- install_insn (ip);
- insert_into_history (0, 1, ip);
+ gas_assert(mips_opts.mips16 || ISA_IS_R6 (mips_opts.isa));
+ if (mips_opts.mips16)
+ {
+ /* Convert MIPS16 jr/jalr into a "compact" jump. */
+ ip->insn_opcode |= 0x0080;
+ find_altered_mips16_opcode (ip);
+ install_insn (ip);
+ insert_into_history (0, 1, ip);
+ }
+ else
+ {
+ install_insn (ip);
+ insert_into_history (0, 1, ip);
+ }
break;
case APPEND_SWAP:
@@ -7497,8 +7648,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
}
/* If we have just completed an unconditional branch, clear the history. */
- if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
+ if (((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
|| (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
+ && !(history[0].insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT))
{
unsigned int i;
@@ -7876,7 +8028,7 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
abort ();
/* Skip prefixes. */
- if (*args == '+' || *args == 'm' || *args == '-')
+ if (*args == '+' || *args == 'm' || *args == '-' || *args == '`')
args++;
if (mips_optional_operand_p (operand)
@@ -8530,7 +8682,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
uval |= (uval << 5);
insn_insert_operand (&insn, operand, uval);
- if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
+ if (*fmt == '+' || *fmt == 'm' || *fmt == '-' || *fmt == '`')
++fmt;
break;
}
@@ -17906,6 +18058,8 @@ mips_convert_ase_flags (int ase)
ext_ases |= AFL_ASE_DSP;
if (ase & ASE_DSPR2)
ext_ases |= AFL_ASE_DSPR2;
+ if (ase & ASE_DSPR6)
+ ext_ases |= AFL_ASE_DSPR6;
if (ase & ASE_EVA)
ext_ases |= AFL_ASE_EVA;
if (ase & ASE_MCU)
@@ -18680,6 +18834,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
MIPS64R2 rather than MIPS64. */
{ "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
+ /* i6400. */
+ { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
+
/* End marker */
{ NULL, 0, 0, 0, 0 }
};
@@ -18918,6 +19075,9 @@ MIPS options:\n\
-mxpa generate eXtended Physical Address (XPA) instructions\n\
-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
fprintf (stream, _("\
+-mmxu generate MXU instructions\n\
+-mno-mxu do not generate MXU instructions\n"));
+ fprintf (stream, _("\
-mvirt generate Virtualization instructions\n\
-mno-virt do not generate Virtualization instructions\n"));
fprintf (stream, _("\
diff --git a/binutils-2.25/gas/configure b/binutils-2.25/gas/configure
index 1025ddb..c8b6e87 100755
--- a/binutils-2.25/gas/configure
+++ b/binutils-2.25/gas/configure
@@ -12159,6 +12159,9 @@ _ACEOF
mips64vr | mips64vrel)
mips_cpu=vr4100
;;
+ mips64*-*android*)
+ mips_cpu=mips64r6
+ ;;
mipsisa32r2* | mipsisa64r2*)
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
;;
@@ -12203,7 +12206,7 @@ _ACEOF
mips*-linux* | mips*-freebsd* | mips*-kfreebsd*-gnu)
mips_default_abi=O32_ABI
;;
- mips64*-openbsd*)
+ mips64*-openbsd* | mips64*-*android*)
mips_default_abi=N64_ABI
;;
*)
diff --git a/binutils-2.25/gas/configure.ac b/binutils-2.25/gas/configure.ac
index 371f7b3..9ac0442 100644
--- a/binutils-2.25/gas/configure.ac
+++ b/binutils-2.25/gas/configure.ac
@@ -241,6 +241,9 @@ changequote([,])dnl
mips64vr | mips64vrel)
mips_cpu=vr4100
;;
+ mips64*-*android*)
+ mips_cpu=mips64r6
+ ;;
mipsisa32r2* | mipsisa64r2*)
changequote(,)dnl
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
@@ -293,7 +296,7 @@ changequote([,])dnl
mips*-linux* | mips*-freebsd* | mips*-kfreebsd*-gnu)
mips_default_abi=O32_ABI
;;
- mips64*-openbsd*)
+ mips64*-openbsd* | mips64*-*android*)
mips_default_abi=N64_ABI
;;
*)
diff --git a/binutils-2.25/gas/doc/as.texinfo b/binutils-2.25/gas/doc/as.texinfo
index 243851b..55e4f54 100644
--- a/binutils-2.25/gas/doc/as.texinfo
+++ b/binutils-2.25/gas/doc/as.texinfo
@@ -417,6 +417,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mdspr2}] [@b{-mno-dspr2}]
[@b{-mmsa}] [@b{-mno-msa}]
[@b{-mxpa}] [@b{-mno-xpa}]
+ [@b{-mmxu}] [@b{-mno-mxu}]
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
[@b{-minsn32}] [@b{-mno-insn32}]
@@ -1401,6 +1402,12 @@ Generate code for the MIPS eXtended Physical Address (XPA) Extension.
This tells the assembler to accept XPA instructions.
@samp{-mno-xpa} turns off this option.
+@item -mmxu
+@itemx -mno-mxu
+Generate code for the XBurst MXU Extension.
+This tells the assembler to accept MXU instructions.
+@samp{-mno-mxu} turns off this option.
+
@item -mmt
@itemx -mno-mt
Generate code for the MT Application Specific Extension.
diff --git a/binutils-2.25/gas/doc/c-mips.texi b/binutils-2.25/gas/doc/c-mips.texi
index d960022..7d19169 100644
--- a/binutils-2.25/gas/doc/c-mips.texi
+++ b/binutils-2.25/gas/doc/c-mips.texi
@@ -215,6 +215,12 @@ Generate code for the MIPS eXtended Physical Address (XPA) Extension.
This tells the assembler to accept XPA instructions.
@samp{-mno-xpa} turns off this option.
+@item -mmxu
+@itemx -mno-mxu
+Generate code for the XBurst MXU Extension.
+This tells the assembler to accept MXU instructions.
+@samp{-mno-mxu} turns off this option.
+
@item -mvirt
@itemx -mno-virt
Generate code for the Virtualization Application Specific Extension.
@@ -1041,6 +1047,13 @@ The directive @code{.set xpa} makes the assembler accept instructions
from the XPA Extension from that point on in the assembly. The
@code{.set noxpa} directive prevents XPA instructions from being accepted.
+@cindex XBurst MXU instruction generation override
+@kindex @code{.set mxu}
+@kindex @code{.set nomxu}
+The directive @code{.set mxu} makes the assembler accept instructions
+from the MXU Extension from that point on in the assembly. The
+@code{.set nomxu} directive prevents MXU instructions from being accepted.
+
Traditional MIPS assemblers do not support these directives.
@node MIPS Floating-Point
diff --git a/binutils-2.25/gas/testsuite/gas/mips/mips.exp b/binutils-2.25/gas/testsuite/gas/mips/mips.exp
index 6c0c9c8..fb5d19a 100644
--- a/binutils-2.25/gas/testsuite/gas/mips/mips.exp
+++ b/binutils-2.25/gas/testsuite/gas/mips/mips.exp
@@ -1237,6 +1237,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
+ run_dump_test_arches "mxu" [mips_arch_list_matching mips32 !micromips !octeon]
run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5 !micromips]
run_dump_test "pcrel-1"
diff --git a/binutils-2.25/gas/testsuite/gas/mips/mxu.d b/binutils-2.25/gas/testsuite/gas/mips/mxu.d
new file mode 100644
index 0000000..61990ff
--- /dev/null
+++ b/binutils-2.25/gas/testsuite/gas/mips/mxu.d
@@ -0,0 +1,463 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmxu
+#name: MXU instructions
+#as: -32 -mmxu
+
+.*: +file format .*mips.*
+
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 44021002 mfc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 44020802 mfc1 v0,\$f1
+[0-9a-f]+ <[^>]*> 44821002 mtc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 44820802 mtc1 v0,\$f1
+[0-9a-f]+ <[^>]*> 44621002 mfhc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 44621002 mfhc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2
+[0-9a-f]+ <[^>]*> 7010c84a d16mac xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84a d16mac xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84a d16mac xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84a d16mac xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7010c84a d16mac xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84a d16mac xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84a d16mac xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84a d16mac xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7110c84a d16mac xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84a d16mac xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84a d16mac xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84a d16mac xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7110c84a d16mac xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84a d16mac xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84a d16mac xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84a d16mac xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7210c84a d16mac xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84a d16mac xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84a d16mac xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84a d16mac xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7210c84a d16mac xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84a d16mac xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84a d16mac xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84a d16mac xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7310c84a d16mac xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84a d16mac xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84a d16mac xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84a d16mac xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7310c84a d16mac xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84a d16mac xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84a d16mac xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84a d16mac xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84b d16macf xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84b d16macf xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84b d16macf xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84b d16macf xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7010c84b d16macf xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84b d16macf xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84b d16macf xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84b d16macf xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7110c84b d16macf xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84b d16macf xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84b d16macf xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84b d16macf xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7110c84b d16macf xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84b d16macf xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84b d16macf xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84b d16macf xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7210c84b d16macf xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84b d16macf xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84b d16macf xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84b d16macf xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7210c84b d16macf xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84b d16macf xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84b d16macf xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84b d16macf xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7310c84b d16macf xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84b d16macf xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84b d16macf xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84b d16macf xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7310c84b d16macf xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84b d16macf xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84b d16macf xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84b d16macf xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84c d16madl xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84c d16madl xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84c d16madl xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84c d16madl xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7010c84c d16madl xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84c d16madl xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84c d16madl xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84c d16madl xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7110c84c d16madl xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84c d16madl xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84c d16madl xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84c d16madl xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7110c84c d16madl xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84c d16madl xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84c d16madl xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84c d16madl xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7210c84c d16madl xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84c d16madl xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84c d16madl xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84c d16madl xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7210c84c d16madl xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84c d16madl xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84c d16madl xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84c d16madl xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7310c84c d16madl xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84c d16madl xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84c d16madl xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84c d16madl xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7310c84c d16madl xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84c d16madl xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84c d16madl xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84c d16madl xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84e q16add xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84e q16add xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84e q16add xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84e q16add xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7010c84e q16add xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84e q16add xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84e q16add xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84e q16add xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7110c84e q16add xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84e q16add xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84e q16add xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84e q16add xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7110c84e q16add xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84e q16add xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84e q16add xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84e q16add xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7210c84e q16add xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84e q16add xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84e q16add xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84e q16add xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7210c84e q16add xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84e q16add xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84e q16add xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84e q16add xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7310c84e q16add xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84e q16add xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84e q16add xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84e q16add xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7310c84e q16add xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84e q16add xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84e q16add xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84e q16add xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84f d16mace xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84f d16mace xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84f d16mace xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84f d16mace xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7010c84f d16mace xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7050c84f d16mace xr1,xr2,xr3,xr4,AA,LW
+[0-9a-f]+ <[^>]*> 7090c84f d16mace xr1,xr2,xr3,xr4,AA,HW
+[0-9a-f]+ <[^>]*> 70d0c84f d16mace xr1,xr2,xr3,xr4,AA,XW
+[0-9a-f]+ <[^>]*> 7110c84f d16mace xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84f d16mace xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84f d16mace xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84f d16mace xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7110c84f d16mace xr1,xr2,xr3,xr4,AS,WW
+[0-9a-f]+ <[^>]*> 7150c84f d16mace xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7190c84f d16mace xr1,xr2,xr3,xr4,AS,HW
+[0-9a-f]+ <[^>]*> 71d0c84f d16mace xr1,xr2,xr3,xr4,AS,XW
+[0-9a-f]+ <[^>]*> 7210c84f d16mace xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84f d16mace xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84f d16mace xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84f d16mace xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7210c84f d16mace xr1,xr2,xr3,xr4,SA,WW
+[0-9a-f]+ <[^>]*> 7250c84f d16mace xr1,xr2,xr3,xr4,SA,LW
+[0-9a-f]+ <[^>]*> 7290c84f d16mace xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 72d0c84f d16mace xr1,xr2,xr3,xr4,SA,XW
+[0-9a-f]+ <[^>]*> 7310c84f d16mace xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84f d16mace xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84f d16mace xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84f d16mace xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7310c84f d16mace xr1,xr2,xr3,xr4,SS,WW
+[0-9a-f]+ <[^>]*> 7350c84f d16mace xr1,xr2,xr3,xr4,SS,LW
+[0-9a-f]+ <[^>]*> 7390c84f d16mace xr1,xr2,xr3,xr4,SS,HW
+[0-9a-f]+ <[^>]*> 73d0c84f d16mace xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c848 d16mul xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7050c848 d16mul xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7090c848 d16mul xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 70d0c848 d16mul xr1,xr2,xr3,xr4,XW
+[0-9a-f]+ <[^>]*> 7010c848 d16mul xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7050c848 d16mul xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7090c848 d16mul xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 70d0c848 d16mul xr1,xr2,xr3,xr4,XW
+[0-9a-f]+ <[^>]*> 7000c849 d16mulf xr1,xr2,xr3,WW
+[0-9a-f]+ <[^>]*> 7040c849 d16mulf xr1,xr2,xr3,LW
+[0-9a-f]+ <[^>]*> 7080c849 d16mulf xr1,xr2,xr3,HW
+[0-9a-f]+ <[^>]*> 70c0c849 d16mulf xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7000c849 d16mulf xr1,xr2,xr3,WW
+[0-9a-f]+ <[^>]*> 7040c849 d16mulf xr1,xr2,xr3,LW
+[0-9a-f]+ <[^>]*> 7080c849 d16mulf xr1,xr2,xr3,HW
+[0-9a-f]+ <[^>]*> 70c0c849 d16mulf xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW
+[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW
+[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW
+[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW
+[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW
+[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW
+[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7010c84d s16mad xr1,xr2,xr3,xr4,A,WW
+[0-9a-f]+ <[^>]*> 7050c84d s16mad xr1,xr2,xr3,xr4,A,LW
+[0-9a-f]+ <[^>]*> 7090c84d s16mad xr1,xr2,xr3,xr4,A,HW
+[0-9a-f]+ <[^>]*> 70d0c84d s16mad xr1,xr2,xr3,xr4,A,XW
+[0-9a-f]+ <[^>]*> 7010c84d s16mad xr1,xr2,xr3,xr4,A,WW
+[0-9a-f]+ <[^>]*> 7050c84d s16mad xr1,xr2,xr3,xr4,A,LW
+[0-9a-f]+ <[^>]*> 7090c84d s16mad xr1,xr2,xr3,xr4,A,HW
+[0-9a-f]+ <[^>]*> 70d0c84d s16mad xr1,xr2,xr3,xr4,A,XW
+[0-9a-f]+ <[^>]*> 7110c84d s16mad xr1,xr2,xr3,xr4,S,WW
+[0-9a-f]+ <[^>]*> 7150c84d s16mad xr1,xr2,xr3,xr4,S,LW
+[0-9a-f]+ <[^>]*> 7190c84d s16mad xr1,xr2,xr3,xr4,S,HW
+[0-9a-f]+ <[^>]*> 71d0c84d s16mad xr1,xr2,xr3,xr4,S,XW
+[0-9a-f]+ <[^>]*> 7110c84d s16mad xr1,xr2,xr3,xr4,S,WW
+[0-9a-f]+ <[^>]*> 7150c84d s16mad xr1,xr2,xr3,xr4,S,LW
+[0-9a-f]+ <[^>]*> 7190c84d s16mad xr1,xr2,xr3,xr4,S,HW
+[0-9a-f]+ <[^>]*> 71d0c84d s16mad xr1,xr2,xr3,xr4,S,XW
+[0-9a-f]+ <[^>]*> 7010c878 q8mul xr1,xr2,xr3,xr4
+[0-9a-f]+ <[^>]*> 7090c878 q8mulsu xr1,xr2,xr3,xr4
+[0-9a-f]+ <[^>]*> 7000c879 q8movz xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7004c879 q8movn xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7008c879 d16movz xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 700cc879 d16movn xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c879 s32movz xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7014c879 s32movn xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c87a q8mac xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c87a q8mac xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c87a q8mac xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c87a q8mac xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c87a q8macsu xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7290c87a q8macsu xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7190c87a q8macsu xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7390c87a q8macsu xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c87b q16scop xr1,xr2,xr3,xr4
+[0-9a-f]+ <[^>]*> 7010c87c q8madl xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c87c q8madl xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c87c q8madl xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c87c q8madl xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c87d s32sfl xr1,xr2,xr3,xr4,ptn0
+[0-9a-f]+ <[^>]*> 7110c87d s32sfl xr1,xr2,xr3,xr4,ptn1
+[0-9a-f]+ <[^>]*> 7210c87d s32sfl xr1,xr2,xr3,xr4,ptn2
+[0-9a-f]+ <[^>]*> 7310c87d s32sfl xr1,xr2,xr3,xr4,ptn3
+[0-9a-f]+ <[^>]*> 7010c87e q8sad xr1,xr2,xr3,xr4
+[0-9a-f]+ <[^>]*> 7010c858 d32add xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c858 d32add xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c858 d32add xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c858 d32add xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7050c858 d32addc xr1,xr2,xr3,xr4
+[0-9a-f]+ <[^>]*> 7010c859 d32acc xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c859 d32acc xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c859 d32acc xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c859 d32acc xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7050c859 d32accm xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7250c859 d32accm xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7150c859 d32accm xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7350c859 d32accm xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c859 d32asum xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7290c859 d32asum xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7190c859 d32asum xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7390c859 d32asum xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c85b q16acc xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c85b q16acc xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c85b q16acc xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c85b q16acc xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7050c85b q16accm xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7250c85b q16accm xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7150c85b q16accm xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7350c85b q16accm xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c85b d16asum xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7290c85b d16asum xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7190c85b d16asum xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7390c85b d16asum xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c85c q8adde xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c85c q8adde xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c85c q8adde xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c85c q8adde xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7040c85c d8sum xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7080c85c d8sumc xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c85d q8acce xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7210c85d q8acce xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7110c85d q8acce xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7310c85d q8acce xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7000c847 s32cps xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7008c847 d16cps xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c847 q8abd xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7018c847 q16sat xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7000c846 s32slt xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7004c846 d16slt xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7008c846 d16avg xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 700cc846 d16avgr xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c846 q8avg xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7014c846 q8avgr xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 701cc846 q8add xr1,xr2,xr3,AA
+[0-9a-f]+ <[^>]*> 711cc846 q8add xr1,xr2,xr3,AS
+[0-9a-f]+ <[^>]*> 721cc846 q8add xr1,xr2,xr3,SA
+[0-9a-f]+ <[^>]*> 731cc846 q8add xr1,xr2,xr3,SS
+[0-9a-f]+ <[^>]*> 7000c843 s32max xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7004c843 s32min xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7008c843 d16max xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 700cc843 d16min xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7010c843 q8max xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7014c843 q8min xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7018c843 q8slt xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 701cc843 q8sltu xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 73d0c830 d32sll xr0,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 73d0c871 d32slr xr1,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 73c0c872 d32sarl xr1,xr2,xr3,15
+[0-9a-f]+ <[^>]*> 73d0c873 d32sar xr1,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 73d0c874 q16sll xr1,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 73d0c875 q16slr xr1,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 73d0c877 q16sar xr1,xr2,xr3,xr4,15
+[0-9a-f]+ <[^>]*> 70008436 d32sllv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 70048436 d32slrv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 700c8436 d32sarv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 70108436 q16sllv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 70148436 q16slrv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 701c8436 q16sarv xr1,xr2,zero
+[0-9a-f]+ <[^>]*> 70028840 s32madd xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 70028841 s32maddu xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 70028844 s32msub xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 70028845 s32msubu xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 70020866 s32mul xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 70024866 s32mulu xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 7002c866 s32extrv xr1,xr2,zero,v0
+[0-9a-f]+ <[^>]*> 701f8866 s32extr xr1,xr2,zero,31
+[0-9a-f]+ <[^>]*> 7000c867 d32sarw xr1,xr2,xr3,zero
+[0-9a-f]+ <[^>]*> 7004c867 s32aln xr1,xr2,xr3,zero
+[0-9a-f]+ <[^>]*> 7008c867 s32alni xr1,xr2,xr3,ptn0
+[0-9a-f]+ <[^>]*> 7088c867 s32alni xr1,xr2,xr3,ptn1
+[0-9a-f]+ <[^>]*> 7108c867 s32alni xr1,xr2,xr3,ptn2
+[0-9a-f]+ <[^>]*> 7188c867 s32alni xr1,xr2,xr3,ptn3
+[0-9a-f]+ <[^>]*> 7208c867 s32alni xr1,xr2,xr3,ptn4
+[0-9a-f]+ <[^>]*> 700dfc67 s32lui xr1,127,ptn0
+[0-9a-f]+ <[^>]*> 708dfc67 s32lui xr1,127,ptn1
+[0-9a-f]+ <[^>]*> 710dfc67 s32lui xr1,127,ptn2
+[0-9a-f]+ <[^>]*> 718dfc67 s32lui xr1,127,ptn3
+[0-9a-f]+ <[^>]*> 720dfc67 s32lui xr1,127,ptn4
+[0-9a-f]+ <[^>]*> 728dfc67 s32lui xr1,127,ptn5
+[0-9a-f]+ <[^>]*> 730dfc67 s32lui xr1,127,ptn6
+[0-9a-f]+ <[^>]*> 738dfc67 s32lui xr1,127,ptn7
+[0-9a-f]+ <[^>]*> 700e0067 s32lui xr1,-128,ptn0
+[0-9a-f]+ <[^>]*> 708e0067 s32lui xr1,-128,ptn1
+[0-9a-f]+ <[^>]*> 710e0067 s32lui xr1,-128,ptn2
+[0-9a-f]+ <[^>]*> 718e0067 s32lui xr1,-128,ptn3
+[0-9a-f]+ <[^>]*> 720e0067 s32lui xr1,-128,ptn4
+[0-9a-f]+ <[^>]*> 728e0067 s32lui xr1,-128,ptn5
+[0-9a-f]+ <[^>]*> 730e0067 s32lui xr1,-128,ptn6
+[0-9a-f]+ <[^>]*> 738e0067 s32lui xr1,-128,ptn7
+[0-9a-f]+ <[^>]*> 700ffc67 s32lui xr1,-1,ptn0
+[0-9a-f]+ <[^>]*> 708ffc67 s32lui xr1,-1,ptn1
+[0-9a-f]+ <[^>]*> 710ffc67 s32lui xr1,-1,ptn2
+[0-9a-f]+ <[^>]*> 718ffc67 s32lui xr1,-1,ptn3
+[0-9a-f]+ <[^>]*> 720ffc67 s32lui xr1,-1,ptn4
+[0-9a-f]+ <[^>]*> 728ffc67 s32lui xr1,-1,ptn5
+[0-9a-f]+ <[^>]*> 730ffc67 s32lui xr1,-1,ptn6
+[0-9a-f]+ <[^>]*> 738ffc67 s32lui xr1,-1,ptn7
+[0-9a-f]+ <[^>]*> 7010c867 s32nor xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7014c867 s32and xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 7018c867 s32or xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 701cc867 s32xor xr1,xr2,xr3
+[0-9a-f]+ <[^>]*> 70440428 lxb zero,v0,a0,2
+[0-9a-f]+ <[^>]*> 70440528 lxbu zero,v0,a0,2
+[0-9a-f]+ <[^>]*> 70440468 lxh zero,v0,a0,2
+[0-9a-f]+ <[^>]*> 70440568 lxhu zero,v0,a0,2
+[0-9a-f]+ <[^>]*> 704404e8 lxw zero,v0,a0,2
+[0-9a-f]+ <[^>]*> 7043fc6b s16std xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6b s16std xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7044006b s16std xr1,v0,-512,ptn0
+[0-9a-f]+ <[^>]*> 704c006b s16std xr1,v0,-512,ptn1
+[0-9a-f]+ <[^>]*> 7043fc6d s16sdi xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6d s16sdi xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7044006d s16sdi xr1,v0,-512,ptn0
+[0-9a-f]+ <[^>]*> 704c006d s16sdi xr1,v0,-512,ptn1
+[0-9a-f]+ <[^>]*> 7043fc6a s16ldd xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6a s16ldd xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7053fc6a s16ldd xr1,v0,510,ptn2
+[0-9a-f]+ <[^>]*> 705bfc6a s16ldd xr1,v0,510,ptn3
+[0-9a-f]+ <[^>]*> 7044006a s16ldd xr1,v0,-512,ptn0
+[0-9a-f]+ <[^>]*> 704c006a s16ldd xr1,v0,-512,ptn1
+[0-9a-f]+ <[^>]*> 7054006a s16ldd xr1,v0,-512,ptn2
+[0-9a-f]+ <[^>]*> 705c006a s16ldd xr1,v0,-512,ptn3
+[0-9a-f]+ <[^>]*> 7043fc6c s16ldi xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6c s16ldi xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7053fc6c s16ldi xr1,v0,510,ptn2
+[0-9a-f]+ <[^>]*> 705bfc6c s16ldi xr1,v0,510,ptn3
+[0-9a-f]+ <[^>]*> 7044006c s16ldi xr1,v0,-512,ptn0
+[0-9a-f]+ <[^>]*> 704c006c s16ldi xr1,v0,-512,ptn1
+[0-9a-f]+ <[^>]*> 7054006c s16ldi xr1,v0,-512,ptn2
+[0-9a-f]+ <[^>]*> 705c006c s16ldi xr1,v0,-512,ptn3
+[0-9a-f]+ <[^>]*> 7004006e s32m2i xr1,a0
+[0-9a-f]+ <[^>]*> 7004006f s32i2m xr1,a0
+[0-9a-f]+ <[^>]*> 70028052 s32lddv xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028452 s32lddvr xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028053 s32stdv xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028453 s32stdvr xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028056 s32ldiv xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028456 s32ldivr xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028057 s32sdiv xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 70028457 s32sdivr xr1,zero,v0,2
+[0-9a-f]+ <[^>]*> 7007fc50 s32ldd xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70080050 s32ldd xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7017fc50 s32lddr xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70180050 s32lddr xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7007fc51 s32std xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70080051 s32std xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7017fc51 s32stdr xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70180051 s32stdr xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7007fc54 s32ldi xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70080054 s32ldi xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7017fc54 s32ldir xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70180054 s32ldir xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7007fc55 s32sdi xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70080055 s32sdi xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7017fc55 s32sdir xr1,zero,2044
+[0-9a-f]+ <[^>]*> 70180055 s32sdir xr1,zero,-2048
+[0-9a-f]+ <[^>]*> 7041fc62 s8ldd xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc62 s8ldd xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc62 s8ldd xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc62 s8ldd xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 7051fc62 s8ldd xr1,v0,127,ptn4
+[0-9a-f]+ <[^>]*> 7055fc62 s8ldd xr1,v0,127,ptn5
+[0-9a-f]+ <[^>]*> 7059fc62 s8ldd xr1,v0,127,ptn6
+[0-9a-f]+ <[^>]*> 705dfc62 s8ldd xr1,v0,127,ptn7
+[0-9a-f]+ <[^>]*> 70420062 s8ldd xr1,v0,-128,ptn0
+[0-9a-f]+ <[^>]*> 70460062 s8ldd xr1,v0,-128,ptn1
+[0-9a-f]+ <[^>]*> 704a0062 s8ldd xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0062 s8ldd xr1,v0,-128,ptn3
+[0-9a-f]+ <[^>]*> 70520062 s8ldd xr1,v0,-128,ptn4
+[0-9a-f]+ <[^>]*> 70560062 s8ldd xr1,v0,-128,ptn5
+[0-9a-f]+ <[^>]*> 705a0062 s8ldd xr1,v0,-128,ptn6
+[0-9a-f]+ <[^>]*> 705e0062 s8ldd xr1,v0,-128,ptn7
+[0-9a-f]+ <[^>]*> 7041fc64 s8ldi xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc64 s8ldi xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc64 s8ldi xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc64 s8ldi xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 7051fc64 s8ldi xr1,v0,127,ptn4
+[0-9a-f]+ <[^>]*> 7055fc64 s8ldi xr1,v0,127,ptn5
+[0-9a-f]+ <[^>]*> 7059fc64 s8ldi xr1,v0,127,ptn6
+[0-9a-f]+ <[^>]*> 705dfc64 s8ldi xr1,v0,127,ptn7
+[0-9a-f]+ <[^>]*> 70420064 s8ldi xr1,v0,-128,ptn0
+[0-9a-f]+ <[^>]*> 70460064 s8ldi xr1,v0,-128,ptn1
+[0-9a-f]+ <[^>]*> 704a0064 s8ldi xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0064 s8ldi xr1,v0,-128,ptn3
+[0-9a-f]+ <[^>]*> 70520064 s8ldi xr1,v0,-128,ptn4
+[0-9a-f]+ <[^>]*> 70560064 s8ldi xr1,v0,-128,ptn5
+[0-9a-f]+ <[^>]*> 705a0064 s8ldi xr1,v0,-128,ptn6
+[0-9a-f]+ <[^>]*> 705e0064 s8ldi xr1,v0,-128,ptn7
+[0-9a-f]+ <[^>]*> 7041fc63 s8std xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc63 s8std xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc63 s8std xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc63 s8std xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 70420063 s8std xr1,v0,-128,ptn0
+[0-9a-f]+ <[^>]*> 70460063 s8std xr1,v0,-128,ptn1
+[0-9a-f]+ <[^>]*> 704a0063 s8std xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0063 s8std xr1,v0,-128,ptn3
+[0-9a-f]+ <[^>]*> 7041fc65 s8sdi xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc65 s8sdi xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc65 s8sdi xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc65 s8sdi xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 70420065 s8sdi xr1,v0,-128,ptn0
+[0-9a-f]+ <[^>]*> 70460065 s8sdi xr1,v0,-128,ptn1
+[0-9a-f]+ <[^>]*> 704a0065 s8sdi xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0065 s8sdi xr1,v0,-128,ptn3
+ \.\.\.
diff --git a/binutils-2.25/gas/testsuite/gas/mips/mxu.s b/binutils-2.25/gas/testsuite/gas/mips/mxu.s
new file mode 100644
index 0000000..7650451
--- /dev/null
+++ b/binutils-2.25/gas/testsuite/gas/mips/mxu.s
@@ -0,0 +1,340 @@
+ .text
+ .set noat
+ .set noreorder
+ .set nomacro
+test_mxu:
+
+.macro test1 insn
+ \insn xr1, xr2, xr3, xr4,AA,WW
+ \insn xr1, xr2, xr3, xr4,AA,LW
+ \insn xr1, xr2, xr3, xr4,AA,HW
+ \insn xr1, xr2, xr3, xr4,AA,XW
+
+ \insn xr1, xr2, xr3, xr4,AA,0
+ \insn xr1, xr2, xr3, xr4,AA,1
+ \insn xr1, xr2, xr3, xr4,AA,2
+ \insn xr1, xr2, xr3, xr4,AA,3
+
+ \insn xr1, xr2, xr3, xr4,AS,WW
+ \insn xr1, xr2, xr3, xr4,AS,LW
+ \insn xr1, xr2, xr3, xr4,AS,HW
+ \insn xr1, xr2, xr3, xr4,AS,XW
+
+ \insn xr1, xr2, xr3, xr4,AS,0
+ \insn xr1, xr2, xr3, xr4,AS,1
+ \insn xr1, xr2, xr3, xr4,AS,2
+ \insn xr1, xr2, xr3, xr4,AS,3
+
+ \insn xr1, xr2, xr3, xr4,SA,WW
+ \insn xr1, xr2, xr3, xr4,SA,LW
+ \insn xr1, xr2, xr3, xr4,SA,HW
+ \insn xr1, xr2, xr3, xr4,SA,XW
+
+ \insn xr1, xr2, xr3, xr4,SA,0
+ \insn xr1, xr2, xr3, xr4,SA,1
+ \insn xr1, xr2, xr3, xr4,SA,2
+ \insn xr1, xr2, xr3, xr4,SA,3
+
+ \insn xr1, xr2, xr3, xr4,SS,WW
+ \insn xr1, xr2, xr3, xr4,SS,LW
+ \insn xr1, xr2, xr3, xr4,SS,HW
+ \insn xr1, xr2, xr3, xr4,SS,XW
+
+ \insn xr1, xr2, xr3, xr4,SS,0
+ \insn xr1, xr2, xr3, xr4,SS,1
+ \insn xr1, xr2, xr3, xr4,SS,2
+ \insn xr1, xr2, xr3, xr4,SS,3
+.endm
+
+.macro test2 insn
+ \insn xr1, xr2, xr3, xr4, AA
+ \insn xr1, xr2, xr3, xr4, SA
+ \insn xr1, xr2, xr3, xr4, AS
+ \insn xr1, xr2, xr3, xr4, SS
+.endm
+
+.macro test3 insn
+ \insn xr1, $2,510, ptn0
+ \insn xr1, $2,510, ptn1
+
+ \insn xr1, $2,-512, ptn0
+ \insn xr1, $2,-512, ptn1
+.endm
+
+.macro test4 insn
+ \insn xr1, $2,510, ptn0
+ \insn xr1, $2,510, ptn1
+ \insn xr1, $2,510, ptn2
+ \insn xr1, $2,510, ptn3
+
+ \insn xr1, $2,-512, ptn0
+ \insn xr1, $2,-512, ptn1
+ \insn xr1, $2,-512, ptn2
+ \insn xr1, $2,-512, ptn3
+.endm
+
+.macro test5 insn
+ \insn xr1, $2,127, ptn0
+ \insn xr1, $2,127, ptn1
+ \insn xr1, $2,127, ptn2
+ \insn xr1, $2,127, ptn3
+ \insn xr1, $2,127, ptn4
+ \insn xr1, $2,127, ptn5
+ \insn xr1, $2,127, ptn6
+ \insn xr1, $2,127, ptn7
+
+ \insn xr1, $2,-128, ptn0
+ \insn xr1, $2,-128, ptn1
+ \insn xr1, $2,-128, ptn2
+ \insn xr1, $2,-128, ptn3
+ \insn xr1, $2,-128, ptn4
+ \insn xr1, $2,-128, ptn5
+ \insn xr1, $2,-128, ptn6
+ \insn xr1, $2,-128, ptn7
+.endm
+
+.macro test6 insn
+ \insn xr1, $2,127, ptn0
+ \insn xr1, $2,127, ptn1
+ \insn xr1, $2,127, ptn2
+ \insn xr1, $2,127, ptn3
+
+ \insn xr1, $2,-128, ptn0
+ \insn xr1, $2,-128, ptn1
+ \insn xr1, $2,-128, ptn2
+ \insn xr1, $2,-128, ptn3
+.endm
+ mfc1 $2, $2
+ mfc1 $2, $f1
+ mtc1 $2, $2
+ mtc1 $2, $f1
+ mfhc1 $2, $2
+ mfhc1 $2, $f2
+ mthc1 $2, $2
+ mthc1 $2, $f2
+ test1 d16mac
+ test1 d16macf
+ test1 d16madl
+ test1 q16add
+ test1 d16mace
+
+ d16mul xr1, xr2, xr3, xr4,WW
+ d16mul xr1, xr2, xr3, xr4,LW
+ d16mul xr1, xr2, xr3, xr4,HW
+ d16mul xr1, xr2, xr3, xr4,XW
+
+ d16mul xr1, xr2, xr3, xr4,0
+ d16mul xr1, xr2, xr3, xr4,1
+ d16mul xr1, xr2, xr3, xr4,2
+ d16mul xr1, xr2, xr3, xr4,3
+
+ d16mulf xr1, xr2, xr3, WW
+ d16mulf xr1, xr2, xr3, LW
+ d16mulf xr1, xr2, xr3, HW
+ d16mulf xr1, xr2, xr3, XW
+
+ d16mulf xr1, xr2, xr3, 0
+ d16mulf xr1, xr2, xr3, 1
+ d16mulf xr1, xr2, xr3, 2
+ d16mulf xr1, xr2, xr3, 3
+
+ d16mule xr1, xr2, xr3, WW
+ d16mule xr1, xr2, xr3, LW
+ d16mule xr1, xr2, xr3, HW
+ d16mule xr1, xr2, xr3, XW
+
+ d16mule xr1, xr2, xr3, 0
+ d16mule xr1, xr2, xr3, 1
+ d16mule xr1, xr2, xr3, 2
+ d16mule xr1, xr2, xr3, 3
+
+ s16mad xr1, xr2, xr3, xr4,A,WW
+ s16mad xr1, xr2, xr3, xr4,A,LW
+ s16mad xr1, xr2, xr3, xr4,A,HW
+ s16mad xr1, xr2, xr3, xr4,A,XW
+
+ s16mad xr1, xr2, xr3, xr4,A,0
+ s16mad xr1, xr2, xr3, xr4,A,1
+ s16mad xr1, xr2, xr3, xr4,A,2
+ s16mad xr1, xr2, xr3, xr4,A,3
+
+ s16mad xr1, xr2, xr3, xr4,S,WW
+ s16mad xr1, xr2, xr3, xr4,S,LW
+ s16mad xr1, xr2, xr3, xr4,S,HW
+ s16mad xr1, xr2, xr3, xr4,S,XW
+
+ s16mad xr1, xr2, xr3, xr4,S,0
+ s16mad xr1, xr2, xr3, xr4,S,1
+ s16mad xr1, xr2, xr3, xr4,S,2
+ s16mad xr1, xr2, xr3, xr4,S,3
+
+ q8mul xr1, xr2, xr3, xr4
+ q8mulsu xr1, xr2, xr3, xr4
+ q8movz xr1, xr2, xr3
+ q8movn xr1, xr2, xr3
+ d16movz xr1, xr2, xr3
+ d16movn xr1, xr2, xr3
+ s32movz xr1, xr2, xr3
+ s32movn xr1, xr2, xr3
+
+ test2 q8mac
+ test2 q8macsu
+
+ q16scop xr1, xr2, xr3, xr4
+
+ test2 q8madl
+
+ s32sfl xr1, xr2, xr3, xr4, ptn0
+ s32sfl xr1, xr2, xr3, xr4, ptn1
+ s32sfl xr1, xr2, xr3, xr4, ptn2
+ s32sfl xr1, xr2, xr3, xr4, ptn3
+
+ q8sad xr1, xr2, xr3, xr4
+
+ test2 d32add
+
+ d32addc xr1, xr2, xr3, xr4
+
+ test2 d32acc
+ test2 d32accm
+ test2 d32asum
+ test2 q16acc
+ test2 q16accm
+ test2 d16asum
+ test2 q8adde
+
+ d8sum xr1, xr2, xr3
+ d8sumc xr1, xr2, xr3
+ test2 q8acce
+
+ s32cps xr1, xr2, xr3
+ d16cps xr1, xr2, xr3
+ q8abd xr1, xr2, xr3
+ q16sat xr1, xr2, xr3
+
+ s32slt xr1, xr2, xr3
+ d16slt xr1, xr2, xr3
+ d16avg xr1, xr2, xr3
+ d16avgr xr1, xr2, xr3
+ q8avg xr1, xr2, xr3
+ q8avgr xr1, xr2, xr3
+ q8add xr1, xr2, xr3,AA
+ q8add xr1, xr2, xr3,AS
+ q8add xr1, xr2, xr3,SA
+ q8add xr1, xr2, xr3,SS
+
+ s32max xr1, xr2, xr3
+ s32min xr1, xr2, xr3
+ d16max xr1, xr2, xr3
+ d16min xr1, xr2, xr3
+ q8max xr1, xr2, xr3
+ q8min xr1, xr2, xr3
+ q8slt xr1, xr2, xr3
+ q8sltu xr1, xr2, xr3
+
+ d32sll xr0, xr2, xr3, xr4, 15
+ d32slr xr1, xr2, xr3, xr4, 15
+ d32sarl xr1, xr2, xr3, 15
+ d32sar xr1, xr2, xr3, xr4, 15
+ q16sll xr1, xr2, xr3, xr4, 15
+ q16slr xr1, xr2, xr3, xr4, 15
+ q16sar xr1, xr2, xr3, xr4, 15
+
+ d32sllv xr1, xr2, $0
+ d32slrv xr1, xr2, $0
+ d32sarv xr1, xr2, $0
+ q16sllv xr1, xr2, $0
+ q16slrv xr1, xr2, $0
+ q16sarv xr1, xr2, $0
+
+ s32madd xr1, xr2, $0, $2
+ s32maddu xr1, xr2, $0, $2
+ s32msub xr1, xr2, $0, $2
+ s32msubu xr1, xr2, $0, $2
+ s32mul xr1, xr2, $0, $2
+ s32mulu xr1, xr2, $0, $2
+ s32extrv xr1, xr2, $0, $2
+ s32extr xr1, xr2, $0, 31
+
+ d32sarw xr1, xr2, xr3, $0
+ s32aln xr1, xr2, xr3, $0
+ s32alni xr1, xr2, xr3, ptn0
+ s32alni xr1, xr2, xr3, ptn1
+ s32alni xr1, xr2, xr3, ptn2
+ s32alni xr1, xr2, xr3, ptn3
+ s32alni xr1, xr2, xr3, ptn4
+ s32lui xr1, 127, ptn0
+ s32lui xr1, 127, ptn1
+ s32lui xr1, 127, ptn2
+ s32lui xr1, 127, ptn3
+ s32lui xr1, 127, ptn4
+ s32lui xr1, 127, ptn5
+ s32lui xr1, 127, ptn6
+ s32lui xr1, 127, ptn7
+ s32lui xr1, -128, ptn0
+ s32lui xr1, -128, ptn1
+ s32lui xr1, -128, ptn2
+ s32lui xr1, -128, ptn3
+ s32lui xr1, -128, ptn4
+ s32lui xr1, -128, ptn5
+ s32lui xr1, -128, ptn6
+ s32lui xr1, -128, ptn7
+ s32lui xr1, 255, ptn0
+ s32lui xr1, 255, ptn1
+ s32lui xr1, 255, ptn2
+ s32lui xr1, 255, ptn3
+ s32lui xr1, 255, ptn4
+ s32lui xr1, 255, ptn5
+ s32lui xr1, 255, ptn6
+ s32lui xr1, 255, ptn7
+ s32nor xr1, xr2, xr3
+ s32and xr1, xr2, xr3
+ s32or xr1, xr2, xr3
+ s32xor xr1, xr2, xr3
+
+ lxb $0, $2, $4, 2
+ lxbu $0, $2, $4, 2
+ lxh $0, $2, $4, 2
+ lxhu $0, $2, $4, 2
+ lxw $0, $2, $4, 2
+
+ test3 s16std
+ test3 s16sdi
+ test4 s16ldd
+ test4 s16ldi
+
+ s32m2i xr1, $4
+ s32i2m xr1, $4
+
+ s32lddv xr1, $0, $2, 2
+ s32lddvr xr1, $0, $2, 2
+ s32stdv xr1, $0, $2, 2
+ s32stdvr xr1, $0, $2, 2
+ s32ldiv xr1, $0, $2, 2
+ s32ldivr xr1, $0, $2, 2
+ s32sdiv xr1, $0, $2, 2
+ s32sdivr xr1, $0, $2, 2
+ s32ldd xr1, $0, 2044
+ s32ldd xr1, $0, -2048
+ s32lddr xr1, $0, 2044
+ s32lddr xr1, $0, -2048
+ s32std xr1, $0, 2044
+ s32std xr1, $0, -2048
+ s32stdr xr1, $0, 2044
+ s32stdr xr1, $0, -2048
+ s32ldi xr1, $0, 2044
+ s32ldi xr1, $0, -2048
+ s32ldir xr1, $0, 2044
+ s32ldir xr1, $0, -2048
+ s32sdi xr1, $0, 2044
+ s32sdi xr1, $0, -2048
+ s32sdir xr1, $0, 2044
+ s32sdir xr1, $0, -2048
+
+ test5 s8ldd
+ test5 s8ldi
+ test6 s8std
+ test6 s8sdi
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff --git a/binutils-2.25/include/elf/mips.h b/binutils-2.25/include/elf/mips.h
index 2ed6acd..a76dae7 100644
--- a/binutils-2.25/include/elf/mips.h
+++ b/binutils-2.25/include/elf/mips.h
@@ -1224,7 +1224,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */
#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */
#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
-#define AFL_ASE_MASK 0x00001fff /* All ASEs. */
+#define AFL_ASE_DSPR6 0x00002000 /* DSP R6 ASE. */
+#define AFL_ASE_MASK 0x00003fff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
diff --git a/binutils-2.25/include/opcode/mips.h b/binutils-2.25/include/opcode/mips.h
index ef26167..2882699 100644
--- a/binutils-2.25/include/opcode/mips.h
+++ b/binutils-2.25/include/opcode/mips.h
@@ -427,7 +427,10 @@ enum mips_operand_type {
OP_CHECK_PREV,
/* A register operand that must not be zero. */
- OP_NON_ZERO_REG
+ OP_NON_ZERO_REG,
+
+ OP_MAPPED_STRING,
+ OP_MXU_STRIDE
};
/* Enumerates the types of MIPS register. */
@@ -474,7 +477,11 @@ enum mips_reg_operand_type {
OP_REG_MSA,
/* MSA control registers $0-$31. */
- OP_REG_MSA_CTRL
+ OP_REG_MSA_CTRL,
+
+ OP_REG_MXU,
+
+ OP_REG_MXU_GP
};
/* Base class for all operands. */
@@ -527,6 +534,12 @@ struct mips_mapped_int_operand
bfd_boolean print_hex;
};
+struct mips_mapped_string_operand
+{
+ struct mips_operand root;
+ const char ** strings;
+ int allow_constants;
+};
/* An operand that encodes the most significant bit position of a bitfield.
Given a bitfield that spans bits [MSB, LSB], some operands of this type
encode MSB directly while others encode MSB - LSB. Each operand of this
@@ -993,6 +1006,11 @@ struct mips_opcode
following), for quick reference when adding more:
"AB"
"abdstuvwxy"
+
+ Extension character sequences used so far ("`" followed by the
+ following), for quick reference when adding more:
+ "ABEIOPTRSU"
+ "abcdefgimopr"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -1102,6 +1120,8 @@ struct mips_opcode
#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
/* Instruction has a forbidden slot. */
#define INSN2_FORBIDDEN_SLOT 0x00008000
+/* This indicates pre-R6 instructions mapped to R6 ones. */
+#define INSN2_CONVERTED_TO_COMPACT 0x00010000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
@@ -1255,6 +1275,9 @@ static const unsigned int mips_isa_table[] = {
#define ASE_MSA64 0x00001000
/* eXtended Physical Address (XPA) Extension. */
#define ASE_XPA 0x00002000
+/* MXU Extension. */
+#define ASE_MXU 0x00004000
+#define ASE_DSPR6 0x00008000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
diff --git a/binutils-2.25/ld/configure.tgt b/binutils-2.25/ld/configure.tgt
index 24e36d1..828e139 100644
--- a/binutils-2.25/ld/configure.tgt
+++ b/binutils-2.25/ld/configure.tgt
@@ -476,6 +476,9 @@ mips*el-*-vxworks*) targ_emul=elf32elmipvxworks
mips*-*-vxworks*) targ_emul=elf32ebmipvxworks
targ_extra_emuls="elf32elmipvxworks" ;;
mips*-*-windiss) targ_emul=elf32mipswindiss ;;
+mips64*el-*android*) targ_emul=elf64ltsmip
+ targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip"
+ targ_extra_libpath=$targ_extra_emuls ;;
mips64*el-*-linux-*) targ_emul=elf32ltsmipn32
targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip"
targ_extra_libpath=$targ_extra_emuls ;;
diff --git a/binutils-2.25/ld/emultempl/mipself.em b/binutils-2.25/ld/emultempl/mipself.em
index b6e17ce..b3458ae 100644
--- a/binutils-2.25/ld/emultempl/mipself.em
+++ b/binutils-2.25/ld/emultempl/mipself.em
@@ -34,6 +34,7 @@ static lang_input_statement_type *stub_file;
static bfd *stub_bfd;
static bfd_boolean insn32;
+static bfd_boolean compact_branches;
static void
mips_after_parse (void)
@@ -205,7 +206,10 @@ mips_create_output_section_statements (void)
_bfd_mips_elf_insn32 (&link_info, insn32);
if (is_mips_elf (link_info.output_bfd))
- _bfd_mips_elf_init_stubs (&link_info, mips_add_stub_section);
+ {
+ _bfd_mips_elf_compact_branches (&link_info, compact_branches);
+ _bfd_mips_elf_init_stubs (&link_info, mips_add_stub_section);
+ }
}
/* This is called after we have merged the private data of the input bfds. */
@@ -252,11 +256,15 @@ EOF
PARSE_AND_LIST_PROLOGUE='
#define OPTION_INSN32 301
#define OPTION_NO_INSN32 (OPTION_INSN32 + 1)
+#define OPTION_COMPACT_BRANCHES (OPTION_NO_INSN32 + 1)
+#define OPTION_NO_COMPACT_BRANCHES (OPTION_COMPACT_BRANCHES + 1)
'
PARSE_AND_LIST_LONGOPTS='
{ "insn32", no_argument, NULL, OPTION_INSN32 },
{ "no-insn32", no_argument, NULL, OPTION_NO_INSN32 },
+ { "compact-branches", no_argument, NULL, OPTION_COMPACT_BRANCHES },
+ { "no-compact-branches", no_argument, NULL, OPTION_NO_COMPACT_BRANCHES },
'
PARSE_AND_LIST_OPTIONS='
@@ -266,6 +274,12 @@ PARSE_AND_LIST_OPTIONS='
fprintf (file, _("\
--no-insn32 Generate all microMIPS instructions\n"
));
+ fprintf (file, _("\
+ --compact-branches Generate compact branches/jumps for MIPS R6\n"
+ ));
+ fprintf (file, _("\
+ --no-compact-branches Generate delay slot branches/jumps for MIPS R6\n"
+ ));
'
PARSE_AND_LIST_ARGS_CASES='
@@ -276,6 +290,14 @@ PARSE_AND_LIST_ARGS_CASES='
case OPTION_NO_INSN32:
insn32 = FALSE;
break;
+
+ case OPTION_COMPACT_BRANCHES:
+ compact_branches = TRUE;
+ break;
+
+ case OPTION_NO_COMPACT_BRANCHES:
+ compact_branches = FALSE;
+ break;
'
LDEMUL_AFTER_PARSE=mips_after_parse
diff --git a/binutils-2.25/ld/ld.texinfo b/binutils-2.25/ld/ld.texinfo
index bb386e4..43973cc 100644
--- a/binutils-2.25/ld/ld.texinfo
+++ b/binutils-2.25/ld/ld.texinfo
@@ -2819,6 +2819,13 @@ or in relaxation. If @samp{--insn32} is used, then the linker only uses
used, all instruction encodings are used, including 16-bit ones where
possible.
+@kindex --compact-branches
+@item --compact-branches
+@kindex --no-compact-branches
+@item --compact-branches
+These options control the generation of compact instructions by the linker
+in the PLT entries for MIPS R6.
+
@end table
@c man end
diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp b/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp
index 91036de..21c809f 100644
--- a/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp
+++ b/binutils-2.25/ld/testsuite/ld-mips-elf/mips-elf.exp
@@ -434,6 +434,13 @@ if {$linux_gnu} {
run_dump_test "jaloverflow"
run_dump_test "jaloverflow-2"
+run_dump_test "undefweak-overflow"
+
+if {$has_newabi} {
+ run_dump_test "undefweak-overflow-n32"
+ run_dump_test "undefweak-overflow-n64"
+}
+
if {$has_newabi} {
run_dump_test "jalbal" [list [list ld $abi_ldflags(n32)]]
}
diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d
new file mode 100644
index 0000000..4d965b8
--- /dev/null
+++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n32.d
@@ -0,0 +1,23 @@
+#name: undefined weak symbol overflow (n32)
+#source: undefweak-overflow.s
+#as: -n32 -EB
+#ld: -melf32btsmipn32 -Ttext=0x20000000 -e start
+#objdump: -dr
+#...
+0*20000000: d85fffff.*
+0*20000004: 00000000.*
+0*20000008: f85ffffd.*
+0*2000000c: ec4ffffd.*
+0*20000010: ec5bfffe.*
+0*20000014: cbfffffa.*
+0*20000018: 3c04e000.*
+0*2000001c: 1000fff8.*
+0*20000020: 2484ffe0.*
+0*20000024: 0411fff6.*
+0*20000028: 00000000.*
+0*2000002c: 3c047fd0.*
+0*20000030: 8e670c00.*
+0*20000034: cfe50c00.*
+0*20000038: 9400ffe2.*
+0*2000003c: 0c000c00.*
+#pass
diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d
new file mode 100644
index 0000000..e0d9fda
--- /dev/null
+++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow-n64.d
@@ -0,0 +1,23 @@
+#name: undefined weak symbol overflow (n64)
+#source: undefweak-overflow.s
+#as: -64 -EB
+#ld: -melf64btsmip -Ttext=0x20000000 -e start
+#objdump: -dr
+#...
+ 0*20000000: d85fffff.*
+ 0*20000004: 00000000.*
+ 0*20000008: f85ffffd.*
+ 0*2000000c: ec4ffffd.*
+ 0*20000010: ec5bfffe.*
+ 0*20000014: cbfffffa.*
+ 0*20000018: 3c04e000.*
+ 0*2000001c: 1000fff8.*
+ 0*20000020: 2484ffe0.*
+ 0*20000024: 0411fff6.*
+ 0*20000028: 00000000.*
+ 0*2000002c: 3c047fd0.*
+ 0*20000030: 8e670c00.*
+ 0*20000034: cfe50c00.*
+ 0*20000038: 9400ffe2.*
+ 0*2000003c: 0c000c00.*
+#pass
diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d
new file mode 100644
index 0000000..18b3a90
--- /dev/null
+++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.d
@@ -0,0 +1,23 @@
+#name: undefined weak symbol overflow
+#source: undefweak-overflow.s
+#as: -32 -EB
+#ld: -melf32btsmip -Ttext=0x20000000 -e start
+#objdump: -dr
+#...
+0*20000000: d85fffff.*
+0*20000004: 00000000.*
+0*20000008: f85ffffd.*
+0*2000000c: ec4ffffd.*
+0*20000010: ec5bfffe.*
+0*20000014: cbfffffa.*
+0*20000018: 3c04e000.*
+0*2000001c: 1000fff8.*
+0*20000020: 2484ffe0.*
+0*20000024: 0411fff6.*
+0*20000028: 00000000.*
+0*2000002c: 3c047fd0.*
+0*20000030: 8e670c00.*
+0*20000034: cfe50c00.*
+0*20000038: 9400ffe2.*
+0*2000003c: 0c000c00.*
+#pass
diff --git a/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s
new file mode 100644
index 0000000..525f11b
--- /dev/null
+++ b/binutils-2.25/ld/testsuite/ld-mips-elf/undefweak-overflow.s
@@ -0,0 +1,25 @@
+# relocs against undefined weak symbols should not be treated as
+# overflowing
+
+
+ .globl start
+ .weak foo
+start:
+ .set mips64r6
+ beqzc $2, foo
+ bnezc $2, foo
+ lwpc $2, foo
+ ldpc $2, foo
+ bc foo
+ lui $4, %pcrel_hi(foo)
+ addiu $4, $4, %pcrel_lo(foo)
+
+ .set mips32r2
+ b foo
+ bal foo
+ lui $4, %gp_rel(foo)
+
+ .set micromips
+ beqz16 $4, foo
+ b16 foo
+ b foo
diff --git a/binutils-2.25/opcodes/mips-dis.c b/binutils-2.25/opcodes/mips-dis.c
index 1eb1d45..426d06f 100644
--- a/binutils-2.25/opcodes/mips-dis.c
+++ b/binutils-2.25/opcodes/mips-dis.c
@@ -73,6 +73,12 @@ static const char * const mips_gpr_names_newabi[32] =
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
+static const char * const mips_gpr_names_xr[17] = {
+ "xr0", "xr1", "xr2", "xr3", "xr4", "xr5", "xr6", "xr7",
+ "xr8", "xr9", "xr10", "xr11", "xr12", "xr13", "xr14", "xr15",
+ "xr16"
+};
+
static const char * const mips_fpr_names_numeric[32] =
{
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
@@ -543,7 +549,7 @@ const struct mips_arch_choice mips_arch_choices[] =
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
- ISA_MIPS32, ASE_SMARTMIPS,
+ ISA_MIPS32, ASE_SMARTMIPS | ASE_MXU,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_cp1_names_mips3264, mips_hwr_names_numeric },
@@ -551,7 +557,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
- | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -559,7 +565,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3,
ISA_MIPS32R3,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
- | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -567,7 +573,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5,
ISA_MIPS32R5,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
- | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -575,14 +581,14 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
- | ASE_DSPR2),
+ | ASE_DSPR2 | ASE_DSPR6),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
- ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
+ ISA_MIPS64, ASE_MIPS3D | ASE_MDMX | ASE_MXU,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_cp1_names_mips3264, mips_hwr_names_numeric },
@@ -590,7 +596,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
ISA_MIPS64R2,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
- | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA
+ | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -598,7 +605,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3,
ISA_MIPS64R3,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
- | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA
+ | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -606,7 +614,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5,
ISA_MIPS64R5,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
- | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA
+ | ASE_MXU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -614,7 +623,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
- | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2),
+ | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR6 | ASE_DSP64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -771,6 +780,17 @@ is_micromips (Elf_Internal_Ehdr *header)
return 0;
}
+/* Check if ISA is R6. */
+
+static inline int
+is_isa_r6 (unsigned long isa)
+{
+ if ((isa & INSN_ISA_MASK) == ISA_MIPS32R6
+ || ((isa & INSN_ISA_MASK) == ISA_MIPS64R6))
+ return 1;
+ return 0;
+}
+
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
@@ -871,6 +891,11 @@ parse_mips_dis_option (const char *option, unsigned int len)
return;
}
+ if (CONST_STRNEQ (option, "mxu"))
+ {
+ mips_ase |= ASE_MXU;
+ return;
+ }
/* Look for the = that delimits the end of the option name. */
for (i = 0; i < len; i++)
@@ -1017,6 +1042,11 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
{
switch (type)
{
+ case OP_REG_MXU:
+ case OP_REG_MXU_GP:
+ info->fprintf_func (info->stream, "%s", mips_gpr_names_xr[regno]);
+ break;
+
case OP_REG_GP:
info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]);
break;
@@ -1167,6 +1197,13 @@ print_insn_arg (struct disassemble_info *info,
switch (operand->type)
{
+ case OP_MAPPED_STRING:
+ {
+ const struct mips_mapped_string_operand *string_op;
+ string_op = (const struct mips_mapped_string_operand *) operand;
+ infprintf (is, "%s", string_op->strings[uval]);
+ }
+ break;
case OP_INT:
{
const struct mips_int_operand *int_op;
@@ -1429,6 +1466,10 @@ print_insn_arg (struct disassemble_info *info,
infprintf (is, "[%d]", uval);
break;
+ case OP_MXU_STRIDE:
+ infprintf (is, "%d", uval);
+ break;
+
case OP_REG_INDEX:
infprintf (is, "[");
print_reg (info, opcode, OP_REG_GP, uval);
@@ -1537,6 +1578,8 @@ validate_insn_args (const struct mips_opcode *opcode,
case OP_VU0_MATCH_SUFFIX:
case OP_IMM_INDEX:
case OP_REG_INDEX:
+ case OP_MXU_STRIDE:
+ case OP_MAPPED_STRING:
break;
case OP_SAVE_RESTORE_LIST:
@@ -1544,7 +1587,7 @@ validate_insn_args (const struct mips_opcode *opcode,
abort ();
}
}
- if (*s == 'm' || *s == '+' || *s == '-')
+ if (*s == 'm' || *s == '+' || *s == '-' || *s == '`')
++s;
}
}
@@ -1642,7 +1685,7 @@ print_insn_args (struct disassemble_info *info,
print_insn_arg (info, &state, opcode, operand, base_pc,
mips_extract_operand (operand, insn));
}
- if (*s == 'm' || *s == '+' || *s == '-')
+ if (*s == 'm' || *s == '+' || *s == '-' || *s == '`')
++s;
break;
}
@@ -1709,10 +1752,10 @@ print_insn_mips (bfd_vma memaddr,
&& (word & op->mask) == op->match)
{
/* We always disassemble the jalx instruction, except for MIPS r6. */
- if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
- && (strcmp (op->name, "jalx")
- || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6
- || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6))
+ if ((!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
+ && (strcmp (op->name, "jalx") || is_isa_r6 (mips_isa)))
+ || (is_isa_r6 (op->membership)
+ && (op->pinfo2 & INSN2_CONVERTED_TO_COMPACT)))
continue;
/* Figure out instruction type and branch delay information. */
@@ -2428,6 +2471,9 @@ with the -M switch (multiple options should be separated by commas):\n"));
xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n"));
fprintf (stream, _("\n\
+ mxu Recognize the MXU ASE instructions.\n"));
+
+ fprintf (stream, _("\n\
gpr-names=ABI Print GPR names according to specified ABI.\n\
Default: based on binary being disassembled.\n"));
diff --git a/binutils-2.25/opcodes/mips-formats.h b/binutils-2.25/opcodes/mips-formats.h
index 116d7c8..9c265a5 100644
--- a/binutils-2.25/opcodes/mips-formats.h
+++ b/binutils-2.25/opcodes/mips-formats.h
@@ -53,6 +53,16 @@
return &op.root; \
}
+#define MAPPED_STRING(SIZE, LSB, MAP, ALLOW_CONSTANTS) \
+ { \
+ typedef char ATTRIBUTE_UNUSED \
+ static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
+ static const struct mips_mapped_string_operand op = { \
+ { OP_MAPPED_STRING, SIZE, LSB }, MAP, ALLOW_CONSTANTS \
+ }; \
+ return &op.root; \
+ }
+
#define MSB(SIZE, LSB, BIAS, ADD_LSB, OPSIZE) \
{ \
static const struct mips_msb_operand op = { \
diff --git a/binutils-2.25/opcodes/mips-opc.c b/binutils-2.25/opcodes/mips-opc.c
index 0e9f716..1871a85 100644
--- a/binutils-2.25/opcodes/mips-opc.c
+++ b/binutils-2.25/opcodes/mips-opc.c
@@ -31,6 +31,31 @@
/* The 4-bit XYZW mask used in some VU0 instructions. */
const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21 };
+const char * mxu_s32mad[] = {"A", "S"};
+
+const char * mxu_optn[] = {"WW", "LW", "HW", "XW"};
+
+const char * mxu_aptn[] = {"AA", "AS", "SA", "SS"};
+
+const char * mxu_ptn_7[] = {
+ "ptn0", "ptn1", "ptn2", "ptn3",
+ "ptn4", "ptn5", "ptn6", "ptn7"
+};
+
+const char * mxu_ptn_4[] = {
+ "ptn0", "ptn1", "ptn2", "ptn3",
+ "ptn4", "", "", ""
+};
+
+const char * mxu_ptn_1[] = {
+ "ptn0", "ptn1", "", "",
+};
+
+const char * mxu_ptn_3[] = {
+ "ptn0", "ptn1", "ptn2", "ptn3",
+ "", "", "", ""
+};
+
static unsigned char reg_0_map[] = { 0 };
/* Return the mips_operand structure for the operand at the beginning of P. */
@@ -58,6 +83,35 @@ decode_mips_operand (const char *p)
}
break;
+ case '`':
+ switch (p[1])
+ {
+ case 'm': REG (5, 6, MXU);
+ case '=': REG (4, 6, MXU);
+ case 'a': MAPPED_STRING (2, 24, mxu_aptn, 0);
+ case 'b': REG (4, 10, MXU_GP);
+ case 'c': REG (4, 14, MXU_GP);
+ case 'd': REG (4, 18, MXU_GP);
+ case 'e': MAPPED_STRING (3, 18, mxu_ptn_7, 1)
+ case 'g': MAPPED_STRING (3, 18, mxu_ptn_3, 0)
+ case 'f': UINT (4, 22);
+ case 'i': INT_ADJ (10, 10, 511, 2, FALSE);
+ case 'o': MAPPED_STRING (2, 22, mxu_optn, 1);
+ case 'P': MAPPED_STRING (2, 19, mxu_ptn_3, 0);
+ case 'p': MAPPED_STRING (2, 19, mxu_ptn_1, 0);
+ case 'r': SPECIAL (2, 14, MXU_STRIDE);
+ case 'R': SPECIAL (2, 9, MXU_STRIDE);
+ case 'A': MAPPED_STRING (1, 24, mxu_s32mad, 0);
+ case 'B': SINT (8, 10);
+ case 'U': UINT (8, 10);
+ case 'E': MAPPED_STRING (2, 24, mxu_ptn_3, 0);
+ case 'I': INT_ADJ (9, 10, 255, 1, FALSE);
+ case 'S': MAPPED_STRING (3, 23, mxu_ptn_4, 0);
+ case 'O': MAPPED_STRING (3, 23, mxu_ptn_7, 1);
+ case 'T': UINT (5, 16);
+ }
+ break;
+
case '+':
switch (p[1])
{
@@ -373,6 +427,7 @@ decode_mips_operand (const char *p)
#define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 ASE_DSP
#define D33 ASE_DSPR2
+#define D37 ASE_DSPR6
#define D64 ASE_DSP64
/* MIPS MT ASE support. */
@@ -394,6 +449,9 @@ decode_mips_operand (const char *p)
/* eXtended Physical Address (XPA) support. */
#define XPA ASE_XPA
+/* MXU support. */
+#define MXU ASE_MXU
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -1381,8 +1439,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, WR_1|RD_C0|LC, 0, I33, XPA, 0 },
{"mfhgc0", "t,G", 0x40600400, 0xffe007ff, WR_1|RD_C0|LC, 0, I33, IVIRT|XPA, 0 },
{"mfhgc0", "t,G,H", 0x40600400, 0xffe007f8, WR_1|RD_C0|LC, 0, I33, IVIRT|XPA, 0 },
+{"mfc1", "t,S", 0x44000002, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, 0, MXU, 0 },
+{"mfc1", "t,G", 0x44000002, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, 0, MXU, 0 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 },
+{"mfhc1", "t,S", 0x44600002, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, 0, MXU, 0 },
+{"mfhc1", "t,G", 0x44600002, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, 0, MXU, 0 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 },
{"mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 },
/* mfc2 is at the bottom of the table. */
@@ -1479,8 +1541,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I33, XPA, 0 },
{"mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I33, IVIRT|XPA, 0 },
{"mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I33, IVIRT|XPA, 0 },
+{"mtc1", "t,S", 0x44800002, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, 0, MXU, 0 },
+{"mtc1", "t,G", 0x44800002, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, 0, MXU, 0 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 },
+{"mthc1", "t,S", 0x44e00002, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, 0, MXU, 0 },
+{"mthc1", "t,G", 0x44e00002, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, 0, MXU, 0 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 },
{"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 },
/* mtc2 is at the bottom of the table. */
@@ -2137,6 +2203,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 },
{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 },
+{"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D37, 0 },
{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 },
{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 },
{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 },
@@ -3138,6 +3205,134 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|CM, 0, 0, MSA, 0 },
{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+/* MXU Extension. */
+{"d16mul", "`=,`b,`c,`d,`o", 0x70000008, 0xff00003f, TRAP, 0, 0, MXU, 0 },
+{"d16mulf", "`=,`b,`c,`o", 0x70000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 },
+{"d16mule", "`=,`b,`c,`o", 0x71000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 },
+{"d16mac", "`=,`b,`c,`d,`a,`o", 0x7000000a, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"d16macf", "`=,`b,`c,`d,`a,`o", 0x7000000b, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"d16madl", "`=,`b,`c,`d,`a,`o", 0x7000000c, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s16mad", "`=,`b,`c,`d,`A,`o", 0x7000000d, 0xfe00003f, TRAP, 0, 0, MXU, 0 },
+{"q16add", "`=,`b,`c,`d,`a,`o", 0x7000000e, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"d16mace", "`=,`b,`c,`d,`a,`o", 0x7000000f, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+
+{"q8mul", "`=,`b,`c,`d", 0x70000038, 0xffc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8mulsu", "`=,`b,`c,`d", 0x70800038, 0xffc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8movz", "`=,`b,`c", 0x70000039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8movn", "`=,`b,`c", 0x70040039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16movz", "`=,`b,`c", 0x70080039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16movn", "`=,`b,`c", 0x700c0039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32movz", "`=,`b,`c", 0x70100039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32movn", "`=,`b,`c", 0x70140039, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8mac", "`=,`b,`c,`d,`a", 0x7000003a, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8macsu", "`=,`b,`c,`d,`a", 0x7080003a, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q16scop", "`=,`b,`c,`d", 0x7000003b, 0xffc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8madl", "`=,`b,`c,`d,`a", 0x7000003c, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"s32sfl", "`=,`b,`c,`d,`E", 0x7000003d, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8sad", "`=,`b,`c,`d", 0x7000003e, 0xffc0003f, TRAP, 0, 0, MXU, 0 },
+
+{"d32add", "`=,`b,`c,`d,`a", 0x70000018, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"d32addc", "`=,`b,`c,`d", 0x70400018, 0xffc0003f, TRAP, 0, 0, MXU, 0 },
+{"d32acc", "`=,`b,`c,`d,`a", 0x70000019, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"d32accm", "`=,`b,`c,`d,`a", 0x70400019, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"d32asum", "`=,`b,`c,`d,`a", 0x70800019, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q16acc", "`=,`b,`c,`d,`a", 0x7000001b, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q16accm", "`=,`b,`c,`d,`a", 0x7040001b, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"d16asum", "`=,`b,`c,`d,`a", 0x7080001b, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"q8adde", "`=,`b,`c,`d,`a", 0x7000001c, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+{"d8sum", "`=,`b,`c", 0x7040001c, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d8sumc", "`=,`b,`c", 0x7080001c, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8acce", "`=,`b,`c,`d,`a", 0x7000001d, 0xfcc0003f, TRAP, 0, 0, MXU, 0 },
+
+{"s32cps", "`=,`b,`c", 0x70000007, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16cps", "`=,`b,`c", 0x70080007, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8abd", "`=,`b,`c", 0x70100007, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q16sat", "`=,`b,`c", 0x70180007, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+
+{"s32slt", "`=,`b,`c", 0x70000006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16slt", "`=,`b,`c", 0x70040006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16avg", "`=,`b,`c", 0x70080006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16avgr", "`=,`b,`c", 0x700c0006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8avg", "`=,`b,`c", 0x70100006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8avgr", "`=,`b,`c", 0x70140006, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8add", "`=,`b,`c,`a", 0x701c0006, 0xfcfc003f, TRAP, 0, 0, MXU, 0 },
+
+{"s32max", "`=,`b,`c", 0x70000003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32min", "`=,`b,`c", 0x70040003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16max", "`=,`b,`c", 0x70080003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"d16min", "`=,`b,`c", 0x700c0003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8max", "`=,`b,`c", 0x70100003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8min", "`=,`b,`c", 0x70140003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8slt", "`=,`b,`c", 0x70180003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"q8sltu", "`=,`b,`c", 0x701c0003, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+
+{"d32sll", "`=,`b,`c,`d,`f", 0x70000030, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"d32slr", "`=,`b,`c,`d,`f", 0x70000031, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"d32sarl", "`=,`b,`c,`f", 0x70000032, 0xfc3c003f, TRAP, 0, 0, MXU, 0 },
+{"d32sar", "`=,`b,`c,`d,`f", 0x70000033, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"q16sll", "`=,`b,`c,`d,`f", 0x70000034, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"q16slr", "`=,`b,`c,`d,`f", 0x70000035, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"q16sar", "`=,`b,`c,`d,`f", 0x70000037, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+
+{"d32sllv", "`b,`c,s", 0x70000036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+{"d32slrv", "`b,`c,s", 0x70040036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+{"d32sarv", "`b,`c,s", 0x700c0036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+{"q16sllv", "`b,`c,s", 0x70100036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+{"q16slrv", "`b,`c,s", 0x70140036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+{"q16sarv", "`b,`c,s", 0x701c0036, 0xfc1c03ff, TRAP, 0, 0, MXU, 0 },
+
+{"s32madd", "`=,`b,s,t", 0x70008000, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32maddu", "`=,`b,s,t", 0x70008001, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32msub", "`=,`b,s,t", 0x70008004, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32msubu", "`=,`b,s,t", 0x70008005, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32mul", "`=,`b,s,t", 0x70000026, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32mulu", "`=,`b,s,t", 0x70004026, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32extr", "`=,`b,s,`T", 0x70008026, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+{"s32extrv", "`=,`b,s,t", 0x7000c026, 0xfc00c03f, TRAP, 0, 0, MXU, 0 },
+
+{"d32sarw", "`=,`b,`c,s", 0x70000027, 0xfc1c003f, TRAP, 0, 0, MXU, 0 },
+{"s32aln", "`=,`b,`c,s", 0x70040027, 0xfc1c003f, TRAP, 0, 0, MXU, 0 },
+{"s32alni", "`=,`b,`c,`S", 0x70080027, 0xfc7c003f, TRAP, 0, 0, MXU, 0 },
+{"s32lui", "`=,`B,`O", 0x700c0027, 0xfc7c003f, TRAP, 0, 0, MXU, 0 },
+{"s32lui", "`=,`U,`O", 0x700c0027, 0xfc7c003f, TRAP, 0, 0, MXU, 0 },
+{"s32nor", "`=,`b,`c", 0x70100027, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32and", "`=,`b,`c", 0x70140027, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32or", "`=,`b,`c", 0x70180027, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+{"s32xor", "`=,`b,`c", 0x701c0027, 0xfffc003f, TRAP, 0, 0, MXU, 0 },
+
+{"lxb", "d,s,t,`R", 0x70000028, 0xfc0001ff, TRAP, 0, 0, MXU, 0 },
+{"lxbu", "d,s,t,`R", 0x70000128, 0xfc0001ff, TRAP, 0, 0, MXU, 0 },
+{"lxh", "d,s,t,`R", 0x70000068, 0xfc0001ff, TRAP, 0, 0, MXU, 0 },
+{"lxhu", "d,s,t,`R", 0x70000168, 0xfc0001ff, TRAP, 0, 0, MXU, 0 },
+{"lxw", "d,s,t,`R", 0x700000e8, 0xfc0001ff, TRAP, 0, 0, MXU, 0 },
+{"s16ldd", "`=,s,`I,`P", 0x7000002a, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s16std", "`=,s,`I,`p", 0x7000002b, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s16ldi", "`=,s,`I,`P", 0x7000002c, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s16sdi", "`=,s,`I,`p", 0x7000002d, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s32m2i", "`m,t", 0x7000002e, 0xffe0f83f, TRAP, 0, 0, MXU, 0 },
+{"s32i2m", "`m,t", 0x7000002f, 0xffe0f83f, TRAP, 0, 0, MXU, 0 },
+
+{"s32lddv", "`=,s,t,`r", 0x70000012, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32lddvr", "`=,s,t,`r", 0x70000412, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32stdv", "`=,s,t,`r", 0x70000013, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32stdvr", "`=,s,t,`r", 0x70000413, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32ldiv", "`=,s,t,`r", 0x70000016, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32ldivr", "`=,s,t,`r", 0x70000416, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32sdiv", "`=,s,t,`r", 0x70000017, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32sdivr", "`=,s,t,`r", 0x70000417, 0xfc003c3f, TRAP, 0, 0, MXU, 0 },
+{"s32ldd", "`=,s,`i", 0x70000010, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32lddr", "`=,s,`i", 0x70100010, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32std", "`=,s,`i", 0x70000011, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32stdr", "`=,s,`i", 0x70100011, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32ldi", "`=,s,`i", 0x70000014, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32ldir", "`=,s,`i", 0x70100014, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32sdi", "`=,s,`i", 0x70000015, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s32sdir", "`=,s,`i", 0x70100015, 0xfc10003f, TRAP, 0, 0, MXU, 0 },
+{"s8ldd", "`=,s,`B,`e", 0x70000022, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s8std", "`=,s,`B,`g", 0x70000023, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s8ldi", "`=,s,`B,`e", 0x70000024, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+{"s8sdi", "`=,s,`B,`g", 0x70000025, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
+
/* User Defined Instruction. */
{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
@@ -3247,6 +3442,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"jic", "t,j", 0xd8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 },
{"bnezc", "-s,+\"", 0xf8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 },
+{"jalrc", "t", 0xf8000000, 0xffe0ffff, RD_1|NODS, 0, I37, 0, 0 },
{"jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 },
{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },