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authorSteve Ellcey <Steve.Ellcey@imgtec.com>2014-12-18 10:41:50 -0800
committerSteve Ellcey <Steve.Ellcey@imgtec.com>2014-12-18 10:41:50 -0800
commitb3e9a4171187f64c03d1858c2c840113df6b02de (patch)
tree24ed906374d33eabcbd3cfccc5d5b6ea9b4f5f51 /binutils-2.25/include
parentbbff162609624c737f72b070e2b53aeb5ed1e958 (diff)
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Add MIPS specific changes to binutils 2.25 (prerelease) for MIPSR6 bug fixes,
MXU support, and a fix to needed by gdbserver.
Diffstat (limited to 'binutils-2.25/include')
-rw-r--r--binutils-2.25/include/elf/mips.h3
-rw-r--r--binutils-2.25/include/opcode/mips.h27
2 files changed, 27 insertions, 3 deletions
diff --git a/binutils-2.25/include/elf/mips.h b/binutils-2.25/include/elf/mips.h
index 2ed6acd2..a76dae74 100644
--- a/binutils-2.25/include/elf/mips.h
+++ b/binutils-2.25/include/elf/mips.h
@@ -1224,7 +1224,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */
#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */
#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
-#define AFL_ASE_MASK 0x00001fff /* All ASEs. */
+#define AFL_ASE_DSPR6 0x00002000 /* DSP R6 ASE. */
+#define AFL_ASE_MASK 0x00003fff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
diff --git a/binutils-2.25/include/opcode/mips.h b/binutils-2.25/include/opcode/mips.h
index ef261674..28826997 100644
--- a/binutils-2.25/include/opcode/mips.h
+++ b/binutils-2.25/include/opcode/mips.h
@@ -427,7 +427,10 @@ enum mips_operand_type {
OP_CHECK_PREV,
/* A register operand that must not be zero. */
- OP_NON_ZERO_REG
+ OP_NON_ZERO_REG,
+
+ OP_MAPPED_STRING,
+ OP_MXU_STRIDE
};
/* Enumerates the types of MIPS register. */
@@ -474,7 +477,11 @@ enum mips_reg_operand_type {
OP_REG_MSA,
/* MSA control registers $0-$31. */
- OP_REG_MSA_CTRL
+ OP_REG_MSA_CTRL,
+
+ OP_REG_MXU,
+
+ OP_REG_MXU_GP
};
/* Base class for all operands. */
@@ -527,6 +534,12 @@ struct mips_mapped_int_operand
bfd_boolean print_hex;
};
+struct mips_mapped_string_operand
+{
+ struct mips_operand root;
+ const char ** strings;
+ int allow_constants;
+};
/* An operand that encodes the most significant bit position of a bitfield.
Given a bitfield that spans bits [MSB, LSB], some operands of this type
encode MSB directly while others encode MSB - LSB. Each operand of this
@@ -993,6 +1006,11 @@ struct mips_opcode
following), for quick reference when adding more:
"AB"
"abdstuvwxy"
+
+ Extension character sequences used so far ("`" followed by the
+ following), for quick reference when adding more:
+ "ABEIOPTRSU"
+ "abcdefgimopr"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -1102,6 +1120,8 @@ struct mips_opcode
#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
/* Instruction has a forbidden slot. */
#define INSN2_FORBIDDEN_SLOT 0x00008000
+/* This indicates pre-R6 instructions mapped to R6 ones. */
+#define INSN2_CONVERTED_TO_COMPACT 0x00010000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
@@ -1255,6 +1275,9 @@ static const unsigned int mips_isa_table[] = {
#define ASE_MSA64 0x00001000
/* eXtended Physical Address (XPA) Extension. */
#define ASE_XPA 0x00002000
+/* MXU Extension. */
+#define ASE_MXU 0x00004000
+#define ASE_DSPR6 0x00008000
/* MIPS ISA defines, use instead of hardcoding ISA level. */