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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 13:02:08 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 13:02:08 +0000 |
| commit | 421dcc59212a73b82141caa2c94ea340a7b34deb (patch) | |
| tree | 81e5df49bee43b0e171a07917f9124da1dacd823 /lib | |
| parent | 930f2b51084c6dac1238b8b0f8dd11f40f619694 (diff) | |
| download | external_llvm-421dcc59212a73b82141caa2c94ea340a7b34deb.tar.gz external_llvm-421dcc59212a73b82141caa2c94ea340a7b34deb.tar.bz2 external_llvm-421dcc59212a73b82141caa2c94ea340a7b34deb.zip | |
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
This covers the case where fmax_a can be used to implement ISD::FABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 14 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 1 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index d0dbb15211..959c05aa0a 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -2946,6 +2946,20 @@ def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr), def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr), (ST_D MSA128D:$ws, addrRegImm:$addr)>; +class MSA_FABS_PSEUDO_DESC_BASE<RegisterClass RCWD, RegisterClass RCWS = RCWD, + InstrItinClass itin = NoItinerary> : + MipsPseudo<(outs RCWD:$wd), + (ins RCWS:$ws), + [(set RCWD:$wd, (fabs RCWS:$ws))]> { + InstrItinClass Itinerary = itin; +} +def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128W>, + PseudoInstExpansion<(FMAX_A_W MSA128W:$wd, MSA128W:$ws, + MSA128W:$ws)>; +def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128D>, + PseudoInstExpansion<(FMAX_A_D MSA128D:$wd, MSA128D:$ws, + MSA128D:$ws)>; + class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : MSAPat<(DstVT (bitconvert SrcVT:$src)), diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index ef2217c56a..30774540ee 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -206,6 +206,7 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); if (Ty != MVT::v8f16) { + setOperationAction(ISD::FABS, Ty, Legal); setOperationAction(ISD::FADD, Ty, Legal); setOperationAction(ISD::FDIV, Ty, Legal); setOperationAction(ISD::FLOG2, Ty, Legal); |