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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:45:36 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-24 12:45:36 +0000 |
| commit | 930f2b51084c6dac1238b8b0f8dd11f40f619694 (patch) | |
| tree | 0849acd2079d936ad9a3bada070be73a90238acb /lib | |
| parent | c998bc98439e21bc8c3838d6353475eacfb8494e (diff) | |
| download | external_llvm-930f2b51084c6dac1238b8b0f8dd11f40f619694.tar.gz external_llvm-930f2b51084c6dac1238b8b0f8dd11f40f619694.tar.bz2 external_llvm-930f2b51084c6dac1238b8b0f8dd11f40f619694.zip | |
[mips][msa] Line wrapping.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191295 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index a4c9cb1f1f..d0dbb15211 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1764,8 +1764,8 @@ class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w, MSA128W>; class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, MSA128D>; class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, - ValueType TyNode, RegisterClass RCWD, - Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm, + ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem, + ComplexPattern Addr = addrRegImm, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs RCWD:$wd); dag InOperandList = (ins MemOpnd:$addr); @@ -2059,8 +2059,8 @@ class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w, MSA128W>; class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d, MSA128D>; class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, - ValueType TyNode, RegisterClass RCWD, - Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm, + ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem, + ComplexPattern Addr = addrRegImm, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr); |