Add facility for pre-RA passes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50165 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 12 insertions, 1 deletions

diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 5c721a685c..7c86a8d7db 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -280,7 +280,14 @@ public:
   virtual bool addInstSelector(PassManagerBase &PM, bool Fast) {
     return true;
   }
-  
+
+  /// addPreRegAllocPasses - This method may be implemented by targets that want
+  /// to run passes immediately before register allocation. This should return
+  /// true if -print-machineinstrs should print after these passes.
+  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast) {
+    return false;
+  }
+
   /// addPostRegAllocPasses - This method may be implemented by targets that
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index c65a6b9a79..3927eee503 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -94,6 +94,10 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (EnableSinking)
     PM.add(createMachineSinkingPass());
 
+  // Run pre-ra passes.
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());